HK1120876A1 - Integrated circuit and method for performing masked store operations in a processor - Google Patents

Integrated circuit and method for performing masked store operations in a processor

Info

Publication number
HK1120876A1
HK1120876A1 HK08112358.3A HK08112358A HK1120876A1 HK 1120876 A1 HK1120876 A1 HK 1120876A1 HK 08112358 A HK08112358 A HK 08112358A HK 1120876 A1 HK1120876 A1 HK 1120876A1
Authority
HK
Hong Kong
Prior art keywords
processor
integrated circuit
store operations
masked store
performing masked
Prior art date
Application number
HK08112358.3A
Other languages
English (en)
Inventor
Mark Taunton
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Publication of HK1120876A1 publication Critical patent/HK1120876A1/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
  • Devices For Executing Special Programs (AREA)
HK08112358.3A 2006-12-22 2008-11-11 Integrated circuit and method for performing masked store operations in a processor HK1120876A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/643,999 US7921263B2 (en) 2006-12-22 2006-12-22 System and method for performing masked store operations in a processor

Publications (1)

Publication Number Publication Date
HK1120876A1 true HK1120876A1 (en) 2009-04-09

Family

ID=39243717

Family Applications (1)

Application Number Title Priority Date Filing Date
HK08112358.3A HK1120876A1 (en) 2006-12-22 2008-11-11 Integrated circuit and method for performing masked store operations in a processor

Country Status (6)

Country Link
US (1) US7921263B2 (fr)
EP (1) EP1939727A3 (fr)
KR (1) KR100956970B1 (fr)
CN (1) CN101206635B (fr)
HK (1) HK1120876A1 (fr)
TW (1) TWI410865B (fr)

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US7610472B2 (en) * 2005-06-05 2009-10-27 Apple Inc. Performing variable and/or bitwise shift operation for a shift instruction that does not provide a variable or bitwise shift option
US7921263B2 (en) 2006-12-22 2011-04-05 Broadcom Corporation System and method for performing masked store operations in a processor
US8732437B2 (en) * 2010-01-26 2014-05-20 Oracle America, Inc. Low-overhead misalignment and reformatting support for SIMD
CN103827815B (zh) * 2011-09-26 2017-11-28 英特尔公司 用于提供利用跨越和掩码功能的向量加载和存储的指令和逻辑
CN103988173B (zh) * 2011-11-25 2017-04-05 英特尔公司 用于提供掩码寄存器与通用寄存器或存储器之间的转换的指令和逻辑
WO2013089709A1 (fr) * 2011-12-14 2013-06-20 Intel Corporation Système, appareil et procédé de génération d'un compte d'alignement de boucle ou d'un masque d'alignement de boucle
CN104011650B (zh) 2011-12-23 2017-09-19 英特尔公司 使用输入写掩码和立即数从源写掩码寄存器在目的地写掩码寄存器中设置输出掩码的系统、装置和方法
CN104025040B (zh) * 2011-12-23 2017-11-21 英特尔公司 用于混洗浮点或整数值的装置和方法
WO2013095609A1 (fr) * 2011-12-23 2013-06-27 Intel Corporation Systèmes, appareils et procédés pour effectuer une conversion d'un registre de masque en un registre vectoriel
US9354877B2 (en) 2011-12-23 2016-05-31 Intel Corporation Systems, apparatuses, and methods for performing mask bit compression
US20140019718A1 (en) * 2012-07-10 2014-01-16 Shihjong J. Kuo Vectorized pattern searching
US9170811B2 (en) * 2013-01-09 2015-10-27 King Fahd University Of Petroleum And Minerals Structured control instruction fetch unit
US9888077B2 (en) * 2014-04-22 2018-02-06 Western Digital Technologies, Inc. Metadata based data alignment in data storage systems
KR101649828B1 (ko) * 2015-07-30 2016-08-19 엘에스산전 주식회사 이더넷 프레임 감지 장치 그의 동작 방법
US9875214B2 (en) 2015-07-31 2018-01-23 Arm Limited Apparatus and method for transferring a plurality of data structures between memory and a plurality of vector registers
WO2019000456A1 (fr) * 2017-06-30 2019-01-03 华为技术有限公司 Procédé de transmission de masque de données, dispositif de commande de mémoire, puce mémoire et système informatique
CN114510271B (zh) * 2022-02-09 2023-08-15 海飞科(南京)信息技术有限公司 用于在单指令多线程计算系统中加载数据的方法和装置
US12014183B2 (en) * 2022-09-21 2024-06-18 Intel Corporation Base plus offset addressing for load/store messages
US20240111526A1 (en) * 2022-09-30 2024-04-04 Advanced Micro Devices, Inc. Methods and apparatus for providing mask register optimization for vector operations
CN116150058B (zh) * 2023-04-17 2023-06-23 合肥芯荣微电子有限公司 一种基于axi总线的并发传输模块和方法

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US6058473A (en) * 1993-11-30 2000-05-02 Texas Instruments Incorporated Memory store from a register pair conditional upon a selected status bit
US6035369A (en) * 1995-10-19 2000-03-07 Rambus Inc. Method and apparatus for providing a memory with write enable information
US5703810A (en) * 1995-12-15 1997-12-30 Silicon Graphics, Inc. DRAM for texture mapping
US5867444A (en) * 1997-09-25 1999-02-02 Compaq Computer Corporation Programmable memory device that supports multiple operational modes
US6122189A (en) * 1998-10-02 2000-09-19 Rambus Inc. Data packet with embedded mask
US7529907B2 (en) * 1998-12-16 2009-05-05 Mips Technologies, Inc. Method and apparatus for improved computer load and store operations
US6820195B1 (en) * 1999-10-01 2004-11-16 Hitachi, Ltd. Aligning load/store data with big/little endian determined rotation distance control
AU2001226324A1 (en) 2000-01-18 2001-07-31 Clearwater Networks, Inc. Method and apparatus for improved computer load and store operations
DE10127194B4 (de) * 2001-06-05 2008-08-21 Infineon Technologies Ag Verfahren und Vorrichtung zum Ausblenden von nicht funktionstüchtigen Speicherzellen
US7051168B2 (en) * 2001-08-28 2006-05-23 International Business Machines Corporation Method and apparatus for aligning memory write data in a microprocessor
US6826663B2 (en) * 2003-01-13 2004-11-30 Rambus Inc. Coded write masking
JP4717798B2 (ja) * 2003-01-13 2011-07-06 ラムバス・インコーポレーテッド 符号化書き込みマスキング
US7610466B2 (en) * 2003-09-05 2009-10-27 Freescale Semiconductor, Inc. Data processing system using independent memory and register operand size specifiers and method thereof
US7921263B2 (en) 2006-12-22 2011-04-05 Broadcom Corporation System and method for performing masked store operations in a processor

Also Published As

Publication number Publication date
CN101206635B (zh) 2011-11-30
US7921263B2 (en) 2011-04-05
US20080155210A1 (en) 2008-06-26
EP1939727A2 (fr) 2008-07-02
TWI410865B (zh) 2013-10-01
KR20080059106A (ko) 2008-06-26
KR100956970B1 (ko) 2010-05-11
TW200842702A (en) 2008-11-01
CN101206635A (zh) 2008-06-25
EP1939727A3 (fr) 2008-10-22

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Legal Events

Date Code Title Description
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20171206