HK1042374A1 - 記憶陣列組織 - Google Patents

記憶陣列組織

Info

Publication number
HK1042374A1
HK1042374A1 HK02103244.6A HK02103244A HK1042374A1 HK 1042374 A1 HK1042374 A1 HK 1042374A1 HK 02103244 A HK02103244 A HK 02103244A HK 1042374 A1 HK1042374 A1 HK 1042374A1
Authority
HK
Hong Kong
Prior art keywords
memory array
array organization
organization
memory
array
Prior art date
Application number
HK02103244.6A
Other languages
English (en)
Inventor
S Tetrick Raymond
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of HK1042374A1 publication Critical patent/HK1042374A1/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1028—Adjacent errors, e.g. error in n-bit (n>1) wide storage units, i.e. package error

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
HK02103244.6A 1998-12-30 2002-04-30 記憶陣列組織 HK1042374A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US22318498A 1998-12-30 1998-12-30
PCT/US1999/028177 WO2000041182A1 (en) 1998-12-30 1999-11-30 Memory array organization

Publications (1)

Publication Number Publication Date
HK1042374A1 true HK1042374A1 (zh) 2002-08-09

Family

ID=22835413

Family Applications (1)

Application Number Title Priority Date Filing Date
HK02103244.6A HK1042374A1 (zh) 1998-12-30 2002-04-30 記憶陣列組織

Country Status (5)

Country Link
US (1) US6598199B2 (zh)
EP (1) EP1153395A4 (zh)
AU (1) AU1634600A (zh)
HK (1) HK1042374A1 (zh)
WO (1) WO2000041182A1 (zh)

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US7197575B2 (en) * 1997-12-17 2007-03-27 Src Computers, Inc. Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers
US20040236877A1 (en) * 1997-12-17 2004-11-25 Lee A. Burton Switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module format (FB-DIMM)
US7424552B2 (en) * 1997-12-17 2008-09-09 Src Computers, Inc. Switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element and one or more dense logic devices
US7373440B2 (en) * 1997-12-17 2008-05-13 Src Computers, Inc. Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format
US7565461B2 (en) * 1997-12-17 2009-07-21 Src Computers, Inc. Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers
US6691276B2 (en) * 2001-06-25 2004-02-10 Intel Corporation Method for detecting and correcting failures in a memory system
US20030163769A1 (en) * 2002-02-27 2003-08-28 Sun Microsystems, Inc. Memory module including an error detection mechanism for address and control signals
US6941493B2 (en) * 2002-02-27 2005-09-06 Sun Microsystems, Inc. Memory subsystem including an error detection mechanism for address and control signals
US6996766B2 (en) * 2002-06-28 2006-02-07 Sun Microsystems, Inc. Error detection/correction code which detects and corrects a first failing component and optionally a second failing component
US6973613B2 (en) * 2002-06-28 2005-12-06 Sun Microsystems, Inc. Error detection/correction code which detects and corrects component failure and which provides single bit error correction subsequent to component failure
US6976194B2 (en) 2002-06-28 2005-12-13 Sun Microsystems, Inc. Memory/Transmission medium failure handling controller and method
US6996686B2 (en) * 2002-12-23 2006-02-07 Sun Microsystems, Inc. Memory subsystem including memory modules having multiple banks
US7505890B2 (en) * 2003-01-15 2009-03-17 Cox Communications, Inc. Hard disk drive emulator
US7779285B2 (en) * 2003-02-18 2010-08-17 Oracle America, Inc. Memory system including independent isolated power for each memory module
US7530008B2 (en) * 2003-08-08 2009-05-05 Sun Microsystems, Inc. Scalable-chip-correct ECC scheme
US7188296B1 (en) 2003-10-30 2007-03-06 Sun Microsystems, Inc. ECC for component failures using Galois fields
US7581154B2 (en) 2005-06-30 2009-08-25 Intel Corporation Method and apparatus to lower operating voltages for memory arrays using error correcting codes
US7447941B2 (en) * 2005-07-19 2008-11-04 Hewlett-Packard Development Company, L.P. Error recovery systems and methods for execution data paths
US7558992B2 (en) * 2005-10-10 2009-07-07 Intel Corporation Reducing the soft error vulnerability of stored data
US7683480B2 (en) * 2006-03-29 2010-03-23 Freescale Semiconductor, Inc. Methods and apparatus for a reduced inductance wirebond array
DE102006016499B4 (de) * 2006-04-07 2014-11-13 Qimonda Ag Speichermodulsteuerung, Speichersteuerung und entsprechende Speicheranordnung sowie Verfahren zur Fehlerkorrektur
KR20080080882A (ko) * 2007-03-02 2008-09-05 삼성전자주식회사 Ｅｃｃ용 레이어를 구비하는 다층 구조 반도체 메모리 장치및 이를 이용하는 에러 검출 및 정정 방법
US8166229B2 (en) * 2008-06-30 2012-04-24 Intel Corporation Apparatus and method for multi-level cache utilization
US8321761B1 (en) * 2009-09-28 2012-11-27 Nvidia Corporation ECC bits used as additional register file storage
US8327225B2 (en) 2010-01-04 2012-12-04 Micron Technology, Inc. Error correction in a stacked memory
US10120749B2 (en) 2016-09-30 2018-11-06 Intel Corporation Extended application of error checking and correction code in memory
US10705912B2 (en) 2017-06-07 2020-07-07 Rambus Inc. Energy efficient storage of error-correction-detection information

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US6061263A (en) 1998-12-29 2000-05-09 Intel Corporation Small outline rambus in-line memory module

Also Published As

Publication number Publication date
EP1153395A4 (en) 2002-04-17
US20010001158A1 (en) 2001-05-10
US6598199B2 (en) 2003-07-22
WO2000041182A1 (en) 2000-07-13
EP1153395A1 (en) 2001-11-14
AU1634600A (en) 2000-07-24

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