HK1039986A1 - 設有可編程阻延的uart自動半雙工方向控制 - Google Patents

設有可編程阻延的uart自動半雙工方向控制

Info

Publication number
HK1039986A1
HK1039986A1 HK02101172.6A HK02101172A HK1039986A1 HK 1039986 A1 HK1039986 A1 HK 1039986A1 HK 02101172 A HK02101172 A HK 02101172A HK 1039986 A1 HK1039986 A1 HK 1039986A1
Authority
HK
Hong Kong
Prior art keywords
direction control
programmable delay
duplex direction
automatic half
uart
Prior art date
Application number
HK02101172.6A
Other languages
English (en)
Inventor
Man Lo Sun
Wegner Glenn
Original Assignee
Exar Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Exar Corp filed Critical Exar Corp
Publication of HK1039986A1 publication Critical patent/HK1039986A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Communication Control (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
HK02101172.6A 2000-03-17 2002-02-18 設有可編程阻延的uart自動半雙工方向控制 HK1039986A1 (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/527,634 US6865626B1 (en) 2000-03-17 2000-03-17 UART automatic half-duplex direction control with programmable delay

Publications (1)

Publication Number Publication Date
HK1039986A1 true HK1039986A1 (zh) 2002-05-17

Family

ID=24102305

Family Applications (1)

Application Number Title Priority Date Filing Date
HK02101172.6A HK1039986A1 (zh) 2000-03-17 2002-02-18 設有可編程阻延的uart自動半雙工方向控制

Country Status (6)

Country Link
US (1) US6865626B1 (zh)
EP (1) EP1134666B1 (zh)
KR (1) KR100648631B1 (zh)
DE (2) DE60032730T2 (zh)
HK (1) HK1039986A1 (zh)
TW (1) TW490614B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3668697B2 (ja) * 2001-04-09 2005-07-06 三菱電機株式会社 データ送信方法及びデータ送信装置
FR2830953A1 (fr) 2001-10-15 2003-04-18 St Microelectronics Sa Dispositif de synchronisation a chaud d'un recepteur de trames asynchrones
TWI371948B (en) 2007-06-07 2012-09-01 Microelectronics Tech Inc System of satellite signal down conversion and reception and signal transmission method thereof

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5241660A (en) * 1986-10-30 1993-08-31 National Semiconductor Corporation Buffered asynchronous communications element with receive/transmit control and status reporting
US5140679A (en) * 1988-09-14 1992-08-18 National Semiconductor Corporation Universal asynchronous receiver/transmitter
US5619681A (en) * 1992-11-23 1997-04-08 Zilog, Inc. Delayed FIFO status for serial shift emulation
US5619544A (en) * 1994-06-03 1997-04-08 Texas Instruments Incorporated Universal asynchronous receive/transmit circuit with flow control
US5884099A (en) * 1996-05-31 1999-03-16 Sun Microsystems, Inc. Control circuit for a buffer memory to transfer data between systems operating at different speeds
US5983017A (en) * 1996-11-12 1999-11-09 Lsi Logic Corporation Virtual monitor debugging method and apparatus
US5892927A (en) 1997-01-08 1999-04-06 Intel Corporation Bus delay compensation circuitry
US6212609B1 (en) * 1997-06-30 2001-04-03 Intel Corporation Alternate access mechanism for saving and restoring state of read-only register
GB9805482D0 (en) * 1998-03-13 1998-05-13 Sgs Thomson Microelectronics Microcomputer
US6363501B1 (en) * 1998-12-10 2002-03-26 Advanced Micro Devices, Inc. Method and apparatus for saving and loading peripheral device states of a microcontroller via a scan path
US6381661B1 (en) * 1999-05-28 2002-04-30 3Com Corporation High throughput UART to DSP interface having Dual transmit and receive FIFO buffers to support data transfer between a host computer and an attached modem
US6381703B1 (en) * 1999-08-04 2002-04-30 Qualcomm Incorporated Guaranteeing clock slew correction in point-to-point protocol packet detection without data loss after baud rate detection in autobaud mode

Also Published As

Publication number Publication date
US6865626B1 (en) 2005-03-08
EP1134666B1 (en) 2007-01-03
KR100648631B1 (ko) 2006-11-24
DE1134666T1 (de) 2002-04-18
EP1134666A2 (en) 2001-09-19
DE60032730D1 (de) 2007-02-15
DE60032730T2 (de) 2007-11-08
EP1134666A3 (en) 2004-02-25
TW490614B (en) 2002-06-11
KR20010091865A (ko) 2001-10-23

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