HK1037413A1 - Computer processor with a replay system - Google Patents

Computer processor with a replay system

Info

Publication number
HK1037413A1
HK1037413A1 HK01108212A HK01108212A HK1037413A1 HK 1037413 A1 HK1037413 A1 HK 1037413A1 HK 01108212 A HK01108212 A HK 01108212A HK 01108212 A HK01108212 A HK 01108212A HK 1037413 A1 HK1037413 A1 HK 1037413A1
Authority
HK
Hong Kong
Prior art keywords
computer processor
replay system
replay
processor
computer
Prior art date
Application number
HK01108212A
Other languages
English (en)
Inventor
Amit A Merchant
David J Sager
Darrell D Boggs
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of HK1037413A1 publication Critical patent/HK1037413A1/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Hardware Redundancy (AREA)
HK01108212A 1998-06-30 2001-11-21 Computer processor with a replay system HK1037413A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/106,857 US6163838A (en) 1996-11-13 1998-06-30 Computer processor with a replay system
PCT/US1999/013655 WO2000000886A1 (en) 1998-06-30 1999-06-21 Computer processor with a replay system

Publications (1)

Publication Number Publication Date
HK1037413A1 true HK1037413A1 (en) 2002-02-08

Family

ID=22313636

Family Applications (1)

Application Number Title Priority Date Filing Date
HK01108212A HK1037413A1 (en) 1998-06-30 2001-11-21 Computer processor with a replay system

Country Status (7)

Country Link
US (1) US6163838A (de)
CN (1) CN1126028C (de)
DE (1) DE19983330B4 (de)
GB (1) GB2354615B (de)
HK (1) HK1037413A1 (de)
TW (1) TW444180B (de)
WO (1) WO2000000886A1 (de)

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US6631454B1 (en) 1996-11-13 2003-10-07 Intel Corporation Processor and data cache with data storage unit and tag hit/miss logic operated at a first and second clock frequencies
US6256745B1 (en) 1998-06-05 2001-07-03 Intel Corporation Processor having execution core sections operating at different clock rates
US6385715B1 (en) 1996-11-13 2002-05-07 Intel Corporation Multi-threading for a processor utilizing a replay queue
US6665792B1 (en) * 1996-11-13 2003-12-16 Intel Corporation Interface to a memory system for a processor having a replay system
US6625756B1 (en) * 1997-12-19 2003-09-23 Intel Corporation Replay mechanism for soft error recovery
US6629271B1 (en) * 1999-12-28 2003-09-30 Intel Corporation Technique for synchronizing faults in a processor having a replay system
US6643767B1 (en) * 2000-01-27 2003-11-04 Kabushiki Kaisha Toshiba Instruction scheduling system of a processor
US6880069B1 (en) * 2000-06-30 2005-04-12 Intel Corporation Replay instruction morphing
US6880153B1 (en) * 2000-11-21 2005-04-12 Hewlett-Packard Development Company, L.P. Method and apparatus for varying the level of correctness checks executed when performing correctness checks opportunistically using spare instruction slots
US7203817B2 (en) * 2001-09-24 2007-04-10 Broadcom Corporation Power consumption reduction in a pipeline by stalling instruction issue on a load miss
US6912648B2 (en) * 2001-12-31 2005-06-28 Intel Corporation Stick and spoke replay with selectable delays
US6925550B2 (en) * 2002-01-02 2005-08-02 Intel Corporation Speculative scheduling of instructions with source operand validity bit and rescheduling upon carried over destination operand invalid bit detection
US6799257B2 (en) 2002-02-21 2004-09-28 Intel Corporation Method and apparatus to control memory accesses
US20040078558A1 (en) * 2002-03-25 2004-04-22 Sprangle Eric A. Method and apparatus to process instructions in a processor
US7984268B2 (en) * 2002-10-08 2011-07-19 Netlogic Microsystems, Inc. Advanced processor scheduling in a multithreaded system
US7653906B2 (en) * 2002-10-23 2010-01-26 Intel Corporation Apparatus and method for reducing power consumption on simultaneous multi-threading systems
TW591478B (en) 2002-11-12 2004-06-11 Mitac Technology Corp Apparatus and method of using personal computer to integrate functions of home electronics
US20040218351A1 (en) 2002-11-12 2004-11-04 Mitac Technology Corp. Method and apparatus for integrating personal computer and electronic device functions
US6986010B2 (en) * 2002-12-13 2006-01-10 Intel Corporation Cache lock mechanism with speculative allocation
US7080209B2 (en) * 2002-12-24 2006-07-18 Intel Corporation Method and apparatus for processing a load-lock instruction using a relaxed lock protocol
US20040123078A1 (en) * 2002-12-24 2004-06-24 Hum Herbert H Method and apparatus for processing a load-lock instruction using a scoreboard mechanism
US7529913B2 (en) * 2003-12-23 2009-05-05 Intel Corporation Late allocation of registers
US20050147036A1 (en) * 2003-12-30 2005-07-07 Intel Corporation Method and apparatus for enabling an adaptive replay loop in a processor
US7502912B2 (en) * 2003-12-30 2009-03-10 Intel Corporation Method and apparatus for rescheduling operations in a processor
JP2007026392A (ja) * 2005-07-21 2007-02-01 Toshiba Corp マイクロプロセッサ
US20070043930A1 (en) * 2005-08-16 2007-02-22 Hill Stephen J Performance of a data processing apparatus
US9529594B2 (en) * 2010-11-30 2016-12-27 Oracle International Corporation Miss buffer for a multi-threaded processor
WO2013188306A1 (en) 2012-06-15 2013-12-19 Soft Machines, Inc. Reordered speculative instruction sequences with a disambiguation-free out of order load store queue
EP2862069A4 (de) 2012-06-15 2016-12-28 Soft Machines Inc Anweisungsdefinition zur implementierung von lastspeicherumordnung und -optimierung
EP2862062B1 (de) 2012-06-15 2024-03-06 Intel Corporation Speicherwarteschlange für virtuelle last mit dynamischem versandfenster mit verteilter struktur
KR101818967B1 (ko) 2012-06-15 2018-01-16 인텔 코포레이션 명확화 없는 비순차 load store 큐
CN104823154B (zh) 2012-06-15 2017-12-29 英特尔公司 包括虚拟加载存储队列的处理器和系统
WO2013188701A1 (en) 2012-06-15 2013-12-19 Soft Machines, Inc. A method and system for implementing recovery from speculative forwarding miss-predictions/errors resulting from load store reordering and optimization
US9361103B2 (en) * 2012-11-02 2016-06-07 Advanced Micro Devices, Inc. Store replay policy
KR101837817B1 (ko) 2014-12-14 2018-03-12 비아 얼라이언스 세미컨덕터 씨오., 엘티디. 비순차 프로세서에서 페이지 워크에 따라 로드 리플레이를 억제하는 메커니즘
US10146540B2 (en) 2014-12-14 2018-12-04 Via Alliance Semiconductor Co., Ltd Apparatus and method to preclude load replays dependent on write combining memory space access in an out-of-order processor
KR101837816B1 (ko) 2014-12-14 2018-03-12 비아 얼라이언스 세미컨덕터 씨오., 엘티디. 비순차 프로세서에서 ｉ／ｏ­의존 로드 리플레이를 불가능하게 하는 메커니즘
US10114794B2 (en) 2014-12-14 2018-10-30 Via Alliance Semiconductor Co., Ltd Programmable load replay precluding mechanism
US10175984B2 (en) 2014-12-14 2019-01-08 Via Alliance Semiconductor Co., Ltd Apparatus and method to preclude non-core cache-dependent load replays in an out-of-order processor
KR101819316B1 (ko) 2014-12-14 2018-01-16 비아 얼라이언스 세미컨덕터 씨오., 엘티디. 비순차 프로세서에서 캐시 불가­의존 로드 리플레이를 억제하는 메커니즘
WO2016097814A1 (en) 2014-12-14 2016-06-23 Via Alliance Semiconductor Co., Ltd. Mechanism to preclude shared ram-dependent load replays in out-of-order processor
US10127046B2 (en) 2014-12-14 2018-11-13 Via Alliance Semiconductor Co., Ltd. Mechanism to preclude uncacheable-dependent load replays in out-of-order processor
US10083038B2 (en) 2014-12-14 2018-09-25 Via Alliance Semiconductor Co., Ltd Mechanism to preclude load replays dependent on page walks in an out-of-order processor
WO2016097797A1 (en) 2014-12-14 2016-06-23 Via Alliance Semiconductor Co., Ltd. Load replay precluding mechanism
US10114646B2 (en) 2014-12-14 2018-10-30 Via Alliance Semiconductor Co., Ltd Programmable load replay precluding mechanism
WO2016097815A1 (en) * 2014-12-14 2016-06-23 Via Alliance Semiconductor Co., Ltd. Apparatus and method to preclude x86 special bus cycle load replays in out-of-order processor
US10108421B2 (en) 2014-12-14 2018-10-23 Via Alliance Semiconductor Co., Ltd Mechanism to preclude shared ram-dependent load replays in an out-of-order processor
WO2016097811A1 (en) 2014-12-14 2016-06-23 Via Alliance Semiconductor Co., Ltd. Mechanism to preclude load replays dependent on fuse array access in out-of-order processor
US9804845B2 (en) 2014-12-14 2017-10-31 Via Alliance Semiconductor Co., Ltd. Apparatus and method to preclude X86 special bus cycle load replays in an out-of-order processor
US10088881B2 (en) 2014-12-14 2018-10-02 Via Alliance Semiconductor Co., Ltd Mechanism to preclude I/O-dependent load replays in an out-of-order processor
US10108420B2 (en) 2014-12-14 2018-10-23 Via Alliance Semiconductor Co., Ltd Mechanism to preclude load replays dependent on long load cycles in an out-of-order processor
US9703359B2 (en) 2014-12-14 2017-07-11 Via Alliance Semiconductor Co., Ltd. Power saving mechanism to reduce load replays in out-of-order processor
US10228944B2 (en) 2014-12-14 2019-03-12 Via Alliance Semiconductor Co., Ltd. Apparatus and method for programmable load replay preclusion
US10108430B2 (en) 2014-12-14 2018-10-23 Via Alliance Semiconductor Co., Ltd Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processor
US10120689B2 (en) 2014-12-14 2018-11-06 Via Alliance Semiconductor Co., Ltd Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processor
US10209996B2 (en) 2014-12-14 2019-02-19 Via Alliance Semiconductor Co., Ltd. Apparatus and method for programmable load replay preclusion
US10146539B2 (en) 2014-12-14 2018-12-04 Via Alliance Semiconductor Co., Ltd. Load replay precluding mechanism
JP6286067B2 (ja) 2014-12-14 2018-02-28 ヴィア アライアンス セミコンダクター カンパニー リミテッド アウトオブオーダープロセッサでの長いロードサイクルに依存するロードリプレイを除外するメカニズム
US10089112B2 (en) 2014-12-14 2018-10-02 Via Alliance Semiconductor Co., Ltd Mechanism to preclude load replays dependent on fuse array access in an out-of-order processor
WO2016097790A1 (en) 2014-12-14 2016-06-23 Via Alliance Semiconductor Co., Ltd. Apparatus and method to preclude non-core cache-dependent load replays in out-of-order processor
KR101819315B1 (ko) 2014-12-14 2018-01-16 비아 얼라이언스 세미컨덕터 씨오., 엘티디. 비순차 프로세서에서 작성 결합 메모리 공간 접근에 따라 로드 리플레이를 억제하기 위한 장치 및 방법
CN109032665B (zh) * 2017-06-09 2021-01-26 龙芯中科技术股份有限公司 微处理器中指令输出处理方法及装置
CN116450216B (zh) * 2023-06-12 2023-08-29 上海灵动微电子股份有限公司 共享硬件运算单元的局部缓存方法

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Also Published As

Publication number Publication date
DE19983330B4 (de) 2009-04-09
CN1126028C (zh) 2003-10-29
GB2354615B (en) 2003-03-19
DE19983330T1 (de) 2001-05-31
TW444180B (en) 2001-07-01
WO2000000886A1 (en) 2000-01-06
GB2354615A (en) 2001-03-28
CN1307700A (zh) 2001-08-08
US6163838A (en) 2000-12-19
GB0100244D0 (en) 2001-02-14

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Legal Events

Date Code Title Description
PF Patent in force
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20100621