HK1016025A1 - Superscalar microprocessor instruction pipeline including instruction dispatch and release control - Google Patents

Superscalar microprocessor instruction pipeline including instruction dispatch and release control

Info

Publication number
HK1016025A1
HK1016025A1 HK98114200.0A HK98114200A HK1016025A1 HK 1016025 A1 HK1016025 A1 HK 1016025A1 HK 98114200 A HK98114200 A HK 98114200A HK 1016025 A1 HK1016025 A1 HK 1016025A1
Authority
HK
Hong Kong
Prior art keywords
release control
pipeline including
superscalar microprocessor
dispatch
instruction
Prior art date
Application number
HK98114200.0A
Other languages
English (en)
Inventor
Joseph P Bratt
Peter Yan-Tek Hsu
Chandra S Joshi
Monica R Nofal
Paul Rodman
Joseph T Scanlon
Man Kit Tang
Original Assignee
Mips Tech Inc
Toshiba Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mips Tech Inc, Toshiba Kk filed Critical Mips Tech Inc
Publication of HK1016025A1 publication Critical patent/HK1016025A1/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/3822—Parallel decoding, e.g. parallel decode units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
HK98114200.0A 1993-12-15 1998-12-21 Superscalar microprocessor instruction pipeline including instruction dispatch and release control HK1016025A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16809493A 1993-12-15 1993-12-15
PCT/JP1994/002108 WO1995016952A1 (en) 1993-12-15 1994-12-15 Superscalar microprocessor instruction pipeline including instruction dispatch and release control

Publications (1)

Publication Number Publication Date
HK1016025A1 true HK1016025A1 (en) 1999-12-10

Family

ID=22610099

Family Applications (1)

Application Number Title Priority Date Filing Date
HK98114200.0A HK1016025A1 (en) 1993-12-15 1998-12-21 Superscalar microprocessor instruction pipeline including instruction dispatch and release control

Country Status (8)

Country Link
EP (1) EP0690372B1 (xx)
JP (1) JP2815236B2 (xx)
KR (1) KR0175116B1 (xx)
CN (1) CN1068445C (xx)
DE (1) DE69435278D1 (xx)
HK (1) HK1016025A1 (xx)
TW (1) TW350046B (xx)
WO (1) WO1995016952A1 (xx)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5805907A (en) * 1996-10-04 1998-09-08 International Business Machines Corporation System and method for reducing power consumption in an electronic circuit
US5870616A (en) * 1996-10-04 1999-02-09 International Business Machines Corporation System and method for reducing power consumption in an electronic circuit
US6609190B1 (en) * 2000-01-06 2003-08-19 International Business Machines Corporation Microprocessor with primary and secondary issue queue
US6697939B1 (en) * 2000-01-06 2004-02-24 International Business Machines Corporation Basic block cache microprocessor with instruction history information
US6823448B2 (en) 2000-12-15 2004-11-23 Intel Corporation Exception handling using an exception pipeline in a pipelined processor
US9201657B2 (en) * 2004-05-13 2015-12-01 Intel Corporation Lower power assembler
RU2656782C2 (ru) 2013-05-16 2018-06-06 Конинклейке Филипс Н.В. Способ приведения в действие мельницы
EP2866138B1 (en) * 2013-10-23 2019-08-07 Teknologian tutkimuskeskus VTT Oy Floating-point supportive pipeline for emulated shared memory architectures
CN104951283B (zh) * 2015-06-05 2017-05-31 中国航天科技集团公司第九研究院第七七一研究所 一种risc处理器的浮点处理单元集成电路及方法
CN110825436B (zh) * 2018-08-10 2022-04-29 昆仑芯(北京)科技有限公司 应用于人工智能芯片的计算方法和人工智能芯片

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS586971B2 (ja) * 1979-12-26 1983-02-07 株式会社日立製作所 演算処理装置
JPS5943440A (ja) * 1982-09-03 1984-03-10 Toshiba Corp 演算制御装置
US4879676A (en) * 1988-02-29 1989-11-07 Mips Computer Systems, Inc. Method and apparatus for precise floating point exceptions
US5072364A (en) * 1989-05-24 1991-12-10 Tandem Computers Incorporated Method and apparatus for recovering from an incorrect branch prediction in a processor that executes a family of instructions in parallel
US5487156A (en) * 1989-12-15 1996-01-23 Popescu; Valeri Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched
JP2818249B2 (ja) * 1990-03-30 1998-10-30 株式会社東芝 電子計算機
JP2878792B2 (ja) * 1990-06-22 1999-04-05 株式会社東芝 電子計算機
EP0518420A3 (en) * 1991-06-13 1994-08-10 Ibm Computer system for concurrent processing of multiple out-of-order instructions

Also Published As

Publication number Publication date
EP0690372A1 (en) 1996-01-03
KR0175116B1 (ko) 1999-04-01
EP0690372B1 (en) 2010-03-03
CN1119473A (zh) 1996-03-27
CN1068445C (zh) 2001-07-11
WO1995016952A1 (en) 1995-06-22
KR960701399A (ko) 1996-02-24
EP0690372A4 (en) 2000-05-03
DE69435278D1 (de) 2010-04-22
TW350046B (en) 1999-01-11
JP2815236B2 (ja) 1998-10-27

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Legal Events

Date Code Title Description
PE Patent expired

Effective date: 20141214