GB9816548D0 - Method of manufacture using dual damascene process - Google Patents

Method of manufacture using dual damascene process

Info

Publication number
GB9816548D0
GB9816548D0 GBGB9816548.3A GB9816548A GB9816548D0 GB 9816548 D0 GB9816548 D0 GB 9816548D0 GB 9816548 A GB9816548 A GB 9816548A GB 9816548 D0 GB9816548 D0 GB 9816548D0
Authority
GB
United Kingdom
Prior art keywords
manufacture
dual damascene
damascene process
dual
damascene
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GBGB9816548.3A
Other versions
GB2340302A (en
GB2340302A8 (en
GB2340302B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to GB9816548A priority Critical patent/GB2340302B/en
Priority to NL1009899A priority patent/NL1009899C2/en
Publication of GB9816548D0 publication Critical patent/GB9816548D0/en
Publication of GB2340302A publication Critical patent/GB2340302A/en
Publication of GB2340302A8 publication Critical patent/GB2340302A8/en
Application granted granted Critical
Publication of GB2340302B publication Critical patent/GB2340302B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
GB9816548A 1998-07-29 1998-07-29 Method of manufacture using dual damascene process Expired - Fee Related GB2340302B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB9816548A GB2340302B (en) 1998-07-29 1998-07-29 Method of manufacture using dual damascene process
NL1009899A NL1009899C2 (en) 1998-07-29 1998-08-19 Manufacturing method using dual damascene process.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9816548A GB2340302B (en) 1998-07-29 1998-07-29 Method of manufacture using dual damascene process
NL1009899A NL1009899C2 (en) 1998-07-29 1998-08-19 Manufacturing method using dual damascene process.

Publications (4)

Publication Number Publication Date
GB9816548D0 true GB9816548D0 (en) 1998-09-30
GB2340302A GB2340302A (en) 2000-02-16
GB2340302A8 GB2340302A8 (en) 2000-04-05
GB2340302B GB2340302B (en) 2000-07-26

Family

ID=26314140

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9816548A Expired - Fee Related GB2340302B (en) 1998-07-29 1998-07-29 Method of manufacture using dual damascene process

Country Status (2)

Country Link
GB (1) GB2340302B (en)
NL (1) NL1009899C2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6313025B1 (en) * 1999-08-30 2001-11-06 Agere Systems Guardian Corp. Process for manufacturing an integrated circuit including a dual-damascene structure and an integrated circuit

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5420067A (en) * 1990-09-28 1995-05-30 The United States Of America As Represented By The Secretary Of The Navy Method of fabricatring sub-half-micron trenches and holes
DE69318880T2 (en) * 1992-03-31 1998-10-08 Sgs Thomson Microelectronics Planarization process from an integrated circuit
DE4435586A1 (en) * 1994-10-05 1996-04-11 Itt Ind Gmbh Deutsche Self-adjusting, global levelling of integrated circuit surface
US5635423A (en) * 1994-10-11 1997-06-03 Advanced Micro Devices, Inc. Simplified dual damascene process for multi-level metallization and interconnection structure
US5705439A (en) * 1996-04-22 1998-01-06 Taiwan Semiconductor Manufacturing Company Ltd. Method to make an asymmetrical LDD structure for deep sub-micron MOSFETS
US5834159A (en) * 1996-04-22 1998-11-10 Advanced Micro Devices, Inc. Image reversal technique for forming small structures in integrated circuits
KR0184158B1 (en) * 1996-07-13 1999-04-15 문정환 Magnetic matching metal wiring method of semiconductor device

Also Published As

Publication number Publication date
NL1009899C2 (en) 2000-02-22
GB2340302A (en) 2000-02-16
GB2340302A8 (en) 2000-04-05
GB2340302B (en) 2000-07-26

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20020729