GB2340302A

GB2340302A - Dual damascene process

Info

Publication number: GB2340302A
Application number: GB9816548A
Authority: GB
Inventors: Meng-Jin Tsai
Original assignee: United Microelectronics Corp
Current assignee: United Microelectronics Corp
Priority date: 1998-07-29
Filing date: 1998-07-29
Publication date: 2000-02-16
Anticipated expiration: 2018-07-29
Also published as: GB2340302A8; GB2340302B; NL1009899C2; GB9816548D0

Description

2340302 METHOD OF MANUFACTURE US&G DUAL DAMASCENE PROCESS

BACKGROUND OF THE INVENTION

Field of Invention

The present invention relates to a method of manufacturing semiconductor devices. More particularly, the present invention relates to a method of manufacturing semiconductor devices using a dual damascene process.

Rs 0 Sqpti -n of Relate.d Art As the level of integration of integrated circuit increases, the number of necessary metallic interconnects increases correspondingly. Consequently, designs having two or more metallic layers are now frequently employed in the fabrication of integrated circuits.

Due to the increase in packing density, reliable and high-yield metallic interconnects is becoming more difficult to produce. A damascene process is a method of forming metallic interconnects by first etching trench lines in a dielectric layer, and then depositing metal to fill the trench and thereby forming metallic interconnects. Damascene process is a highly efficient method that can produce highly reliable interconnects with high yield.

In fact, damascene process is one of the best choices for fabricating interconnects in the sub-quarter micron regime.

Figs. IA through IC are cross-sectional views showing the progression of manufacturing steps in producing a metallic interconnect according to a conventional dual 2 damascene process. First, as shown in Fig. I A, a substrate 10 having conductive layer 14 on top is provided. The conductive layer 14 is used for connecting to the desired conductive region of a device (not shown). Furthermore, the conductive layer 14 is isolated from other conductive regions underneath by an inter-metal dielectric layer 12.

Next, an oxide layer 16 is formed over the conductive layer 14 using, for example, a low-pressure chemical vapor deposition method. Thereafter, an isolation layer 18 is formed over the oxide layer 16 again using, for example, a low-pressure chemical vapor deposition method. The isolation layer 18 can be a silicon nitride layer, for example.

Next, using a low-pressure chemical vapor deposition method, another oxide layer 20 is formed over the isolation layer 18. Subsequently, a patterned photoresist layer 21 is formed over the oxide layer 20 exposing a portion of the oxide layer 20, wherein the exposed portion of the oxide layer 20 is located directly above the conductive layer 14.

Next, as shown in Fig. 113, conventional photolithographic and etching techniques are used to etch the exposed oxide layer 20. Consequently, a portion of the oxide layer 20 and the insulation layer 18 are etched away forming an opening 22 that exposes a portion of the oxide layer 16. Thereafter, the photoresist layer 21 is removed using, for example, oxygen plasma. Subsequently, another patterned photoresist layer 24 is formed over the oxide layer 20.

Next, as shown in Fig. IC, conventional photolithographic and etching techniques are again used to etch the oxide layer 16 exposed by the opening 22. In the meantime, a portion of the oxide layer 20 on the sidewalls of the opening 22 is removed to form an opening 28. Similarly, an opening 26 is also formed in the oxide layer 20. Next, the photoresist layer 24 is removed using, for example, oxygen plasma. Thereafter, a 3 sputtering method or a chemical vapor deposition method is used to deposit a conductive material into the openings 22 and 28 to form a conductive layer 30 having electrical connection with the conductive layer 14. At the same time, conductive material is also deposited into the opening 26 to form a conductive layer 30. Finally, subsidiary operations for completing the dual damascene structure are conducted.

In the aforementioned dual damascene process, photolithographic and etching operations have to be carried out twice. Therefore, the fabricating procedure is more complicated and hence more vulnerable to problems created by focusing errors.

In light of the foregoing, there is a need to improve the conventional dual damascene method of fabricating interconnects.

SUMMARY OF THE INVENTION

Accordingly, the present invention is to provide a dual damascene process of manufacturing interconnects that requires only one photolithographic and etching operation.

Consequently, manufacturing operation is simplified and problems due to focusing errors are reduced.

To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of manufacturing interconnects using a dual damascene process. The method includes the steps of forming an oxide layer over a substrate that has a conductive layer thereon. The oxide layer has a protrusion region located directly above the conductive layer. Next, an isolation layer is formed over the oxide layer. Then, a polishing method such as a chemical-mechanical polishing operation is employed to remove a portion of the isolation 4 layer in the protrusion region, thereby forming an opening that lies above the conductive layer. Finally, subsidiary operations are carried out to complete the fabrication.

Another method includes the steps of forming an oxide layer over a substrate that has a conductive layer thereon. The oxide layer has a protrusion region located directly above the conductive layer. Next, an isolation layer is formed over the oxide layer. A coating layer is then formed on the isolation layer. Then, a removing method such as a chemicalmechanical polishing operation is employed to remove a portion of the coating layer and the isolation layer in the protrusion region, thereby forming an opening that lies above the conductive layer. Finally, subsidiary operations are carried out to complete the io fabrication.

Therefore, this invention is capable simplifying manufacturing operation by saving one photoresist application and development operation compared with a conventional method.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,

Figs. I A through I C are cross-sectional views showing the progression of manufacturing steps in producing a metallic interconnect according to a conventional dual damascene process; and Figs. 2A through 2C are cross-sectional views showing the progression of manufacturing steps in producing a metallic interconnect using a dual damascene process according to one preferred embodiment of this invention; and Figs. 3A through 3)C are cross-sectional views showing the progression of manufacturing steps in producing a metallic interconnect using a dual damascene process according to one preferred embodiment of this invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

Figs. 2A through 2C are cross-sectional views showing the progression of manufacturing steps in producing a metallic interconnect using a dual damascene process according to one preferred embodiment of this invention. First, as shown in Fig. 2A, a substrate 50 having conductive layers 53 and 54 thereon is provided. The conductive layer 54 is used as a means to couple with other desired device structure (not shown). Underneath the conductive layers 53 and 54, there is an inter-metal dielectric layer 52 for preventing any unwanted electrical contact between other device structures and the 6 conductive layers. In Fig. 2A, the width of the conductive layer 54 is wider than the width of the conductive layer 53.

Next, as shown in Fig. 2B, an oxide layer 56 is formed over the conductive layers 53, 54 and the substrate 50 using, for example, a high- density plasma chemical vapor deposition (HDPCVD) method or a plasma-enhanced vapor deposition method. During the process of depositing oxide material over the substrate and conductive layers using HDPCVD, characteristic sloping edges will form on it surface. Consequently, protrusions 57 and 61 are produced. The protrusion 61 is located above the conductive layer 54, while the protrusion 57 is located above the conductive layer 53. Since the conductive layer 54 has a width wider than the conductive layer 53, the resulting protrusion 61 on the oxide layer 56 is higher and bigger than the protrusion 57.

Thereafter, an insulation layer 58 is formed over the oxide layer 56 using, for example, a low-pressure chemical vapor deposition method. For example, the insulation layer 58 can be a silicon nitride or silicon oxynitride layer whose cross-sectional profile reciprocates the profile of the oxide layer 56 below.

A portion of the insulation layer 58 in protrusion region 61 is removed to form an opening 59 that exposes the oxide layer 56 using, for example, a chemical-mechanical polishing (CMP) method. Because height of the protrusion 57 is small, the polishing operation will not completely remove the insulation layer 58 in the protrusion region 57.

Consequently, both the exposed oxide layer 56 and the residual insulation layer 58 are roughly at the same height level. In the subsequent step, an oxide layer 60 is formed covering the insulation layer 58 and the exposed oxide layer 56 using, for example, a lowpressure chemical vapor deposition method.

7 One major aspect of this invention is the use of a chemical-mechanical polishing operation to remove the insulation layer 58 in protrusion region 61 to form the opening 59. Therefore, one less photolithographic and etching operation is needed. Furthermore, even when there are a plurality of high and low protrusions between the conductive layer 53 and conductive layer 54, only insulation layer 58 in the higher protrusion regions will be removed forming openings. No openings are formed in the low protrusion regions. Hence, when another conductive layer are deposited in a subsequent operation, unnecessary contact of this conductive layer with the conductive layer below is avoided.

Next, a patterned photoresist layer 62 is formed over the oxide layer 60. The photoresist layer 62 exposes the oxide layer 60 above the opening 59. Moreover, the exposed area is larger than the size of the opening 59.

Next, as shown in Fig. 2C, thereafter, conventional photolithographic and etching techniques are used to etch the oxide layer 60 so that another opening 64 is formed. Tben, etching is continued down the oxide layer 56 through the opening 59 until the conductive layer 54 is exposed.

A conductive material is deposited to form a conductive layer 68 that fills the openings 59 and 64, and hence the conductive layer 54 is electrically connected. For example, the conductive layer 68 can be formed by depositing tungsten or other conductive material using a sputtering method or a chemical vapor deposition method.

Finally, subsidiary operations for completing the fabrication of a dual damascene structure are performed. Since these subsidiary operations are not directly related to this invention, detail descriptions are excluded here.

8 In summary, the dual damascene process of this invention utilizes a high- density plasma chemical vapor deposition and a plasma-enhanced chemical vapor deposition method to form the oxide layer 56 and the insulation layer 58 so that protrusions 57 and 61 are formed. Subsequently, a chemical-mechanical polishing operation is used to remove the insulation layer 58 in bigger protrusions 61 forming opening 59. Hence, one less photolithographic and etching operation than the conventional method is required.

Another method of method of manufacture using dual damanscene process describes as below.

The same process shown in FIG. 2A is performed so that the structures as shown in io FIG. 2A are formed.

Referring to 3A, a coating layer 70 is formed over the insulation layer 58 to obtain a flat surface. The coating layer 70 may be a photoresist layer, a spin on glass (SOG) layer, or any other materials that have the same property like they.

A portion of the insulation layer 58 in protrusion region 61 is removed to form an opening 159 that exposes the oxide layer 56 using, for example, a chemical-mechanical polishing (CMP) method or a etching back method. This etching method has the same etching rate toward the insulation layer 58 and the coating layer 70. Because height of the protrusion 57 is small, the polishing operation will not completely remove the insulation layer 58 in the protrusion region 57. Consequently, both the exposed oxide layer 56, the residual insulation layer 58 and the coating layer 70 are roughly at the same height level.

Referring to FIG. 3B, an oxide layer 160 is formed covering the insulation layer 58, the coating layer 70 and the exposed oxide layer 56 using, for example, a low-pressure chemical vapor deposition method. Next, a patterned photoresist layer 162 is formed over 9 the oxide layer 160. The photoresist layer 162 exposes the oxide layer 160 above the opening 159. Moreover, the exposed area is larger than the size of the opening 159.

Next, as shown in Fig. 3C, thereafter, conventional photolithographic and etching techniques are used to etch the oxide layer 160 so that another opening 164 is formed.

Then, etching is continued down the oxide layer 56 through the opening 159 until the conductive layer 54 is exposed.

A conductive material is deposited to form a conductive layer 168 that fills the openings 159 and 164, and hence the conductive layer 54 is electrically connected. For example, the conductive layer 168 can be formed by depositing tungsten or other conductive material using a sputtering method or a chemical vapor deposition method.

In summary, the dual damascene process of this invention utilizes a highdensity plasma chemical vapor deposition and a plasma-enhanced chemical vapor deposition method to form the oxide layer 56 and the insulation layer 58 so that protrusions 57 and 61 are formed. The coating layer 70 is next formed on the insulator layer 58. Subsequently, a chemical-mechanical polishing operation is used to remove the insulation layer 58 in bigger protrusions 61 forming opening 159. Hence, one less photolithographic and etching operation than the conventional method is required.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover I modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents. -

Claims

WHAT IS CLAIMED IS:

1. A dual damascene process for forming interconnects, comprising the steps of providing a substrate having a plurality of first conductive layers thereon; forming a first oxide layer over those first conductive layers and the substrate, wherein the first oxide layer has high or low protrusion regions located whenever there is a first conductive layer below; forming an isolation layer over the first oxide layer so that the cross- sectional profile of the isolation layer matches the undulating profile of the first oxide layer below; removing the isolation layer in the higher protrusion region to form a first opening that exposes a portion of the first oxide layer, wherein the first opening is located above one of the first conductive layers; forming a second oxide layer over the isolation layer with the first opening; patterning the second oxide layer and the first oxide layer to form a second opening that exposes the first opening and one of the first conductive layer; and forming a second conductive layer that fills the first opening and the second opening to establish an electrical connection with the exposed first conductive layer.

2. The method of claim 1, wherein the step of forming the first oxide layer includes a high-density plasma chemical vapor deposition method.

3. The method of claim 1, wherein the step of forming the isolation layer includes depositing silicon nitride.

4. The method of claim 1, wherein the step of removing the isolation layer in the high protrusion regions includes a chemical-mechanical polishing method.

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5. The method of claim 1, wherein the step of patterning the second oxide layer and the first oxide layer includes a photolithographic and etching operation,

6. The method of claim 1, wherein the step of removing the isolation layer in the high protrusion regions includes keeping the isolation layer in the low protrusion regions.

7. A dual damascene process for forming interconnects, comprising the steps of providing a substrate having a plurality of first conductive layers thereon; forming a first oxide layer having high and low protrusion regions and then forming an isolation layer over those first conductive layers and the substrate, wherein the high or low protrusion regions of the first oxide layer are located whenever there is a first conductive layer below; forming a coating layer over the first oxide layer and the isolation layer; removing the coating layer and the isolation layer in the higher protrusion region to form a first opening that exposes a portion of the first oxide layer, wherein the first opening is located above one of the first conductive layers; forming a second oxide layer over the isolation layer with the first opening; patterning the second oxide layer and the first oxide layer to form a second opening that exposes the first opening and one of the first conductive layer; and forming a second conductive layer that fills the first opening and the second opening to establish an electrical connection with the exposed first conductive layer.

8. The method of claim 7, wherein the step of forming the first oxide layer includes a high-density plasma chemical vapor deposition method.

9. The method of claim 7, wherein the step of forming the first oxide layer includes a plasma-enhanced chemical vapor deposition method.

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10. The method of claim 7, wherein the step of forming the isolation layer includes depositing silicon nitride.

11. ne method of claim 7, wherein the step of removing the coating layer and the isolation layer in the high protrusion regions includes a chemical-mechanical polishing method or an etching method.

12. The method of claim 7, wherein the step of patterning the second oxide layer and the first oxide layer includes a photolithographic and etching operation.

13. The method of any preceding claim, wherein the step of forming the second conductive layer includes a chemical vapor deposition method.

13. The method of claim 7, wherein the step of removing the coating layer and the isolation layer in the high protrusion regions includes keeping the coating layer and the io isolation layer in the low protrusion regions.

14. The method of claim 7, wherein the step of forming the second conductive layer includes depositing tungsten, copper or aluminum.

15. The method of claim 7, wherein the step of forming the second conductive layer includes a chemical vapor deposition method.

16. The method of claim 7, wherein the coating layer includes a photoresist layer.

17. The method of claim 7, wherein the coating layer includes a spin on glass layer.

Amendments to the claims have been filed as follows 1 A dual damascene process for forming interconnects, comprising the steps of:

providing a substrate having a plurality of first conductive lines thereon; forming a first oxide layer over those first conductive lines and the substrate, wherein the first oxide layer has higher and lower protrusion regions, one region located above each first conductive line; forming an isolation layer over the first oxide layer so that the cross-sectional profile of the isolation layer matches the undulating profile of the first oxide layer below; removing the isolation layer over a higher protrusion region to form a first opening that exposes a portion of the first oxide layer, located above one of the first conductive lines; forming a second oxide layer over the isolation layer including the exposed portion; patterning the second oxide layer to form a second opening that exposes the first opening, and the first oxide layer to expose the said first conductive line; and forming a second conductive line that fills the first opening and the patterned part of the first oxide layer to establish an electrical connection with the exposed first conductive line.

2. A dual damascene process for forming interconnects, comprising the 1.

steps of:

providing a substrate having a plurality of first conductive lines thereon; forming a first oxide layer having higher and lower protrusion regions and then forming an isolation layer over those first conductive lines and the substrate, the higher or lower protrusion regions of the first oxide layer being located above respective first conductive lines; forming a coating layer over the first oxide layer and the isolation layer; removing the coating layer and the isolation layer in the higher protrusion region to form a first opening that exposes a portion of the first oxide layer, wherein the first opening is located above one of the first conductive lines; forming a second oxide layer over the isolation layer with the first opening; patterning the second oxide layer to form a second opening that exposes the first opening, and the first oxide layer to expose the said first conductive line; and forming a second conductive line that fills the first opening and the patterned is part of the first oxide layer to establish an electrical connection with the exposed first conductive line.

3. The method of claim I or 2, wherein the step of forming the first oxide layer includes a high-density plasma or plasma-enhanced chemical vapor deposition method.

4. The method of claim 1, 2, or 3, wherein the step of forming the isolation layer includes depositing silicon nitride.

5., The method of any preceding claim, wherein the step of removing the isolation layer in the higher protrusion regions includes a chemicalmechanical polishing method.

6. The method of any preceding claim, wherein the step of patterning the second oxide layer and the first oxide layer includes a single photolithographic and etching operation.

7. The method of any preceding claim, wherein the step of removing the isolation layer in the high protrusion regions includes keeping the isolation layer in the lower protrusion regions.

8. The method of claims 2 and 7, wherein the step of removing the coating layer and the isolation layer in the higher protrusion regions includes keeping both the coating layer and the lower protrusion regions.

9. The method of claim 2, wherein the step of removing the coating layer and the isolation layer in the high protrusion regions includes an etching method.

10. The method of claim 2, wherein the coating layer includes a photoresist layer.

11. The method of claim 2, wherein the coating layer includes a spin-on glass layer.

12. The method of any preceding claim, wherein the step of forming the second conductive layer includes depositing tungsten, copper or aluminum.