DE4435586A1 - Self-adjusting, global levelling of integrated circuit surface - Google Patents

Self-adjusting, global levelling of integrated circuit surface

Info

Publication number
DE4435586A1
DE4435586A1 DE19944435586 DE4435586A DE4435586A1 DE 4435586 A1 DE4435586 A1 DE 4435586A1 DE 19944435586 DE19944435586 DE 19944435586 DE 4435586 A DE4435586 A DE 4435586A DE 4435586 A1 DE4435586 A1 DE 4435586A1
Authority
DE
Germany
Prior art keywords
layer
insulating layer
self
levelling
adjusting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE19944435586
Other languages
German (de)
Inventor
Hans-Guenter Dipl Phys Zimmer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
Original Assignee
Deutsche ITT Industries GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche ITT Industries GmbH filed Critical Deutsche ITT Industries GmbH
Priority to DE19944435586 priority Critical patent/DE4435586A1/en
Publication of DE4435586A1 publication Critical patent/DE4435586A1/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H01L21/31056—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching the removal being a selective chemical etching step, e.g. selective dry etching through a mask

Abstract

The surface carries at least a conductive layer (2) covered by an insulating film (3). First a levelling, ancillary layer (4) is applied and is then removed down to a first insulating film. The latter is then etched selectively down to the ancillary layer. The ancillary layer is then removed, and a second insulating film (8) is applied. Pref. the first insulating layer is of silicon dioxide, and the ancillary layer is of a photolacquer.

Description

Die Erfindung betrifft ein Verfahren zum Planarisieren der Oberfläche integrierter Halbleiterschaltungen, sie betrifft insbesondere ein Verfahren zum selbstausrichtenden, globalen Planarisieren von Schaltungsstrukturen, bei denen die Leiterschichten mit einer Isolierschicht abgedeckt sind.The invention relates to a method for planarizing the Surface of integrated semiconductor circuits, it concerns in particular a method for self-aligning, global planarization of circuit structures in which the conductor layers are covered with an insulating layer are.

Bei der Herstellung von integrierten Schaltungsstrukturen kommt es verfahrensbedingt zur Ausbildung unebener Oberflächen. Wird nun eine Isolierschicht aufgebracht, um darauf weitere Strukturen herzustellen, so bildet sich eine Topographie aus in Form einer nichtplanaren oder abgestuften Oberfläche. Dies erschwert in erheblichen Maße die Anwendung herkömmlicher Photolithographietechnik.In the manufacture of integrated circuit structures due to the process, uneven training occurs Surfaces. Now an insulating layer is applied to to create further structures on it, one is formed Topography in the form of a nonplanar or graded surface. This makes it considerably more difficult the application of conventional photolithography technology.

Es ist deshalb üblich geworden, Planarisierschichten aus z. B. Photolack oder Glas (spin on glass) aufzubringen und dann die Hilfsschicht und die darunterliegende Isolierschicht gleichermaßen abzuätzen.It has therefore become common to use planarizing layers made of e.g. B. Apply photoresist or glass (spin on glass) and then the auxiliary layer and the one underneath Etching off the insulating layer equally.

Aus EP-OS 0 368 504 ist ein Verfahren bekannt, bei dem die planarisierende Schicht aus Glas anisotrop mit dem erhabenen Teilen der darunterliegenden Siliciumdioxidschicht geätzt wird. Man erhält damit eine planare Oberfläche, die allerdings den Nachteil hat, daß bei unterschiedlich hohen Leitbahnen unterschiedliche tiefe Kontaktlöcher erforderlich sind.From EP-OS 0 368 504 a method is known in which the planarizing layer of glass anisotropic with the raised parts of the underlying Silicon dioxide layer is etched. You get one planar surface, which however has the disadvantage that different depths with different levels Contact holes are required.

Die in den Ansprüchen gekennzeichnete Erfindung löst deshalb die Aufgabe, ein Verfahren zur Herstellung einer selbstausrichtenden, globalen Planarisierung anzugeben, das gleichmäßig tiefe Kontaktlöcher ermöglicht.The invention characterized in the claims solves hence the task of a method of making a self-aligning global planarization to indicate that allows uniformly deep contact holes.

Die Erfindung wird nachstehend anhand der Figuren der Zeichnung, die aufeinanderfolgende Verfahrensschritte verkörpern, näher erläutert.The invention is described below with reference to the figures of the  Drawing, the successive process steps embody, explained in more detail.

Fig. 1 zeigt unter Bezugsziffer 1 einen mit den entsprechenden aktiven Bereichen versehenen Halbleiterkörper. Auf dessen Oberfläche befinden sich eine oder mehrere Leitbahnen 2 aus z. B. Aluminium. Die gesamte Oberfläche des Halbleiterkörpers, einschließlich der Leitbahnen, ist mit einer Isolierschicht 3 aus z. B. Siliciumdioxid abgedeckt. Erhebungen auf der Oberfläche des Halbleiterkörpers die z. B. durch die Leitbahnen bedingt sind, findet man dann entsprechend auch an der Oberfläche der Isolierschicht 3. Fig. 1 shows a provided with the respective active regions of the semiconductor body with reference numeral 1. On its surface there are one or more interconnects 2 made of z. B. aluminum. The entire surface of the semiconductor body, including the interconnects, is covered with an insulating layer 3 of z. B. covered silicon dioxide. Elevations on the surface of the semiconductor body, the z. B. are caused by the interconnects, can then be found accordingly on the surface of the insulating layer 3 .

Im nächsten Schritt wird nunmehr eine Hilfsschicht 4 aus z. B. Photolack aufgebracht, die dann selektiv z. B. mit 03 abgeätzt wird, wobei die Erhebungen in der Isolierschicht 3 erhalten bleiben, siehe Fig. 2.In the next step, an auxiliary layer 4 of z. B. photoresist, which is then selectively z. B. is etched away with 03, the elevations in the insulating layer 3 being retained, see FIG. 2.

Auf die selektive Ätzung der Hilfsschicht 4 folgt nun die selektive Ätzung des Isolierschicht 3, mit z. B. Fluor-Plasma, wobei durch hinreichend große isotrope Komponente beim Ätzvorgang ein Unterätzen der Hilfsschicht 4 eintritt. Es resultiert die in Fig. 3 gezeigte Struktur.The selective etching of the auxiliary layer 4 is now followed by the selective etching of the insulating layer 3 , with z. B. fluorine plasma, undercutting of the auxiliary layer 4 occurs due to a sufficiently large isotropic component during the etching process. The structure shown in FIG. 3 results.

Nach dem Ablösen der Hilfsschicht 4 ergibt sich die in Fig. 4 gezeigte Struktur.After the auxiliary layer 4 has been detached, the structure shown in FIG. 4 results.

Fig. 4 zeigt exemplarisch nur eine Leitbahn, doch ist es leicht einzusehen, daß bei mehreren unterschiedlich hohen Leitbahnen der Abstand zwischen deren Oberflächen zur Oberfläche der Isolierschicht stets gleich groß ist. Auf das Dielektrikum kann eine weitere Schicht 5 aufgebracht und neue Strukturen erzeugt werden, siehe Fig. 5. Das erfindungsgemäße Verfahren ermöglicht somit, Kontaktlöcher auszubilden, die stets gleich tief sind, unabhängig von der Höhe der zu kontaktierenden Leitbahnen. Fig. 4 shows an example of only one interconnect, but it is easy to see that in the case of several interconnects of different heights, the distance between their surfaces and the surface of the insulating layer is always the same. A further layer 5 can be applied to the dielectric and new structures can be created, see FIG. 5. The method according to the invention thus makes it possible to form contact holes which are always of the same depth, regardless of the height of the interconnects to be contacted.

Claims (2)

1. Verfahren zur selbstjustierenden globalen Planarisierung von Oberflächen integrierter Halbleiterschaltungen, auf denen mindestens eine Leiterschicht (2) aufgebracht und mit einer Isolierschicht (3) abgedeckt ist, gekennzeichnet durch die folgende Schritte:
  • - Aufbringen einer planarisierenden Hilfsschicht (4),
  • - Abtragen der Hilfsschicht (4) mindestens bis zur ersten Isolierschicht (3),
  • - Ätzen der ersten Isolierschicht (3) selektiv zur Hilfsschicht (4), und
  • - Entfernen der Hilfschicht (4) und Aufbringen einer zweiten Isolierschicht (5).
1. Method for self-adjusting global planarization of surfaces of integrated semiconductor circuits on which at least one conductor layer ( 2 ) is applied and covered with an insulating layer ( 3 ), characterized by the following steps:
  • - applying a planarizing auxiliary layer ( 4 ),
  • - removing the auxiliary layer ( 4 ) at least up to the first insulating layer ( 3 ),
  • - Etching the first insulating layer ( 3 ) selectively to the auxiliary layer ( 4 ), and
  • - Removing the auxiliary layer ( 4 ) and applying a second insulating layer ( 5 ).
2. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß die Isolierschicht (3) aus Siliciumdioxid und die Hilfsschicht (4) aus Photolack besteht.2. The method according to claim 1, characterized in that the insulating layer ( 3 ) consists of silicon dioxide and the auxiliary layer ( 4 ) consists of photoresist.
DE19944435586 1994-10-05 1994-10-05 Self-adjusting, global levelling of integrated circuit surface Ceased DE4435586A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE19944435586 DE4435586A1 (en) 1994-10-05 1994-10-05 Self-adjusting, global levelling of integrated circuit surface

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19944435586 DE4435586A1 (en) 1994-10-05 1994-10-05 Self-adjusting, global levelling of integrated circuit surface

Publications (1)

Publication Number Publication Date
DE4435586A1 true DE4435586A1 (en) 1996-04-11

Family

ID=6530015

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19944435586 Ceased DE4435586A1 (en) 1994-10-05 1994-10-05 Self-adjusting, global levelling of integrated circuit surface

Country Status (1)

Country Link
DE (1) DE4435586A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2778494A1 (en) * 1998-05-05 1999-11-12 United Microelectronics Corp Forming double damascene structure for highly integrated circuits
NL1009899C2 (en) * 1998-07-29 2000-02-22 United Microelectronics Corp Manufacturing method using dual damascene process.

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
FLAMM, D.L.: Dry Plasma Resist Stripping Part I: Overview of Equipment. In: Solid-State Technology,Aug. 1992, pp. 37-39 *
JP 4-312923 A2. In: Patent Abstracts of Japan, E-1337, 24.3.1993, Vol. 17, No. 145 *
JP 4-78141 A2. In: Patent Abstracts of Japan, E-1225, 29.6.92, Vol. 16, No. 294 *
JP 60-59737 A2. In: Patent Abstracts of Japan, E-334, 9.8.85, Vol. 9, No. 193 *
JP 60-59738 A2. In: Patent Abstracts of Japan, E-334, 9.8.1985, Vol. 9, No. 193 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2778494A1 (en) * 1998-05-05 1999-11-12 United Microelectronics Corp Forming double damascene structure for highly integrated circuits
NL1009899C2 (en) * 1998-07-29 2000-02-22 United Microelectronics Corp Manufacturing method using dual damascene process.

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OP8 Request for examination as to paragraph 44 patent law
8127 New person/name/address of the applicant

Owner name: MICRONAS INTERMETALL GMBH, 79108 FREIBURG, DE

8131 Rejection