GB9525824D0 - Power reduction in a data processing system using pipeline registers and method therefor - Google Patents

Power reduction in a data processing system using pipeline registers and method therefor

Info

Publication number
GB9525824D0
GB9525824D0 GBGB9525824.0A GB9525824A GB9525824D0 GB 9525824 D0 GB9525824 D0 GB 9525824D0 GB 9525824 A GB9525824 A GB 9525824A GB 9525824 D0 GB9525824 D0 GB 9525824D0
Authority
GB
United Kingdom
Prior art keywords
data processing
processing system
method therefor
power reduction
pipeline registers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GBGB9525824.0A
Other versions
GB2296118A (en
GB2296118B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of GB9525824D0 publication Critical patent/GB9525824D0/en
Publication of GB2296118A publication Critical patent/GB2296118A/en
Application granted granted Critical
Publication of GB2296118B publication Critical patent/GB2296118B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G06F9/30014—Arithmetic instructions with variable precision
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Advance Control (AREA)
  • Microcomputers (AREA)
  • Complex Calculations (AREA)

Abstract

In a data arithmetic logic unit (54), power consumption is reduced by eliminating unnecessary write backs to the destination register (82) following a MAC (multiply/accumulate) operation. A series of instructions provided to the data ALU (arithmetic/logic) (54) are monitored by a control circuit (89). When two or more consecutive instructions having identical destinations for a result are detected, the result is written to a pipeline register (78) instead of to the destination register (82) named in the consecutive instructions. Thus, only a short, lightly loaded bus to the pipeline register (78) is driven, instead of the longer heavily loaded bus to the destination register (82).
GB9525824A 1994-12-22 1995-12-18 Power reduction in a data processing system using pipeline registers and method therefor Expired - Fee Related GB2296118B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/361,405 US5666300A (en) 1994-12-22 1994-12-22 Power reduction in a data processing system using pipeline registers and method therefor

Publications (3)

Publication Number Publication Date
GB9525824D0 true GB9525824D0 (en) 1996-02-21
GB2296118A GB2296118A (en) 1996-06-19
GB2296118B GB2296118B (en) 1999-10-06

Family

ID=23421909

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9525824A Expired - Fee Related GB2296118B (en) 1994-12-22 1995-12-18 Power reduction in a data processing system using pipeline registers and method therefor

Country Status (4)

Country Link
US (1) US5666300A (en)
KR (1) KR100446564B1 (en)
CN (1) CN1132879A (en)
GB (1) GB2296118B (en)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5870581A (en) * 1996-12-20 1999-02-09 Oak Technology, Inc. Method and apparatus for performing concurrent write operations to a single-write-input register file and an accumulator register
JP2000039995A (en) * 1998-06-25 2000-02-08 Texas Instr Inc <Ti> Flexible accumulate register file to be used in high performance microprocessor
KR100325430B1 (en) * 1999-10-11 2002-02-25 윤종용 Data processing apparatus and method for performing different word-length arithmetic operations
US7890566B1 (en) * 2000-02-18 2011-02-15 Texas Instruments Incorporated Microprocessor with rounding dot product instruction
US20030144826A1 (en) * 2002-01-29 2003-07-31 Mandell Michael I. Register repositioning method for functional verification systems
US20040015676A1 (en) * 2002-07-17 2004-01-22 Pierre-Yvan Liardet Sharing of a logic operator having a work register
US7131017B2 (en) * 2002-08-16 2006-10-31 Carnegie Mellon University Programmable pipeline fabric having mechanism to terminate signal propagation
US7730292B2 (en) * 2003-03-31 2010-06-01 Hewlett-Packard Development Company, L.P. Parallel subword instructions for directing results to selected subword locations of data processor result register
AT413895B (en) * 2003-09-08 2006-07-15 On Demand Informationstechnolo DIGITAL SIGNAL PROCESSING DEVICE
US8015229B2 (en) * 2005-06-01 2011-09-06 Atmel Corporation Apparatus and method for performing efficient multiply-accumulate operations in microprocessors
US8307196B2 (en) * 2006-04-05 2012-11-06 Freescale Semiconductor, Inc. Data processing system having bit exact instructions and methods therefor
JP4893154B2 (en) * 2006-08-21 2012-03-07 富士通セミコンダクター株式会社 Image processing apparatus and image processing method
US8370606B2 (en) * 2007-03-16 2013-02-05 Atmel Corporation Switching data pointers based on context
US7797516B2 (en) * 2007-03-16 2010-09-14 Atmel Corporation Microcontroller with low-cost digital signal processing extensions
US20110055303A1 (en) * 2009-09-03 2011-03-03 Azuray Technologies, Inc. Function Generator
US20110153995A1 (en) * 2009-12-18 2011-06-23 Electronics And Telecommunications Research Institute Arithmetic apparatus including multiplication and accumulation, and dsp structure and filtering method using the same
US9886277B2 (en) 2013-03-15 2018-02-06 Intel Corporation Methods and apparatus for fusing instructions to provide OR-test and AND-test functionality on multiple test sources
US9483266B2 (en) 2013-03-15 2016-11-01 Intel Corporation Fusible instructions and logic to provide OR-test and AND-test functionality using multiple test sources
CN109656867B (en) * 2016-11-03 2023-05-16 中科寒武纪科技股份有限公司 SLAM arithmetic device and method
US11144367B2 (en) 2019-02-08 2021-10-12 International Business Machines Corporation Write power optimization for hardware employing pipe-based duplicate register files
US10901492B1 (en) * 2019-03-29 2021-01-26 Amazon Technologies, Inc. Power reduction in processor pipeline by detecting zeros
US11579843B2 (en) * 2020-06-15 2023-02-14 Micron Technology, Inc. Bit string accumulation in multiple registers
CN113504893B (en) * 2021-07-23 2022-08-26 河南亿秒电子科技有限公司 Intelligent chip architecture and method for efficiently processing data
CN114237550B (en) * 2021-11-10 2023-10-13 电子科技大学 Wallace tree-based multi-input shift sum accumulator

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8401807D0 (en) * 1984-01-24 1984-02-29 Int Computers Ltd Pipelined data processing apparatus
US4575812A (en) * 1984-05-31 1986-03-11 Motorola, Inc. X×Y Bit array multiplier/accumulator circuit
GB2204431A (en) * 1987-04-25 1988-11-09 Ferranti Plc Digital signal processing and transducer array beamforming
US4843585A (en) * 1987-09-14 1989-06-27 Motorola, Inc. Pipelineable structure for efficient multiplication and accumulation operations
US5204828A (en) * 1989-02-10 1993-04-20 Intel Corporation Bus apparatus having hold registers for parallel processing in a microprocessor
JPH04119430A (en) * 1990-09-11 1992-04-20 Mitsubishi Electric Corp Pipeline control system
EP0547230B1 (en) * 1991-07-01 1999-10-13 Fujitsu Limited Apparatus for sum-of-product operation
JPH05174050A (en) * 1991-12-26 1993-07-13 Matsushita Electric Ind Co Ltd Series arithmetic unit
JPH05257683A (en) * 1992-03-16 1993-10-08 Sharp Corp Pipeline structure of large scale integrated circuit
JPH06282418A (en) * 1993-03-30 1994-10-07 N T T Idou Tsuushinmou Kk Arithmetic unit

Also Published As

Publication number Publication date
US5666300A (en) 1997-09-09
KR960024896A (en) 1996-07-20
GB2296118A (en) 1996-06-19
GB2296118B (en) 1999-10-06
CN1132879A (en) 1996-10-09
KR100446564B1 (en) 2004-11-03

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20001218