GB2204431A - Digital signal processing and transducer array beamforming - Google Patents

Abstract

A method of forming a directed reception beam sample for an array of transducer elements by time-interpolation of transducer samples taken at predetermined intervals comprises deriving and storing in advance for a particular beam direction, and for each of a set of succeeding sampling intervals, coefficients representing proportions of individual transducer samples taken in the interval utilised to form interpolated values and then multiplying each of the appropriate transducer samples as they are taken by appropriate stored coefficients and accumulating the products. A pipelined digital signal processor 10 (Fig. 2) performs the operation 15, 16 using transducer samples input via 11 and stored coefficients input via 12. To process transducer samples which arrive interleaved with those of different beam samples a feedback path of the accumulator 17 includes a dual port memory 24 to receive at 23 a partially accumulated beam sample formed by receipt of one transducer sample whilst providing a different partially accumulated beam sample to the feedback path for the next transducer sample. A multiplexer 20 permits direct feedback from accumulator output register 10 omitting the memory 24 when successive transducer samples contribute to the same partially accumulated beam sample. <IMAGE>

Description

DIGITAL SIGNAL PROCESSING CIRCUIT AND TRANSDUCER ARRAY BEAMFORMING METHOD SUITABLE FOR SUCH CIRCUIT This invention relates to a digital processing circuit for serially performing similar arithmetic or equivalent logical operations on applied data words in accordance with the data words representing components of different functions thereof interleaved in time.

Such a processing circuit is of particular interest when said functions are summation or accumulations of the components, the results of the arithmetic or logical operations on the data words, and of even further interest when a succession of data words contributing to one function are separated in time of application to the processor from further data words contributing to that function by a succession of data words forming components of a different, but correspondingly defined, function.

Such a digital processing circuit is particularly useful in so-called front end processing of signals received from transducer arrays in sonar, radar and equivalent apparatus in effecting combinations of transducer signals received in both time and space to form directional receptive beams of the arrays.

To this end the invention also relates to the provision of a method of processing sampled data of one or more arrays of transducers in order to define simply and at high speed directed beam samples for a plurality of directions, the method being particularly advantageous when the arrays contain large numbers of transducers and/or a large number of directed beams have to be defined and/or a high directed-beam sampling rate is required. It is common for the transducer signals to be sampled and processed digitally and it is convenient to consider operation of the digital signal processing circuit of the invention in relation to the method of processing digital words representing samples of signals received by transducers of a sonar array.

The invention will be described with reference to the accompanying drawings, in which: Figure l(a) is a graphical illustration of one manner in which data words contributing to exemplary output functions are provided interleaved in time, Figure l(b) is a graphical illustration of the manner of processing the data words to obtain the output functions, Figure 2 is a schematic block diagram of one form of digital signal processing circuit according to the present invention, Figure 3 is in block diagram form the circuit of Figure 2 including some modifications and illustrating the generality of arithmetic or logical operations that can be effected thereby, Figure 4(a) is a graphical illustration of the definition of a reception beam direction for a short linear array of transducer in respect of an energy wavefront crossing the array from said direction and comparison between the sampling of transducers as the wavefront is incident thereon with interpolating from samples taken at fixed intervals, Figure 4(b) is a time-space matrix illustrative of sampling and sample processing steps involved in interpolation between multiple bit digital words representing individual signal samples taken from spaced transducers of an array at predefined uniform delayed array sampling intervals to provide equivalent samples for intermediate array sampling intervals consistent with defining a reception beam direction relative to the array, Figure 5 is a graphical illustration of a time-space matrix for implementating the beam forming method of the present invention using the interpolation characteristics defined in advance from a time-space matrix as shown in Figure 4(b), Figure 6 is a time-space matrix formed for successive array sampling intervals where each array sample is a multiple-bit digital word comprising one bit samples from each of the array transducers, illust#rating a particular transducer time-delay sample summation pattern defining a directed beam sample and isolation of appropriate contributory transducer sample bits of a particular beam sample from the remaining bits of the array word by masking unwanted parts of those words, and Figure 7 is a schematic block diagram of digital signal processing circuit of the present invention configured to form directed beam samples from digital data words in accordance with the scheme of Figure 6.

Referring to Figure l(a) this shows a succession of data words kl, k2, k3 etc. which represents information related to three different functions a, b and c but interleaved in the manner in which the data words contributing to the functions are generated or received for processing.

As illustrated successive words are grouped and the groups associated with one of the three different functions, that is, the data words a00 ... a03, a10 ... a14, a20 ... a21, a30 .. etc. relate to function Fn(a), data words b00 ... b03, b10... b13, b20 ... b23, b30 etc. relate to the function Fn (b) and data words c00 ... c02, c10 ... etc. relate to the function Fn(c). It will be appreciated that the function groups may have the same or different numbers of words and that different groups of the same function, such as Fn(a) may have different numbers of data words.

An illustrative function common to each is defined by the sum of all the data words associated with the function having undergone a multiplication operation, that is, a predetermined number of the commonly known multiply-andaccumulate operations where for each data word the multiplication factor may be unique, say m(data word) Thus Fn(a) = (a00x ma00 +a01xma01 +a02xma02 + a03x ma03) + (a10x ma10 + a11x ma11 + a12x ma12 +a12 x ma13 + a14 x ma14) +(a20X ma20 + a21X ma21) + (a30x ma14) 30 .. etc.... (1) Similarly Fn(b) = (b00x mb00 + b01x mb01 + b02x mb02 + b03x mb03) and Fn(c) = (c00x mc00 + c01x mc01 + c02xm02) + (c10 mc10 + C11X mc11 + c12X mc12) + (c20x m20 ... etc. ... (3).

Referring now to Figure 2 a digital signal processor 10 in accordance with the present invention comprises an input register 11 for the successive data words kl, k2, etc. of Figure 1 and a multiplicand register 12 connected to receive in synchronism with the arrival of data words at 11 a stream of data words representing said multiplicands m(data word) from a control store 13 accessed by simply incrementing read addresses by a control counter 14, itself controlled by system clock 14'.

A first arithmetic logic unit, a multiplier 15, is arranged to receive the current data word from register 11 and multiply it by the multiplicand word currently in register 12 and apply the result to one input 16 of a second arithmetic logic unit, an adder 17.

The adder 17 is connected as an accumulator with the output thereof fed to an accumulator register 18, the output of the register 18 being fed by way of a signal node 19 and a 2:1 addressable multiplexer 20 back to a second input 21 of the adder.

The signal node 19 is connected also to an output buffer 22 which may be addressed to accept the current accumulator output from register 18 for output to further processing circuitry.

The output of the accumulator register is furthermore connected to a WRITE port 23 of a dual port RAM 24, a READ port 25 being connected to the addressable multiplexer 20.

The multiplexer 20 state, buffer 22 acceptance state and RAM 24 READ/WRITE addresses may be predetermined and stored with the successively addressed multiplicands in the control store 13 and all control address states updated for each data word input.

The processing circuit is arranged for pipe lined operation whereby in one increment or beat of the control counter the data in input registers 11 and 12 is input to multiplier 15 and the product applied to adder 17 and in the same beat, the accumulator sums the product of the previous beat (at 16) with the previous accumulator sum made available at 21.

As part of the accumulator operation, that is within the same beat, the contents of the accumulator register 18 are applied to the input 21 of the accumulator for operation in the next beat by way of the multiplexer 20, are applied to output buffer 22, or written to an address of the RAM, the data route being as defined by the controlling data. If the data is written to the RAM rather than the output buffer, and represents only a partial, rather than completed, accumulation, then simultaneously a partial accumulation read from the same or a different RAM address is applied by way of multiplexer 20 to the adder input 21 for the next beat.

It will be seen that the accumulator is able to perform a read-modify-write operation on the data stored in the RAM over two beats, that is, in one beat read a partial accumulation at a specific RAM address and in the next beat add (or otherwise) to it and return it to the same RAM address.

Where suitable circuitry exists to permit the read modify-write operation to be effected within a single beat then this may be adopted as a matter of course for all data operated upon and the register 18 and multiplexer 20 omitted. However, where available circuit components are limited by technology such that a read-modify-write operation takes in excess of one pipeline beat, two pipeline beats of the system are occupied and the time taken for reading from, and writing to, the same address is in general considered excessive when successive pieces of data are to be accumulated. The loop between the accumulator register 19 and address input 21 through the multiplexer 20 therefore permits accumulation to be effected within a single beat.However, where the data is to be split between different functions and stored data is read from, and written to, different addresses the aforementioned single beat "modify-write" and "read-modify" operations are used in parallel to advantage.

Referring again to Figure l(a) and equations (1) to (3) and to Figure l(b) it will be seen that in beat 1 the data word a00 is multiplied by multiplicand maOO and applied to the input 16 of the accumulator adder. In beat 2, the first data/multiplicand product is added unchanged to the accumulator register 18 and fed back to input 21 as the new product a01x m is formed and applied to input 16. In beat 3 the sum a00x #aOO + a01x ma01 is formed, stored in register 18 and reapplied to input 21 and the product a02x ma02 formed and applied to input 16.In beat 4 the sum a00x ma00 + a01x maOl + a02x maO2 is formed, stored in register 19 and reapplied to input 21 and the product a03x maO3 formed and applied to input 16. In beat 5 the sum a00x maOO + a01x maOl + a02X maO2 + a x m is formed, stored in register 18 and written as a partial sum into an address of the RAM defining Fn(a). In the same beat the contents of a different address defining Fn(b), initially zero, are read and applied via multiplexer 20 to adder input 21 and the products of the beat 5 operation, in 15 boox mob00, is applied to the input 16.In beat 6 the sum boox mob00 + (partial sum = 0 read from RAM) is formed in the accumulator register, recirculated to input 21 and the newly formed product b01x mbOl applied to 16.

It will be seen that this process continues as above when in beat 9 the partial sum of the Fn(b) data products is rewritten to the Fn(b) address while the partial sum of the Fn(c) data products, initially zero, is read from a predefined Fn(c) address in the RAM to the adder input 21.

On the twelfth beat the multiplication effected is a10x malt) the partial sum of the Fn#(c) data products is rewritten to the Fn(c) address while the partial sum of the Fn(a) data products previously stored is read and applied to the adder input 21 ready to be added to the product a10x mal0 on the fourteenth beat.

These time relationships between the input data words and pipelined processing beats are illustrated graphically in Figure l(b) in which the multiplication (x) and addition (+) operations, and where the result thereof are directed, are shown aligned with the time axis of data word input to the processor circuit.

The total number of data words required to be processed to provide each function Fn(a), Fn(b) etc., may be defined by a predefined number of words or by a time for which the data is accumulated. If the data words arrive regularly and in synchronism with the processor clock then the functions are in practice reduced to the number of data words processed and the end of processing is defined by a count of operations and the store 13 is arranged to store, as an alternative to writing the contents of the accumulator register 18 written to the RAM, the instruction that the accumulator register 18 is to be written to the buffer 22.

The digital signal processing circuit described with reference to Figure 2 is susceptible to modification without departing from its important properties of speedily handing data of time interleaved functions. One particular form of input data words may be where the sequence of data words may be only one word long, that is where the data stream is of the word form a, b, c, a, b, c, a etc. In this case each output of the accumulator representing a partial sum is written to the appropriate function memory address as the partial accumulation of another function is read for the next data word before it too is returned to the memory. It will be seen that such a formation of input data words involves no recirculation by-passing the memory and accordingly, if input data only of such a form is to be applied the circuit may be constructed without the register 18 and multiplexer 20.

One useful modification concerns teasing RAM addresses when a function has been formed and output for partial sum of subsequent functions. Instead of resetting the RAM address to zero before it is read for the first accumulation of the new function the control store may arrange a further input 21' to be driven to zero. The accumulation proceeds for the succession of input data words for that function which, when interupted, is written to the RAM address and overwrites the remaining partial sum of the previously output function.

The pipelined arithmetic operations which take place on consecutive beats may also be arithmetic operations other than the multiplication and addition shown or such a combination as shown and may be logical operations which are analogous to arithmetic operations.

Figure 3 shows a more generalised arrangement 30 of the signal processing circuit of Figure 2, in which an indeterminate number of arithmetic logic units U1, U2, ... Un are coupled with their operations pipelined as outlined above whereby the constituent factors of the function take a greater number of beats to form individually but the speed of operation, that is, the rate at which data passes through the processor and formation of functions from the interleaved data is essentially unchanged.

The first arithmetic logic unit U1 receives data from an input register 31 and each subsequent one receives at least one piece of input data from the preceding unit or some intermediate storage facility such as a register, the other inputs 321, 322, ... 32 in each unit receiving data words from other input registers, intermediate storage registers, coefficient stores or from other arithmetic logic units representing the results of previous operations in subsequent units or later operations in earlier units as appropriate.

Where a register 33 is associated with the final arithmetic operation unit U , in order to by-pass the RAM 34 n for successively operated-on data words, the multiplexer 35, which provides a data path from either or read port 36 of RAM 34 or the register 33, may be anything from a 2:1 to 2:n path multiplexer which responds to an appropriate operating instruction to apply one of the two source paths to at least one of the arithmetic logic units U1 ..... U or any n intermediate register associated therewith.

Outputs may be taken from other than the final arithmetic logic unit U for use or combination with other n data externally.

The arithmetic or logic operations of the units may be performed on the data retaining the resultant full word length throughout the sequence of operations and the function output taken from the register 34, and/or elsewhere may include a programmable shifter 37 to limit which bits of the function word are extracted, enabling the output significance of the function to be controlled to fewer bits than will normally be available without resorting to floating point arithmetic.

As a further option a data path 38 may be provided from the shifter 37 to the multiplexer 35 which would then be an addressable three-input device.

A multiple word FIFO 39 may be employed to buffer the output where subsequent circuitry is in fact operating at different processing speed or phase.

It will be appreciated that the relatively simple operations and data shifts which take place in the digital signal processor, particularly one with as few arithmetic logic units as in Figure 2, take place at a speed which what may be higher than the rate at which data words are provided for processing by any particular source or data transmission bus and the interleaving in time between input data may be equally effective in dealing with different data word streams interleaved by multiplexing into the signal processor.

The input register 31, together with p-l additional input register 311 ... 31 may provide data words by way of p p:l multiplexer 40 to the first arithmetic operation unit. For instance, if the data is provided from two sources, that is, p=2, the data may be provided to each input register from two sources which are put of phase with the. prosessing circuit or transmit the data at a lower rate, permitting performance of two independent processing functions with the data words from two sources interleaved in time. Multiple and multiplexed input registers may alternatively be used to hold convenient lengths of a long data word which is processed by accessing each of the registers in turn.Alternatively or additionally the other input to the arithmetic operation unit U1 or any other unit may likewise be by way of a multiplexer, and either receive input data words to be processed or provide processing coefficients for operating on the data input words at 31. In particular, where the input data words are received at intervals long in comparison with the processing rate of the circuit the same input data word in the register may be subjected to a sequence of operations by the input arithmetic logic unit for each of multiple coefficients. As an extention of this multiple input words and multiple coefficients (multiplicands or the like) may be grouped together for processing, such as in pairs for processing real and imaginary parts of complex numbers represented by the data words.

Thus by suitable control of such input multiplexers a number of combinations of the arithmetic operation can be effected between the data words before they are replaced by new input data or data words from several sources producing words more slowly than the processing circuit operates can be processed together. It will be seen that with suitably configured arithmetic logic units and interconnections may perform data processing according to well established algorithms representing, say Fourier Transforms and IIR filters.

As indicated hereinbefore the digital processing circuit described with reference to Figure 2 is particularly suited to processing data words by multiply-and-accumulate operations into functions which are of the type required in reception beam forming with an array of transducers and lends itself to convenient implementation of a novel method of processing array transducer signal samples to define beam direction with high resolution and little processing delay.

It is well known in the sonar and radar arts to deploy one or more spatially defined arrays of transducers, to sample the signals generated at the transducers at intervals relating to the passage of an energy front past the array in the form of single bit or multiple bit data words and to process the array transducer signal sample words digitally in order to provide, at longer intervals, directed-beam samples which relate specifically to wave fronts travelling in specified directions with respect to the array.

There are several well known general methods of defining beam directions by combining samples taken from different array transducers at different times within a directed-beam sampling interval.

One such method is the phased-sampling method wherein the transducers of the array are sampled at times, being delays from the wavefront first crossing the first transducer, corresponding to the times the wavefront is expected to cross the subsequent transducers when from the specified direction.

One example of apparatus which operates according to this philosophy is given in British Patent Specification No. 1,572,307.

An alternative operating philosophy is the so-called linear- or time-interpolation method whereby samples of all the transducer signals of the array are taken at each of regular array sampling intervals and the delay variations associated with different transducers to define the beam directions are found by interpolation between transducer samples for the surrounding sampling times.

The present method is an adaptation of the time interpolation method with a view to easing the processing of the transducer samples into directed beam samples and will be better appreciated from consideration of time-interpolation beam forming.

Referring to Figure 4(a) this shows a typical linear array of four transducers a, b, c and d accross which a wavefront w passes in a direction making an angle with the array. Assuming a uniform wave velocity it will be seen to cross the successive transducers with delays between crossings, being a function of the wave front velocity through the transmission medium, the separation of the transducers and the direction of travel of the wavefront.

If the transducers are sampled as the wavefront crosses them, the successive wavefront positions being shown by broken lines, and the samples for the appropriate transducers summed then the sampled signal level due to the wavefront from the given direction will be emphasised at the expense of wavefront from other directions. Instead of sampling the transducer signal levels at predetermined times when the wave front is expetced to cross specific transducers, which is phased sampling, the transducers may be sampled at regular intervals to, tl, t2, t3 etc.

In order to effect response to a particular direction by summing the transducer sample levels at the particular instants the wavefront is incident thereon the samples taken from each particular transducer at neighbouring sample times are interpolated to give an effective incidence time.

In the Figure it will be seen that the effective time of wavefront incidence on transducer b is between actual sampling times t0 and tl, approximately some 80% of the time between them. The samples produced by transducer b at times to and tl are thus combined in the inverse ratio, that is, 80% of sample taken at tl and 20% of sample taken at t0, to give an interpolated sample for transducer b.

Similarly interpolation samples for transducers a c and d may be formed if the wavefront is not incident upon them precisely at the regular sampling times. As all the transducers are sampled at each sampling interval it is only when the wavefront has travelled across the array that the directed reception beam sample can be formed but whilst transducer samples are being taken at later times for the contribution of transducers c and d to the directional reception beam the samples taken of transducers a and b may be contributing to a subsequent directed beam sample.

Referring now to Figure 4(b) this shows a time-space matrix of samples taken from the array transducers a to d of Figure 4(a) and sampling times t0 .... t8 the samples being indicated by circles at matrix nodes.

The positions of the interpolated crossing times for the transducers are shown by crosses and it will be seen how samples at adjacent sampling times may be combined to provide the effective interpolated samples.

Also it is seen clearly which effective interpolated transducer samples are to be summed to provide the directed beam sample, so that at time t3 when all contributory transducer samples have been taken those from from transducer a at time tO' from b at times t0 and tl, from transducer c at times t and t2, and from transducer d at times t2 and t3 are each multiplied by the appropriate coefficient to effect interpolation for the appropriate transducer samples and then summed to provide the directed beam sample. It is also well known for samples from neighbouring transducers at any delay time to contribute to the directed beam sample, their level of contribution being controlled by shading coefficients by which they are multiplied. For the purposes of this explanation such contributions are ignored.

As shown by the broken and chain dotted lines other beam samples may be formed from transducer samples taken in overlapping periods of sampling although each transducer sample taken at any particular array sampling time is used only once in providing a directed beam sample.

The array of Figure 4(a) although suitable for the purpose of outlining time interpolation method of directed beam sample formation is not necessarily representative of practical transducer arrays which may have many more transducers and have non linear dispositions whereby the directed beam line drawn through any time-space matrix there for may well be other than a simple straight line and with such full utilisation of transducer samples in forming multiple beam samples.

Returning to the present invention reference is made to Figure 5 which shows a time-space matrix similar to that of Figure 4 but in which the directed beams have a more representative non-linear path. The matrix is also divided into sections in accordance with the relationship between transducer samples and the directed beam sample to which they contribute, four directed beam samples BSO, BS1, BS2 and BS3 being produced by processing transducer samples received at array sampling times t0, t4, t8, t12 respectively.

It will be seen that one directed beam sample, say beam sample BS2, is formed over nine array sampling intervals t0 to t8 and that the interpolation between samples from different transducers from different sampling times is effected by determining fractions of the sample values available, conveniently called sample factors, to be combined or summed with other sample factors which may be fractions of or whole sample values to define the beam sample.

It will also be seen that although the directed beam sample BS2 may require sample factors from array samples of several sampling intervals to form, successive directed beam samples, such as BS1, BS2, BS3 etc, may be made available at smaller intervals than the time taken to form any individual sample.

In general. the array is sampled more frequently than the directed beam sample period and each directed beam sample may take longer than the beam sample period to form.

Traditionally the formation of a beam sample has been effected by storing all of the array samples for a number of successive array sampling intervals, that is, effectively reproducing the time-space matrix in a store and when the samples have been stored for an appropriate number of intervals reading them and processing them by forming said sample factors values and summing them to give a directed beam sample. Such interpolation is effected concurrently with applying shading coefficients to these and any other samples contributing to, and summed therewith to form, the directed beam sample.

It will be seen that the shading coefficient may be conveniently combined with the interpolation coefficient by which the sample factor is formed and that by a single multiplication the transducer sample may be formed into a sample factor incorporating both array shading and interpolation.

In accordance with the present invention the array samples for any array sampling time interval t0, tl, t2 etc. are taken from the array in sequence or at least processed in sequence. In particular the transducer samples are each multiplied by their appropriate shading and interpolation coefficients as the samples are formed and a corresponding time-space matrix defined as in Figure 5 with transducer dispositions a to d and complete array sampling time intervals t0, tl etc. but with each matrix location holding, instead of transducer samples, the sample factors which merely require summing with all others contributing towards that directed beam sample.Considering the summation it will be seen that for each sample time interval successively applied sample factors may simply be accumulated as they arrive but that in any one sampling interval the sample factors associated with any one directed beam sample are, like the transducer samples from which they derive, interleaved with the sample factors of another beam sample.

Thus considering the formation of sample factors in the array sampling periods t2 and t3, in t2 the first two sample factors contribute towards the beam sample BS2 output at t8 and are summed or accumulated as the transducer samples arrive and the factors are formed in sequence. The next two sample factors contribute towards beam sample BS1 and are summed with the partially accumulated beam sample as they are formed.

The first sample factor in t3 is associated with the directed beam sample BS3 output at t12 and the partial sum thereof is temporarily stored, the next two are associated with BS2 being accumulated with the retrieved partial sum and restored and the final one associated with BS1 is accumulated with the retrieved partial sum there for and also restored. At t4 a similar distribution of sample factors between partially formed beam samples is effected but when the sample factor due to transducer d is added to the sum the beam sample BS1 is completed and the accumulator sum/beam sample provided.

It will be appreciated that the number of transducers or array sampling intervals per directed beam sample are open to variation but that the processing reduces to multiplication of each transducer sample by an appropriate coefficient to define the sample factors therefor, summation with previously accumulated sample factors contributing towards the same beam sample and storing and retrieving the partial sums as the successively received transducer samples produce factors associated with different directed beam samples.

It will be seen from the above that this processing of transducer samples corresponds with that outlined in relation to the interleaved data words of Figure 1 and the processing thereof by the signal processor of Figure 2.

It will also be appreciated that the time-space matrix of the method does not require to exist as a physical storage entity for the sample factors which are accumulated as they are formed and which require therefore only storage for the partial accumulations. However, a notional matrix may be defined in order to determine the coefficients or multiplicands by which each of the samples taken from specific transducers and at specific times are to be multiplied to form the sample factors.

Referring again to Figure 2 it will be seen that if the input data words applied by way of input register 11 comprise the transducer samples as digitised by an ADC and the multiplicands m(data word) applied by way of input register 12 comprise the combined shading and interpolation coefficients for each transducer, determined in advance from the position of the transducer in the array and the beam direction in relation to it in a notional matrix corresponding to Figure 5, and pre-programmed into store 13, then the circuit of Figure 2 is able to implement this method and produce the directed beam samples with little complicated, and therefore time-consuming, processing with the array samples.

Some of the variants shown in the more generalised processing circuit of Figure 3 may be included where beneficial, such as outputting the directed beam sample by way of a shifter 37 to regulate output word significance and/or multiplexing the transducer samples at the input to optimise the use of the faster signal processing circuitry with comparatively slower transducer sampling and digital conversion circuitry and busses and permit the processing of real and imaginary parts of complex samples formed from single transducer samples or use each transducer sample in respect of many directed beam samples.

Although the signal processing circuit, such as shown in Figure 2, has been described as processing data for beam samples of one beam direction the use of each input data word from any particular transducer to contribute towards several directed beam samples is apparent by multiplying the input sample by a succession of suitable coefficients to provide a sample factor for the plural beam directions as required. In general this may lead to successively formed sample factors applied to the accumulator not contributing towards the same beam sample and therefore being accumulated with partial beam samples read from the RAM and subsequently stored rather than successive accumulation by way of the accumulator register and multiplexer, not that this reduces processing speed as the successive partial directed beam samples are at different RAM addresses which can be simultaneously written to and read from.

The above described method of beam forming and its implementation by way of the circuit of Figure 2, modified as appropriate, is effected with each transducer sample in the form of a multiple-bit digital data word and said word being processed by multiplication by coefficient before accumulation to effect a directed beam sample in accordance with full time interpolation of the transducer samples.

In accordance with emphasising the generality of the digital processing circuit of the invention another beam forming process, that is, the formation of directed beams samples from transducer samples will now be considered.

Sonar array arrangements are known in which the transducer samples are produced as one-bit digital words, being a binary 1 or 0, and the transducers are sampled so as to produce a multiple-bit word for processing corresponding in length to the number of transducers.

A time-space matrix similar to Figure 4 may be derived as shown in Fig. 6 except that now transducer samples taken at the uniform array sampling times t0, tl, t2, etc. are utilised without time interpolation and a directed beam sample formed by adding the appropriate transducer sample bits for the appropriate sampling times associated with the delays expected between transducers for the particular beam direction, that is, different bits of the multiple-bit array sample word for different array sampling times. It will be seen that in order to utilise the array sample word of any sampling time the bits corresponding to transducers not involved in forming the directed beam sample have to be masked to leave in effect only the required bit or bits for accumulation.

The digital processing circuit for processing such multiple bit words is shown schematically at 50 in Figure 7 and is similar to Figure 2 except that the input is by way of two registers 51, 52 and a multiplexer 53. The use of multiplexed input, outlined above in relation to Figure 3 permits a multiple-bit transducer word longer than the normal word length for common digital data busses, say, a 25-bit word may be provided as in effect two words on 16 bit input busses and the part words dealt with by the processor in sequence.

The arithmetic logic units also differ in that the one 54 receiving the input data words is a masking unit to which appropriate bit masks are provided by the control store 55, addressed in sequence as described above for multiplicands.

Any mask when applied to a multiple bit input data word masks off those bits not associated with the formation of a particular beam sample and permits the relevant bit or bits to be forwarded to the second arithmetic logic unit 56. This functions within an accumulator but comprises a set-bit counter for the masked word portion forwarded by the masking unit 54, that is, effectively sums the sample levels.

For any word portion forwarded to the counter 56 the transducer samples bits, if they are present and counted, are accumulated with any existing partial accumulation stored as a result of a preceding-beat operation.

Reference to Figure 6 will show that a beam sample will usually take several array sampling times to form and that many beam samples for a particular direction may be in formation at any time.

For a particular input data word, which may for example be the first 16 bits of a 25 bit array sample word at time to a succession of masks are applied in successive beats to forward the relevant bits comprising the beam samples in formation at that time. These are treated for the purposes of accumulation as interleaved signals and the partial accumulations are stored at appropriate addresses in RAM 57, being read again in synchronism with the forwarding of the appropriate contributory beam sample bits.

Because sucessively forwarded (unmasked) portions of an input data word will not relate to the same beam sample there is no requirement for the accumulator register 18 and multiplexer 20 shown in the arrangement of Figure 2.

It will be appreciated that the directed beam forming method described or the processing of signals by the circuits as outlined to derive directed beam samples is not limited to sonar arrays and the particular transducers employed herein but applicable with suitable adaption to all transducer arrays customarily considered equivalent.

Claims (25)

Claims:

1. A digital data processor including a first and a last arithmetic logic unit (ALU), each having first and second inputs and an output, connected for pipelined operation whereby a first input of the first ALU is connected to receive input data to the processor and a first input of the last ALU is connected to receive data derived from the first ALU, a pipeline output register associated with the last ALU to receive the results of the operation of the last ALU, feedback means including a feedback data path to an input of a component of the pipeline and a dual port memory, arranged to write data from a write port to a selected memory address and read data from a selected memory address to a read port in the same beat, the write port of the memory being selectably connected to the pipeline output register to receive data therefrom for storage and the read port of the memory being connected to the feedback data path to provide stored data thereto, output means selectably connected to the pipeline output register, and control means including a store of sequential control instructions operable to provide control instructions in each beat to select either the feedback means or output means to receive the pipeline output register data, the selection instructions to the feedback means defining write and read addresses of t# memory thereof.

2. A digital data processor as claimed in claim 1 in which the feedback data path is to a second input of the last ALU.

3. A digital data processor as claimed in claim 1 or claim 2 in which the first ALU is connected to provide in one beat data for the first input of the last ALU to be operated on by the last ALU in the next beat.

4. A digital data processor as claimed in any one of the preceding claims in which the control means is arranged to store with the control instructions for each pipeline beat data for use in the pipeline beat and apply said data to the second input of the first ALU.

5. A digital data processor as claimed in any one of the preceding claims in which the control means is arranged such that an instruction to be performed in a single pipeline beat in which the memory of the feedback means is selected includes performing the arithmetic/logic operation in the last ALU, defining a memory write address and storing the data contents of the pipeline output register thereat, defining a memory read address, different from the write address, and applying the data contents thereof to the feedback data path.

6. A digital data processor as claimed in any one of the preceding claims in which the feedback means includes a feedback multiplexer in the feedback data path having a first input connected to the read port of the memory and a second input connected to the pipeline output register, and an input selection control connected to be selected by the control means as a supplemental function of selection of the feedback means, selection of said second input of the feedback multiplexer being instead of selection of the memory to write the contents of the pipeline output register.

7. A digital data processor as claimed in claim 3 when dependent on claim 2 in which the first ALU is a multiplier of the contents of the two input registers and the last ALU is an adder arranged to form with the pipeline output register and feedback means an accumulator of the multiplier products of successive pipeline beats.

8. A digital data processor as claimed .n claim 4 when dependent on claim 2 in which the first ALU is a masking unit of data to the first input thereof by said stored data applied to the second input and the last ALU is a set-bit counter arranged to form with the pipeline output register and feedback means, an accumulator of data bits output by the first ALU.

9. A digital data processor as claimed in any one of the preceding claims in which the output means includes a shifter.

10. A digital data processor as claimed in claim 9 when dependent on claim 6 in which the feedback multiplexer includes a third selectable input connected to receive data from the shifter and the input selection control is permitted to respond to selection by the control means as a supplemental function of selection of the feedback means to select said third input instead of said first or second input and apply said data from the shifter to the feedback data path.

11. A digital data processor as claimed in any one of the preceding claims in which the first ALU has associated therewith a plurality of input registers for holding input data from different sources and input multiplexer means having an input for each register and an output connected to the first input of the first ALU as the control means is arranged to permit the control instruction for each beat to include selection of an input to the input multiplexer.

12. A digital data processor substantially as herein described with reference to and as shown in any one of Figures 2, 3 or 7 of the accompanying drawings.

13. A method of forming a directed reception beam sample for an array of transducer elements, by time interpolation of transducer signal samples taken at predetermined time intervals comprising deriving, in advance of operation, for a particular beam direction and for each of succeeding intervals at which the transducers are to be sampled and the samples contribute towards the beam sample, coefficients, representing the proportion of individual transducer samples taken in the interval that are utilised in forming interpolated values thereof, corresponding to transducer sample values at interpolation times intermediate the sampling intervals, storing the coefficients and, in operation, sampling the transducer signals at each of said sampling intervals to derive transducer samples therefrom, processing the transducer samples in the sampling period by operating on them by the coefficients defined for the individual transducers for the time interval to form sample factors representative of a component of directed beam samples and accumulating sample factors associated with the beam directions as they are formed until a predetermined accumulation of sample factors provides a directed beam sample.

14. A method as claimed in claim 13 in which the transducer sample processing comprises, in any time interval for which plural transducer samples are formed, retrieving for each sample a stored coefficient predetermined therefor, operating on each transducer sample by its coefficient to form a sample factor associated with the particular beam direction and updating a partial accumulation of the sample factors associated with an individual beam direction from that and preceding time intervals.

15. A method as claimed in claim 14 for forming directed beam samples for a plurality of directions contemporaneously comprising storing in memory each updated partial accumulation of sample factors associated with each direction temporarily as processing of transducer samples relating to a different direction is carried out with updating of an appropriate partial accumulation removed from said memory.

16. A method as claimed in claim 15 in which the updated partial accumulation in the memory is stored as a different partial accumulation, associated with a different beam direction, is read for the next sample factor to be formed and associated with that beam direction.

17. A method as claimed in claim 16 comprising storing the updated partial accumulation in the memory only when the next sample factor to be formed is associated with a different beam direction.

18. A method as claimed in any one of claims 13 to 17 in which the transducer samples are operated on by multiplying them by their respective coefficients.

1' A method as claimed in claim 18 in which the coefficients for multiplication include a factor for shading the transducer as well as interpolation.

20. A method of forming directed reception beam samples for an array of transducer elements, sampled at predetermined time intervals, by time interpolation of transducer signal samples substantially as herein described with reference to Figures 4 and 5 or Figure 6 of the accompanying drawings.

21. A digital data processor as claimed in any claim 4 when dependent on all preceding claims in which the input is arranged to receive input data comprising samples from transducers forming part of a reception array and the data from the output means represents directed array beam samples and the control means is arranged to store instruction defining routes for the processed data defining the formation of directed beam samples and predetermined data for operating on the transducer sample input data as coefficients to provide factors in the formation of said directed beam samples.

22. A digital data processor as claimed in claim 21 configured and with the control means programmed to perform the method of any one of claims 13 to 15.

23. A digital data process or as claimed in claim 21 when dependent on claim 5 when dependent on all preceding claims configured and with the control means programmed to perform the method of claim 16.

24. A digital data process or as claimed in claim 21 when dependent on claim 6 when dependent on all preceding claims configured and with the control means programmed to perform the method of claim 17.

25. A digital data process or as claimed in claim 21 when dependent on claim 7 when dependent on all preceding claims configured and with the control means programmed to perform the method of claim 18 or 19.