GB945527A - Improvements in or relating to multipliers - Google Patents

Improvements in or relating to multipliers

Info

Publication number
GB945527A
GB945527A GB3573561A GB3573561A GB945527A GB 945527 A GB945527 A GB 945527A GB 3573561 A GB3573561 A GB 3573561A GB 3573561 A GB3573561 A GB 3573561A GB 945527 A GB945527 A GB 945527A
Authority
GB
United Kingdom
Prior art keywords
circuit
register
multiplicand
digits
pair
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3573561A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STC PLC
Original Assignee
Standard Telephone and Cables PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Standard Telephone and Cables PLC filed Critical Standard Telephone and Cables PLC
Publication of GB945527A publication Critical patent/GB945527A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
    • G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/4915—Multiplying; Dividing

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)

Abstract

945,527. Binary multipliers. STANDARD TELEPHONES & CABLES Ltd. Oct. 4,1961 [Dec. 29, 1960], No. 35735/61. Heading G4A. In an electrical binary multiplication circuit, successive pairs of the multiplier digits control entries of the multiplicand, the pair of digits "11" (i.e. decimal 3) causing addition of four times the multiplicand and subtraction of once time the multiplicand. The mathematical theory of the multiplication method employed is discussed in detail in the Specification. The circuit described employs a multiplier/product register 102, a multiplicand register 101 and a partial product register 103. The registers 101-103 comprise bi-stable flip-flop circuits. Commencing with the lowest pair, successive pairs of multiplier digits are supplied from flip-flops a,b of the register 102 to a logical circuit 104, a circuit including a delay 106 being arranged to increase by one unit the value of the pair if the previous pair was "11". Outputs 12-0 to 12-3 of the circuit 104 are applied to a transfer block 105 to control an appropriate transfer from the multiplicand register 101 to the partial product register 103. The multiplicand 101 is supplied in direct or complement form from a transfer circuit 111 unchanged or via circuit 112 or doubled via a circuit 113 to a mixer circuit 114 coupled to the partial product register 103. According as the multiplier digits are "01", "10", "11", the multiplicand is transferred directly via circuit 112, directly via circuit 113, and in complement form via circuit 112 together with a direct transfer via circuit 112 in the next step. Numbers stored in the partial product register 103 includes a sign digit #. Under certain circumstances, a round carry from the sign digit flip-flop via a line 17 and "and" gate 110 controlled by the lowest digits a, # in the register 103 is applied to the lowest order α. When a transfer step has been completed, the two lowest digits α, # in the register 103 are applied together with the sign digit # to a logical circuit 107, whose output supplies the related pair of digits f, g, in positive form for the product, to the register 102.
GB3573561A 1960-12-29 1961-10-04 Improvements in or relating to multipliers Expired GB945527A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR848276A FR1283965A (en) 1960-12-29 1960-12-29 Binary multiplication circuit

Publications (1)

Publication Number Publication Date
GB945527A true GB945527A (en) 1964-01-02

Family

ID=8745697

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3573561A Expired GB945527A (en) 1960-12-29 1961-10-04 Improvements in or relating to multipliers

Country Status (4)

Country Link
CH (1) CH395592A (en)
DE (1) DE1151398B (en)
FR (1) FR1283965A (en)
GB (1) GB945527A (en)

Also Published As

Publication number Publication date
CH395592A (en) 1965-07-15
FR1283965A (en) 1962-02-09
DE1151398B (en) 1963-07-11

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