GB933707A - Improvements in or relating to apparatus for defining predetermined instants in a binary signal sequence - Google Patents
Improvements in or relating to apparatus for defining predetermined instants in a binary signal sequenceInfo
- Publication number
- GB933707A GB933707A GB865861A GB865861A GB933707A GB 933707 A GB933707 A GB 933707A GB 865861 A GB865861 A GB 865861A GB 865861 A GB865861 A GB 865861A GB 933707 A GB933707 A GB 933707A
- Authority
- GB
- United Kingdom
- Prior art keywords
- signal
- pulse
- sequence
- preliminary
- pulses
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B14/00—Transmission systems not characterised by the medium used for transmission
- H04B14/02—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation
- H04B14/06—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation using differential modulation, e.g. delta modulation
- H04B14/062—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation using differential modulation, e.g. delta modulation using delta modulation or one-bit differential modulation [1DPCM]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
933,707. Pulse modulating systems. TELEFUNKEN G.m.b.H. March 9, 1961 [March 12, 1960 (2)], No. 8658/61. Class 40 (5). In a synchronizing arrangement for a pulse code modulation system a predetermined sequence of binary signals is inserted at regular intervals in the coded signal series, said predetermined sequence being divided into a preliminary sequence and a final sequence having a smaller number of digits than the preliminary sequence, the coincidence of the final sequence with the setting of a register being utilized for synchronizing when the presence of the preliminary signal has been detected. As described the preliminary signal is the 32-digit sequence 101010 . . . . and the final or " tripping " signal is the sequence 1001. At the receiver the incoming pulse signals are supplied via terminal 1 to a device 2 which produces a potential on lead 3 or 3a dependent on whether the signal at that instant is a " 1 " or " 0." A pulse generator 4 generates pulse trains T, T 1 which are synchronized in known manner with the incoming signal pulses by a phase-comparison circuit 5. The pulses T are fed to a shift register comprising flip-flops 7 to 10 whose outputs are connected to a coincidence gate 11 in such manner that the tripping signal will cause four coincident pulses to appear at the gate 11. An OR-circuit 15 is connected to the output of the shift register element 10 and applies a pulse to set a bi-stable device 16 whenever the signal at 10 has changed from " 1 " to " 0 " or from " 0 " to " 1 " as during the preliminary synchronizing signal, the time-shifted pulses T 1 being supplied to the other input of the bi-stable device 16. The pulses T 1 also control a counter 14 which is arranged to count either forward one or backward two according to whether the bi-stable device 16 is set to " 1 " or " 0 " just before the arrival of a pulse from the OR-circuit 15. The counter is such that it will only count as far as zero in the backward direction. When the counter has made a count of 32 it applies a pulse to a switching device 13 and a pulse lasting for the duration of several digits is supplied as a coincidence signal to the gate 11. If a short alternating type of signal should occur immediately before the correct preliminary signal the lengthening of the pulse from 13 causes it to be maintained at the gate 11 until the tripping signal has reached the register 7 to 10. An arrangement suitable for the counter 14 and its changeover device is described, Fig. 3 (not shown). The arrangement is applicable to a delta modulation system transmitting a difference signal in which it is required at predetermined intervals to transmit a signal giving an indication of the signal amplitude.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DET18043A DE1115297B (en) | 1960-03-12 | 1960-03-12 | Method and arrangement for identifying certain points in time in a binary signal sequence |
DET18044A DE1115301B (en) | 1960-03-12 | 1960-03-12 | Circuit arrangement for recognizing a regular series within an irregular sequence of binary characters |
Publications (1)
Publication Number | Publication Date |
---|---|
GB933707A true GB933707A (en) | 1963-08-08 |
Family
ID=25999385
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB865861A Expired GB933707A (en) | 1960-03-12 | 1961-03-09 | Improvements in or relating to apparatus for defining predetermined instants in a binary signal sequence |
Country Status (2)
Country | Link |
---|---|
BE (1) | BE601262A (en) |
GB (1) | GB933707A (en) |
-
1961
- 1961-03-09 GB GB865861A patent/GB933707A/en not_active Expired
- 1961-03-13 BE BE601262A patent/BE601262A/en unknown
Also Published As
Publication number | Publication date |
---|---|
BE601262A (en) | 1961-07-03 |
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