GB925161A - Improvements in or relating to calculating machines - Google Patents

Abstract

925,161. Electronic calculating - apparatus. BELL PUNCH CO. Ltd. June 15, 1959 [June 19, 1958], No. 19656/58. Class 106 (1). Fig. 1 shows schematically a keyboardoperated desk calculator for carrying out addition, subtraction, multiplication and division on numbers of up to 11 decimal digits. The keyboard is shown in Fig. 12 and includes 11 set of keys 1K to 11K used for entry of all numbers except multipliers (these keys are normally self-locking for multiplication and division), keys MK0-MK9 on which a multiplier is entered digit-by-digit most significant digit first, operation keys 1-4, decimal point keys DK1-DK11 with corresponding lamps DL1-DL11 and decimal digit display tubes 1RE-12RE of the type having ten digitshaped glow cathodes for recording the calculation result. Referring to Fig. 1, each denomination bank of keys 1K &c. is associated with one decimal counting tube 1R &c. of the register, into which pulses corresponding to the key depressed are entered in appropriate cycles of the apparatus. Timing is controlled by a pulse generator PG which in each cycle of ten pulses gates to switch 1S on each of the nine lines the number of pulses shown against its terminal, the tenth pulse being delivered to timer T to switch to the next cycle. Timer T energizes successively the " cycle " outputs T1-T15 which gate the pulses from PG into the counters 1R-11R according to the keys depressed, and also time any necessary shift in multiplication or division. Addition.-Depression of key 1 (Fig. 12), operates switch 1S to route 1 pulse in each cycle to decimal-digit-1 keys, and correspondingly. When a digit key is depressed switch SS opens so that timer T, previously held at output O, commences to cycle through T1 &c. At cycle T2 any number entered on order 1K is counted into 1R by gate 1GA, and correspondingly at T3-T12 (orders 3-10 are not shown), and at T15 the pulse generator is stopped through gate SG. When the digit key is released SS closes to return T to T0 and the pulse generator re-starts. This is repeated until all the digits of addend and augend have been counted into the register 1R-12R; any necessary carries being transmitted from the differentiated output at the " 0 " cathode of a tube such as 1R to the input amplifier (2A) of the next denomination, 12R receiving any carries from 11R. Subtraction.-The minuend is entered as above, with key 1 depressed. Key 3 is then depressed; this switches 1S so that each digit key receives the 9-complement of its value in pulses in each cycle, and also opens contacts 2S so that when a digit of the subtrahend is entered on keys 1K-11K to start the timer gate 1GE is opened in T1 to count a single pulse from the Z output of the pulse generator into 1R (PG delivers one pulse per cycle at Z), the nines complement of the entered digit being counted into the register in T2-T13. This operation is repeated for other digits of the subtrahend. Multiplication.-Key 2 is depressed to make the keys 1K-11K self-locking, put start switch SS under control of multiplier keys MK0-MK9, connect line SP with output O of a counter C and line AP with its remaining outputs, and open switches 3S and 4S. The multiplicand is entered in keys 1K-11K, and the first (most significant) digit of the multiplier entered on a key MK, which locks down. This starts a (major) cycle of the timer T; in this first cycle with C at CO, AP is de-energized to effect a shift of the contents of the register from 1R-12R to 2R-13R. This shift is effected by a changeover switch CS which delivers 9 pulses from PG first into 12R via 12GB on line S1, and when 12R is counted up to 9 is switched to S2 by a signal on line SC to count the remainder into 13R, and correspondingly in T2-T12 for shift into 12R- 2R. At this point however the register is empty, so that all counters 12R-1R are counted up to nine, except 13R which receives one Z pulse at T2 and nine pulses at T13 which return it to 0. At T14 a Z pulse is applied to 1R, and carries return 1R-12R all to zero. At T0 (the stop line is not energized in multiplication until the count in C equals the value of the multiplier digit recorded in MK0- MK9) a Z pulse through CGA counts C to C1 to energize AP instead of SP so that the multiplicand is added into the register as in " addition " above, and this action continues until the count in C (increased by 1 at each T0) reaches the value of the multiplier digit in MK, when the stop line is energized. The register now contains multiplicand X first multiplier digit. When the next multiplier digit key is pressed the contents of the register is shifted left one place in CO by the action described above, and the multiplicand again added in, and this is repeated for each multiplier digit. Division.-The dividend is first entered into the register, with key 1 depressed, the most significant digit being entered into 11R. Key 4 is then depressed; this switches 1S as for subtraction. The divisor is then entered in 11K-1K, also commencing at 1K, and division is by repeated subtraction and shift, the number of subtractions in each position being counted into 13R. When 12R registers 9 (indicating over-subtraction) the contents of the register is 9's complemented and shifted left, and the 10-complement of the number in 13R is shifted to 1R (this number is the 9-complement of the number of proper subtractions). Subtraction of the divisor is continued (equivalent to addition of the divisor to the negative remainder) until 12R again contains a 9 when the shift and complementing is repeated so that 2R contains the first quotient digit, and the 10-complement of the number of subtraction is again transferred to 1R, as the second quotient digit; this action continues. The alternate shift and subtraction is effected by connecting line SP to the odd outputs C1, C3 &c. and line AP to even outputs C2, C4 &c., of C, and advancing the count in C through CGB and CGA when subtraction and shift respectively are completed. With the dividend in the register and divisor in 11K-1K (the keys are selflocking for division), subtraction as described above is initiated by depressing key MK0 to break SS. When 12R registers a 9, CGB is opened to a Z pulse in T0 to count C up to 1 and shift and complementing takes place. This is effected by delivering pulses in each minor cycle to both S1 and S2, until line SC is energized to cut-off both outputs. The pulses are applied to 12R, 11R &c. through 12GB, 11GB &c. at T1, T2 &c., although 12R will be at 9, and hence SC will be energized to cutoff the pulses in T1. In T2, 11R will be counted up to 9, and a similar number of pulses counted into 12R, which will then register " 9-complement of no. previously in 11R minus 1." In T3, 10R is similarly counted up, and the corresponding number of pulses fed into 11R will cause a carry to be transmitted to 12R to bring this stage to the required state, the action then continuing through the stages until T13 when 13R is counted up to 0 and thus the 10-complement of the number of subtractions made passed via 1GO to 1R to be added to the 9 standing therein. A Z pulse is added at T14 and the result when 9-complemented will be the first quotient digit. 13R being now at 0, C is stepped to C2 by a Z pulse at T0 and subtraction from the register continues. Shift + complementing, and subtraction, continue as above, the quotient building up at the right of the register. The stop line is energized when the count in C reaches C7; at this point 4R-1R contains the quotient and the remainder is at 11R. Circuit elements PG, 1S, CG, CS, T, TA, C, CA, CM are shown in more detail in Figs. 3 and 5-8 (not shown); these elements include decimal counting tubes and diode gates, CS and CG also using triodes in the gating circuits. The mechanical construction of keys 1K &c. is illustrated in Figs. 10 and 11 (not shown). Fig. 13 (not shown), illustrates a 12-cathode counting tube controlling the decimal point lamps DL1-DL11, with associated circuitry. Normally the glow is on cathode 0 which has no associated lamp, but it may be transferred to any desired point by a key DK1-DK11. When multiplying, key 13 (Fig. 12), is depressed after the units have been entered on keys MK0-MK9, and thereafter the tube receives a Z pulse at each additional cycle to count the point along with the partial product; these lamps are positioned intermediate the display tubes 12RE-1RE so that they indicate the position of the decimal point in the result. A tabulator key 12 with associated keys TK0-TK11 allows shift of the contents of the register (including the decimal point) so that the decimal point may be placed in any desired position. Specifications 853,136, 925,162, 925,163, 925,164, 925,165 and 925,166 are referred to.