US3392269A - Calculating machine - Google Patents

Description

July 9, 1968 N. KITZ ETAL CALCULATING MACHINE Filed June 17, 1964 4 Sheets-Sheet 5 FIG. /c.

R IC 6 11.. m IIOH o R a 2 II'QC 9. H o On C 3 11c m 3 H INVENTORS NORBERT KITZ JOHN GEORGE LLOYD JAMES JOHN DRAGE ATTORNEY) y 1968 N. KITZ ETAL CALCULATING MACHINE 4 Sheets-Sheet 4 Filed June 17, 1964 INVEINTORS NORBERT KITZ JOHN GEORGE LLOYD JAMES JOHN DRAGE A TT OIZIVE 71S United States Patent 3,392,269 CALCULATING MACHINE Norbert Kitz, John George Lloyd, and James John Drage, London, England, assignors to Bell Punch Company Limited, London, England, a British company Filed June 17, 1964, Ser. No. 375,772. Claims priority, application Great Britain, June 26, 1963, 25,377/ 63 4 Claims. (Cl. 23592) ABSTRACT OF THE DISCLOSURE There is disclosed a calculating machine of the kind shown in U.S. Patent No. 3,296,425, in which the life of the trigger tubes and the counting tubes is prolonged by providing bursts of pulses to these tubes during standby periods. In the case of ring counters, or multi-cathode counter tubes, each burst contains sufficient pulses to return the counter to the position it was in at the beginning of the burst. The calculating machine disclosed in the present application includes a timing device, and to prolong the life of the trigger tube in the zero stage of this timing device an additional trigger tube is provided and is arranged in a bi-stable circuit with that zero stage trigger tube. During stand-by periods, these two trigger tubes become conductive alternately, and, when the additional tube is conductive, bursts of pulses are applied to the counters of the register.

This invention relates to improvements in electronic circuits employing cold cathode electron tubes and has for an object the provision of a method, and of apparatus for carrying out the method, of prolonging the useful life and the operational reliability of such tubes and circuits.

Circuits incorporating cold cathode tubes, such as trigger tubes, counter tubes, or the like, are frequently required to stand-by in a state of readiness for long periods of time. Often, one or more tubes in such circuits conduct current during stand-by, although most will be cut-off until a signal is receivevd. However, while in some circuits a particular tube is always conductive during stand-by, any one of a number of tubes in other circuits may be conductive during stand-by.

An important disadvantage associated with the use of such tubes is that they, and the circuits generally, appear to age quickly, particularly where the tubes are often conductive during stand-by; that is, the circuit characteristics alter so that after a comparatively short time operation becomes unreliable. This, of course, is a serious drawback to the use of such tubes in fast'operating counters, calculators and computers where reliable and accurate operation over long periods of time is essential.

During the development of this invention, it was found that the characteristics of cold cathode tubes and their circuits age much more slowly if the period of stand-by is frequently interrupted by periods of normal use. Furthermore, it was found that the benefits inherent in frequent normal use could be attained if the stand-by current in the conductive tubes is pulsed. But, when signals are applied to a given circuit to effect the pulsing of any tube that happens to be conductive in a particular standby period, it is difiicult to return the circuit to its original condition immediately it is required for normal use.

However, in accordance with the present invention, it is proposed to periodically generate a full cycle of short pulses and apply them to the circuit, or the tube concerned, during the stand-by period so that the circuit or tube transmits said cycle of pulses; it being understood that the number of pulses in full cycle is such that the circuit always returns to the stand-by condition at the end of the pulse cycle. For example, if a scale of ring counter or a single counter tube such as the Dekatron is employed, each full cycle would consist of 10 pulses.

Preferably, the pulses are generated. in bursts at regular intervals, each burst comprising a full cycle of pulses, and therefore it may be said that a burst of pulses is periodically recirculated during stand-by. In such a case, the recirculation period should be long in comparison with the length of the burst of pulses so that the minimum amount of delay will occur when the ma- 5 chine is required to operate normally. Care should thus be taken to ensure that recirculation cannot occur unless the circuit is actually in a stand-by condition and to ensure that the circuit is not released for normal operation until it is returned to that stand-by condition. Where the 0 normal input to these circuits is derived from a slow-speed input device such as a keyboard, there need be no interruption of the normal operation of the machine. If a high speed input device is employed, it may be necessary to provide input holding means or buffer storage 5 means by which the input signals can be held or stored until the circuits and tubes being recirculated are freed for operation.

Thus, a typical calculating machine employing electronic registry may, according to this invention, be equipped with means for periodically generating a burst of pulses during stand-by periods and for simultaneously applying said pulses to each register stage to drive that stage through a complete cycle of operation and to return said stage to its stand-by condition, means for suppressing carry pulses generated during the driving of said stages, and means for rendering said pulse generating means inoperative when an input signal is received for any one of said stages, the pulse generating means not, however, being rendered inoperative until each register stage has completed its cycle of operation. The registers may comprise multicathode indicator tubes, ring counter circuits, or combined ring counters and. indicator tubes.

However, it is often possible to obtain significant advantages in accordance with this invention where the ring counter or other circuit is such that a single known trigger tube always conducts during stand-by. In such a case, only that conducting tube need be pulsed. The pulsing of the conducting tube is achieved, according to this aspect of the invention, by forming a two-element trigger circuit of that conducting tube and a similar auxiliary tube, the auxiliary tube being preferably arranged to conduct for a substantial portion of the cycle but being prevented from conducting when a normal input signal is received by said ring counter.

According to another aspect of the invention, electronic circuits or machines which employ ring counters to dn've register stages may be improved by providing a trigger circuit in connection with the ring counter as above indicated, deriving a pulse from said trigger circuit, splitting said pulse into a number of sub-pulses exactly sufficient to the drive each register stage through a complete cycle, and applying said plurality of pulses to the register stages simultaneously.

An instance in which the aging problems referred to above become important and where the present invention may be applied to advantage is the electric calculating machine disclosed in patent application No. 226,064, filed Sept. 25, 1962, now US. Patent No. 3,296,425. Although the application of the principles of this invention to that machine will be described in some detail hereinbelow, it should be noted that this description is given by way of example and illustration only and not by way of definition or limitation. In the following description reference will be made to the accompanying drawings in which;

FIGURES la, lb and 1c taken together will be referred to as FIGURE 1 hereafter.

FIGURE 1 is a modification of the first figure of the drawings of patent application No. 3,296,425 and is a block diagram showing the principal components of a calculating machine modified in accordance with the principles of the present invention, and

FIGURE 2 is a detailed circuit diagram of part of the timing device TR together with its additional elements as diagrammatically illustrated in FIGURE 1.

The calculating machine illustrated in FIGURE 1 includes ten groups of keys, each representing a denominational order and hereinafter referred to as an order of keys, of which only the first three orders 1K, 2K and 3K) and the last two orders (9K and 10K) are shown in the drawing. The register of the machine comprises twelve counting devices of which ten can be associated with the ten orders of keys. Of these counting devices only the first three (1R, 2R and 3R) and the last four (9R, 10R, 11R and 12R) are shown in the drawing. The two counting devices 11R and 12R are provided to receive carry pulses from the counting device 10R and these two counting devices cannot be associated with any of the orders of keys. It will be appreciated that there is no limit to the number of orders of keys and counting devices which can be employed in order to obtain any desired capacity for the machine, but it will normally be desirable to make the number of counting devices two greater than the number of orders of keys in order to accommodate carry-over from the highest order counting device which can be associated with an order of keys.

Each counting device will preferably be in the form of a ring counter of the kind described and claimed in patent application No. 331,335, filed Dec. 10, 1963. Each counting device has associated therewith an input gate and in the drawing there are illustrated input gates lRG, ZRG and 3RG for the first three counting devices 1R, 2R and 3R and input gates 9RG, 10RG, 11RG and 12RG for the ninth, tenth, eleventh and twelfth counting devices 9R, 10R, 11R and 12R. The counting devices 4R to SR (not illustrated) are respectively provided with input gates 4RG to 8RG (also not illustrated).

Each of the input gates lRG to 12RG is in the form of an AND logical element. The input gate lRG, for example, is shown with one input designated H and the other input designated T1. An output is applied to the counting device 1R when both the line H and the line T1 have their potentials raised. As a result, if a positive-going pulse is applied on the line H while the input T1 is energised, the counting device 1R will have its content increased by unity.

In addition to the input gates 1RG to 12RG associated with the counting devices 1R to 12R, further gates lKG to 10KG are associated with the orders of keys. In the drawing gates lKG to 3KG are shown for the lowest three orders of keys 1K to 3K and gates 9KG and 10KG are shown associated with the top two orders of keys 9K and 10K. These gates are also in the form of AND logical elements and as a result an output is applied to a common line K if both the inputs of any of the gates are energised simultaneously. It will be seen that each gate has one input from the order of keys with which it is associated and also a second input designated in the case of the lowest order of keys t1 and in the case of the highest order of keys t10. The intermediate orders of keys have inputs designated t2 to t9 in accordance with the rank of the order. Each order of keys consists of nine keys numbered 1 to 9 and all the number nine keys, for example, are connected to a number nine number line, all the number eight keys are connected to a number eight number line and so on. The actuation of any key in an order serves to connect the corresponding number line to the output from that order of keys to the associated KG gate. When no key in any order is actuated the output from that order consists of a negative potential. The number lines are connected to a pulse generator PG which includes a master oscillator which determines the pulse repetition frequency and which is illustrated as having ten outputs numbered 0 to 9. Respective pulses from the generator appear on these outputs for respective periods of time during a cycle of operation of the pulse generator and the pulse generator PG also has an output Z on which appear nine pulses during each cycle of operation of the pulse generator. These nine pulses occur at the times when the outputs P1 to P9 are energised. These times will hereinafter be referred to as P1 to P9 and similarly the time when the terminal P0 is energised will be referred to as P0.

It will be seen from FIGURE 1 of the drawings that the P0 output of the pulse generator is connected to all the number nine keys of the orders of keys 1K to 10K; that the P1 output of the pulse generator is connected to all the number eight keys; and so on up to the P8 output which is connected to the number 1 keys.

The operation of the machine is primarily controlled by two timing devices TR and TK and a control counter CC. Each of the timing devices TR and TK may consist, for example, of a ring counter and each is provided with a number of output terminals, the out-put terminals of the timing device TR being designated T0 to T12 and the output terminals of the timing device TK being designated II to t12. Each of the timing devices is stepped forward by means of input pulses and thus provides a positive potential on each output terminal in succession. Thus initially, for example, the timing device TR provides a positive output on its output terminal T0 and, when this timing device receives an input pulse, the positive potential is removed from the output terminal T0 and appears instead on the output terminal T1. Input pulses are applied to the timing device TR from the P9 output of the pulse generator PG through a differentiating and inverting device KD2 which serves to produce delayed pulses referred to as dP9. A further input to the timing device TR is constituted by an input terminal ST2 and the timing device is held on T0 until a positive potential is applied to the terminal ST2. So long as the positive potential is present on the terminal ST2, the timing device TR can be stepped from T0 to T12 by successive input pulses dP9 and thus will be stepped forward once during each cycle of operation of the pulse generator. Thus the timing device TR will be moved completely from T0 to T12 during thirteen cycles of operation of the pulse generator PG. The various outputs T0 to T12 of the timing device TR are connected to the inputs of the gates IRG to 12RG and also to certain other gates as indicated by the references T0 to T12 shown at the input of these gates.

The timing device T K is similar to the timing device TR except that it has only twelve stages instead of thirteen. The timing device TK is stepped from t1 to r12 by means of input pulses received through an OR gate TG3 which has three inputs constituted respectively by the outputs of three AND gates TG4, T65 and T66. The AND gate TG4 has two inputs, one constituted by the dP9 output of the device KD2 and the second constituted by the terminals T1 and T12 of the timing device TR. Thus, provided the timing device TR is not on T0, the timing device K will be moved forward one step during each cycle of operation of the pulse generator PG. Since the timing device TK is prevented from moving while the timing device TR is on T0, it will also take thirteen cycles of operation of the pulse generator PG to move the timing device TK up to t12. The function of the gates TGS and TG6 is to provide a further pulse to the timing device TK under certain conditions during the period T0. These gates will be described in more detail hereinafter.

The outputs 11 to of the timing device TK are connected to the inputs of the corresponding gates 1KG to 10KG. Other connections of the various outputs of the timing device TK are as indicated by the references t1 to 111 shown at the inputs of various gates.

It will be seen that with the equipment so far described each counting device is connected to the line H in succession for the period during which the corresponding output of the timing device TR is energised, and each order of keys is connected to the line K in succession for the period during which the corresponding output of the timing device TK is energised. Thus if the timing device TR is on T1 while the timing device TK is on t1 the order of keys 1K will be associated with the counting device 1R. Further if the two timing devices are stepped together, the order of keys 2K will be associated with the counting device 2R and so on up to the order of keys 10K which will be associated with the counting device 10R. However, if it is arranged, for example, that the timing device TK is on t2 while the timing device TR is on T1, then the order of keys 2K will be associated with the counting device 1R. Under these conditions the order of keys 3K will be associated with the counting device 2R and so on up to the order of keys 10K which will be associated with the counting device 9R.

Pulses are applied to the various counting devices IE to 12R during the corresponding T periods from a common input line H which is fed from the output of an OR gate G10. The OR gate G10 has ten inputs which are constituted by the outputs of AND gates G1 to G9 and G11. It will be seen that each of the gates G1 to G9 has an input marked P0, an input marked Z, an input marked KA, or an input marked KB. Those gates which have inputs marked P0 serve to supply one pulse direct to the H line when the other inputs to those gates are energised. Similarly those gates which have Z inputs serve to supply nine pulses to the H line when their other inputs are energised. The gates having KA and KB inputs serve to supply numbers of pulses to the H line which are determined by the values of any actuated keys in the orders of keys 1K to 10K. The terminals KA and KB are connected to the outputs of a by-stable device KC and in the rest (or unset) state the output KB is energised. However the device KC can be changed over to the set state by means of an input through a differentiating and inverting device KD1 the input to which is constituted by the output of an AND gate KG1. One of the inputs to this AND gate is constituted by the K line and the other input is constituted by a terminal A the function of which will be described hereinafter. The device KC is returned to the rest state by means of a second input which extends from the P9 output of the pulse generator PG through the differentiating and inverting device KD2. The eifect of the device KD2 is that the trailing edge of a P9 pulse is operative to return the device KC to its rest state. Similarly the effect of the differentiating and inverting device KD1 is that it is the trailing edge of any pulse applied to the K input of the AND gate KG1 that changes the device KC over from its rest state to the state in which the output KA is energised.

In order to explain the manner in which pulses are applied to the counting devices under the control of the keys in the various orders of keys 1K to 10K, it will be assumed that the number six key in the order 1K is depressed, that the timing device TR is on T1 and that the timing device TK is on t1. The depression of the number six key in the order of keys 1K connects the output from this order to the P3 output of the pulse generator PG. Since the terminal t1 is energised, the P3 pulse from the pulse generator will appear on the line K. It will also be assumed that the terminal A is energized so that the P3 pulse will pass through the gate KG and accordingly its trailing edge will cause the bi-stable device KC to change over to the state in which its output. KA is energised. Further it will be assumed that the terminals M, and Y of the gate G6 are energised and accordingly, when the terminal KA is energised, this gate will open to allow the remaining pulses appearing on the Z output of the pulse generator PG to be applied through the OR gate G10 to the H line. The period during which the terminal KA is energised is such that during this period there are six pulses appearing on the Z output of the pulse generator. Since the terminal T1 is energized, the six pulses appearing on the H line are applied to the input of the counting device 1R through the AND gate lRG. Thus as a result of the actuation of the number six key in the order of keys 1K, the content of the counting device IR is increased by six.

To ensure that the number registered in any counting device is increased by one each time the counting device of the next lower order passes on to or through zero, a carry store CS is provided. This carry store is a two-state device which is set by a pulse transmitted thereto over a line C each time a counting device passes on to zero. When the carry store is set, its output CS0 is energised. The two-state device is unset by a P0 pulse applied thereto at the beginning of pach cycle of the pulse generator PG. However the arrangement is such that the output CSO of the carry store remains energised for a short period after the arrival of the P0 pulse by which it is unset. The output CS0 is connected to one of the inputs of the AND gate G9 the other inputs to which are constituted by the P0 output from the pulse generator PG and a terminal TX which will be described hereinafter. Accordingly, provided the terminal TX is energised, a P0 pulse will appear on the H line if the carry store has been set during the preceding cycle of operation of the pulse generator PG. Thus a carry pulse will be applied to any of the counting devices 2R to 12R during the period of the timing device TR when its RG gate is open if the carry store has been set during the preceding period of the timing device TR. For example a carry pulse will be applied to the counting device 2R during the period T2 if the carry store has been set during the period T1. The only counting device which can receive pulses and hence the only counting device which can pass through zero during the period T1 is the counting device 1R. Hence the counting device 2R can receive a carry pulse only from the counting device IR and similarly each other counting device can only receive a carry pulse when the next lower counting device has passed through zero.

The components so far described are the majority of those necessary to enable the machine to perform addition and subtraction, but, when the machine is required to perform multiplication or division, it is necessary for the timing devices TR and TK to carry out a number of cycles and, to control the number of cycles of operation, a control counter CC is provided. The control counter CC has eleven outputs which are illustrated as C1 to C11. For the purposes of performing multiplication a bank of multiplier keys MK is provided and each of the multiplier keys 2 to 9 is associated with a respective one of the outputs C3 to C10 of the control counter CC. Each of these multiplier keys when operated connects the corresponding output of the control counter CC to the multiplier key bank output terminal MR. When the number 1 multiplier key is operated or when none of the multiplier keys are operated, the output T0 of the register timer is connected to the terminal MR. Normally the output Y shown connected to the O multiplier key is at a positive potential, but, when the O multiplier key is operated, the potential of the terminal Y is made negative.

The pulse generator PG includes a ten-cathode counter tube driven by a 4 kc./s. blocking oscillator the anode of which is connected to a terminal oscillator. Normally, when the machine is switched on, the pulse generator PG is running continuously. However the pulse generator can be stopped when a control signal is applied thereto from the output of a stop gate SGl or of a stop gate 562. Each of these gates is in the form of an AND logical element and it will be seen that the inputs to the stop gate 861 are constituted by the terminals T0, I11 and a terminal ST3 which will be described hereinafter. The inputs to the stop gate SGZ are constituted by a terminal M, the terminal MR and the terminal ST3. Thus assuming that the terminals M and ST3 are energised the pulse generator will be stopped when a positive potential is applied to the terminal MR. As previously pointed out the terminal MR is connected to a selected one of the outputs of the control counter CC by the operation of a multiplier key. Accordingly the pulse generator is stopped when the timing device TR has performed a number of cycles corresponding to the operated key in the bank of multiplier keys.

The control counter CC may be a ring counter similar to the devices TR and TK. It is stepped forward by means of input pulses received through an OR gate CGl. The two inputs of the OR gate CG1 are constituted by the outputs of two AND gates CG2 and CG3. It will be seen that the inputs of the AND gate CGZ are constituted by the terminals T12 and M and that the inputs of the AND gate CG3 are constituted by the terminals CGO, T0, DG and ST3. During multiplication the terminal M is energised and accordingly the control counter will be stepped forward once each time the timing device TR passes through T12.

It has already been pointed out that any order of keys can be associated with any one of the counting devices since the timing devices TR and TK need not move in step. However inaccuracies would be introduced into any calculation in which an order of keys was associated with a counting device of higher order than that order of keys. Accordingly to prevent such association a bi-stable device BA is provided. This bi-stable device has two outputs A and K. Normally the output A is positive and the other output is negative. However the bi-stable device may be set by means of an output from the timing device TK which is arranged to occur at the end of the period t11. When the device is set, the output A is energised and the output A becomes negative. The device is reset by means of an input from the timing device TR which is arranged to occur at the end of the period T0. It will be seen that the terminal A constitutes one of the inputs of the gate KGI so that no key can affect the output of the twostate device KC after the end of the period :11. Accord ingly no pulses can be entered from the keys under normal conditions after the period t11.

When the machine is used for division, a further bistable device BC is required. This device is operative, when the machine is being used for division, to determine whether the divisor is added to or substracted from the dividend and it is provided with two outputs one of which is designated C+ and the other C-. In the unset state the output C- is positive, and in the set state the output C+ is positive. The device is set each time the control counter CC is stepped and is unset by the back edge of the next T pulse from the output of the gate TG3.

The machine being described is suitable for performing addition, subtraction, multiplication and division. The various functions which can be performed are selected by means of changeover switches. These switches are not shown in the drawing, but they operate to apply positive potentials to the terminals indicated in the following Table 1:

TABLE 1 Addition M Subtraction M S Multiplication M Division D When the machine is in thet waiting condition, the pulse generator PG is running and produces its normal ten pulses during each cycle of operation. However, these pulses are ineffective at this time because the timing device TR is maintained at T0 and accordingly none of the gate circuits 1RG to 12RG is open. The timing device TR is maintained on T0 by a negative potential applied to it through a start contact ST2. Negative potentials are also supplied by a start contact ST1 which serves to maintain the control counter CC on C1 and a third start contact ST3 which serves to close the gates SGl, SG2, CG3, TGS and TG6.

When the machine is first turned on and has warmed up, it is in a stand-by condition wherein each counting device in the register indicates zero. After a figure has been entered into the register, the machine waits in a second stand-by condition wherein that figure remains in the register. It is therefore possible that the machine may be required to stand-by for long periods in which any one of the tubes associated with a particular digit in each counting device in the register is conductive.

The timing device TR has an output T0 which, when the machine is in the stand-by condition, is held positive and since this device is a ring counter, which returns to a zero or ready condition, a cold-cathode trigger tube corresponding with output T0 will always be conductive during any stand-by period. Although, in the stand-by condition, the pulse generator PG is normally running and the dP9 pulses are applied to the input of the timing device TR, this timing device will not he stepped forward until an enabling signal is received on terminal STZ from a start switch which is closed as a result of the depression of a key.

From the foregoing, it is clear that all the register circuits 1R to 12R and the circuit of the timing device TR suffer from long stand-by periods as each includes a cold-cathode tube which is conductive during stand-by.

In accordance with the invention, therefore, there is provided a circuit T0 containing a cold-cathode tube connected to the T0 stage of timing device TR and forming a bi-stable circuit therewith, the switching being controlled by the dP9 pulses. When the output of T0 remains positive for a period substantially longer than it would do if the machine were in use, T0 is set in readiness to be fired by the next dP9 pulse applied thereto, and, when fired, causes the tube in T0 to be extinguished. However, the next dP9 pulse applied to T0 will again fire its tube and cause the tube in T0 to be extinguished until the aforementioned period has again elapsed. A delay gate DG prevents the circuit T0 from being affected by T0 until the oscillator which drives the pulse generator PG has settled down to its correct frequency after it has been set running; input OSC from the oscillator being provided for this purpose. The output of T0 is energised so long as the tube in T0 conducts and this ouput is amplified by an amplifier AMP from which a positive-going output is applied to all output terminals T1 to T12 of TR, a positive-going output RP is obtained, and a negative-going output TX is also obtained.

Thus, one of the benefits sought has been obtained since the tube in section T0 of timing device TR no longer remains continuously conductive during stand-by. Therefore, the useful life of the timing device TR as a whole substantially increased.

When, by the conduction of the tube in circuit T0, outputs T1 to T12 of timing device TR are swung positive, the register gates 1RG to 12RG are simultaneously opened to pass all the pulses that appear on the common line H. Since the machine is under stand-by conditons there will be no normal pulses on line H, but, according to the principles of this invention, recirculation pulses are applied to this line through the AND gate G11. Gate G11 is shown with two inputs; an input GD which receives the pulses from the oscillator which drives the pulse generator PG, 'and an input RP which is received from amplifier AMP. The input GD is a negativegoing waveform which is derived from the output OSC of the pulse generator PG and is provided primarily for pulse-shaping and to assist in the closing of the gates G1 to G9 at the end of each pulse as explained in application No. 164,645 filed Dec. 29, 1961, now -U.S. Patent No. 3,280,315. However, this waveform is shown as being applied to the gate G11 since the negative excursions of this waveform are sufficient to prevent any positive output from the gate G10 from reaching the H line and, in effect therefore, the positive pulse of RP will be chopped by the waveform GD in the "AND" gate G11 into exactly ten pulses which pass to the OR gate G10 and onto the H line..Since all the gates lRG to 12RG are open, the ten pulses are applied simultaneously to each counting device in the register and during stand-by each counting device is periodically driven through a full cycle of operation at a re-cycling frequency which is determined by the bistable device formed by the valves T0 and T0. If, as supposed, the oscillator runs at a frequency 4 kc./s., each burst of ten pulses will have a duration of approximately 2.5 milliseconds but the mark-space ratio of the bi-stable device formed by T0 and T0 is such that the re-cycling period is between 15 and milliseconds. The proportioning of the mark-space ratio in this way provides the dual advantage of reducing the probability of a delay occurring between the receipt of an input signal and the stepping of timing device TR, and reducing the background glow due to the conduction of the pulses circulated through the register. On the other hand, the period between recirculation pulse bursts cannot be extended indefinitely since the advantages of recirculation are to some extent proportionate to the re-cycling frequency.

If the machine described in Patent No. 3,296,425 is modified in accordance with the present invention, certain additional precautions must be taken to avoid the danger of unintended operation. For example, if all the counting devices 1R to 12R are initially at zero, an output is produced on line C by each counting device simultaneously when the tenth pulse is received and, therefore, the voltage pulse on line C is much larger than normal and could cause malfunction of the carry store CS. Therefore, a limiting stage L is interposed in the C input to CS. However, if an economical limiter such as a Zener diode is employed the pulse is broadened thereby and there is a danger that it would overlap the resetting P0 pulse and the carry store CS would fail to reset, with the result that a spurious P0 pulse would be fed into the gate G9 and finally into the units stage of the register if the machine started a calculation immediately. To suppress a spurious pulse of this nature, the TX output waveform of the amplifier AMP is applied to gate G9 in such a way as to block this gate. When the machine is performing a calculation, there will be no amplifier output and TX will be positive so that normal carry pulses will be transmitted through G9 to the OR gate G10. On the other hand, during recirculation and stand-by, all carry pulses from CS will be blocked by G9 since TX will then be negative. This terminal is arranged to become slowly positive at the end of T0 and the rise is slow enough to prevent the application of a P0 carry pulse during the period T1 immediately after recirculation.

Further, it is possible that the raising of the potential of output T12 of timing device TR by means of the amplifier AMP output during recirculation could cause incorrect operation of gate CG2 and the undesired stepping of control counter CC. Such erroneous operation of gate CG2 can be prevented by adding another input to this gate, which is derived from the start contacts ST3. Since the 8T3 input will not be present during stand-by conditions, gate CG2 is positively blocked against operation by input T12. If desired, additional protection may be obtained by adding a P9 signal to gate G12 by which the gate is blocked at all times except when a P9 pulse is received.

It is possible that a machine such as that described and illustrated in Patent No. 3,296,425 could be left in the jammed condition (that is with both T0 and :11 positive) and as a result, the P9 pulses would be suppressed by the AND-NO gate TG1 which drives the timing device TR and, as a result the P9 drive to T0 would be removed and recirculation could not take place. Therefore, the AND-NOT gate TG1 is removed with the AND gate TGZ and the P9 pulses are fed directly to device TR and to the auxiliary circuit T0. In order to prevent the machine from operation in the jammed condition a simple modification is made to the stop gate SG1 by changing its input 8T3 to the input ST2 and ensuring that it will act promptly if signals on T0, 211 and ST2 are all present. Thus, if the operator attempts to start a calculation, this stop gate immediately operates and the oscillator is stopped. On the other hand, if an attempt to start a jammed machine is made while a burst of recirculation pulses is being fed to the respective registers, no signal will be present on input T0 of SG1 and the recirculation cycle will finish before the oscillator is stopped so that registers cannot be prevented from completing the recirculation cycle.

FIGURE 2 is a partial circuit diagram of the timing device 'DR together with its additional circuit elements and illustrates one way in which the desired output can be generated while the current flow in the tube VTO of the T0 stage of timing device TR is interrupted. During stand-by, VTO is initially conductive since resistors R1 and R2 set its trigger bias so that the first dP9 pulse passed by coupling capacitor C1 fires the valve, the dP9 pulse being coupled into the normal reset or feed back line RS. The firing of valve VTO raises its cathode potential and blocks a diode D1 which is connected between its cathode and the trigger of a valve VTO' via a resistor R3.

If the oscillator has just been started, the delay gate DG will take effect in the following manner. The oscillator output of the pulse generator PG is fed on the input OSC through coupling capacitor C2 and is rectified by diodes D2 and D3 in such a way that the potential across a capacitor C3 is pumped up to a value sufficient to reverse bias a diode D4 which connects the delay gate DG to the trigger resistor R3 of valve VTO. One side of capacitor C3 is held at -20 volts and, should the oscillator input be removed for some reason, this capacitor will discharge through a parallel resistor R4. The trigger of valve VTO is raised to near the firing potential by means of capacitor C4 which charges through resistor R5 from the vo'lt line but, if either diode D1 or D4 is unblocked, a relatively large current flows through R5 to lower the trigger potential of VTO and prevent it from being fired by a dP9 pulse applied through diode D5 and coupling capacitor C5. Therefore, the firing of valve VTO' by a dP9 pulse applied to its trigger is delayed by the delay gate DG until diode D4 is blocked, the delay period being arranged so that the oscillator has sufiicient time to settle down to a constant frequency. It will be noted that the voltage developed across capacitor C4 and the dP9 input pulse to circuit T0 are both referenced to the -20 volt line, resistor R6 being provided between the cathode of diode D5 and the 2() volt line for this purpose.

Thus, as soon as the oscillator has settled down to a constant frequency and the valve VTO has been fired by a dP9 input pulse through capacitor C1, the diodes D1 and D4 are reverse biased and capacitor C4 is permitted to charge through resistor R5 in circuit T0. Depending upon the time constant of R5 and C4, one of the a'P9 pulses applied to the trigger of VTO through C5 will soon be enabled to fire this valve and thereby cause the extinguishing of valve VTO. However, as soon as valve VTO fires, its cathode potential is raised and current is permitted to flow through diode D6, resistors R7, R2, R1 and R8 to the -l25 volt line and thereby raise the trigger potential of VTO to near the firing level so that 1 1 the next dP9 pulse applied through capacitor C1 will fire VTO and the cycle will be repeated.

A positive-going output pulse is coupled from the cathode of VTO and applied to the amplifier circuit AMP, the delay circuit R9, C6 being provided to ensure that VTO' will be extinguished when the valve VTO becomes conductive. The amplifier AMP consists of three NPN transistors TR1, TR2 and TR3, connected as a three-stage amplifier with the emitter of each connected to the +20 volt line. The base bias of transistor TR1 is set by bias resistor R10 connected to the +130 volt line, the bias of transistors TR2 and TR3 being set by the otentiometers formed by resistors R11, R12 and R13, R14 (respectively) also connected to the l30 volt line. The collectors of TR1 and TR3 are respectively connected by resistors R15 and R16 to the +15 volt line, while the collector of transistor TR2 is connected through R17 to a +180 volt line. Therefore, a positive-going pulse applied to the base of TR1 will produce an amplified voltage pulse over R15 and this pulse will be applied to the base of TR2 through R11 to produce a further amplification over resistor R17. The pulses thus amplified by the first two stages are coupled directly to the output line RP and to the terminals T1 to T12 through respective resistors R21, R22 R32.

The output TX is obtained after the third stage of amplification by coupling the voltage drop over R17 through a diode D7 and resistor R13 to gain a further amplified pulse from resistor R16. It will be noted that the collector of transistor TR3 is shunted to the emitter of this transistor by capacitor C7 and a corresponding broadening and delaying of the output TX therefore results and the output pulse thus obtained overlaps the P pulse for the purpose previously described. Thus, the third stage of amplification through transistor TR3 effectively isolates the output pulse TX from the output on the line RP. It will be noted that the transistors TR1 and TR3 are protected against potentially damaging reverse current pulses applied to the base by means of diodes D8 and D9 which are reverse biased for a positive input. Since the output TX is negative when the tube VTO is conductive and is positive at other times, it is possible for this signal to be applied to the gate TG4 as the input T1-T12, provided means are included to make TX negative during T0. For this purpose the T0 pulse is fed to the junction of R13 and D7 through a diode D12, the diodes D7 and D12 thus combining to form an OR circuit. A diode D13 is placed between R13 and the +15 volt line to limit the potential of the junction of D7 and R13.

From the above description of the operation of valves VTO and VTO, it will be seen that the output RP of amplifier AMP consists of a positive-going pulse which commences at the end of one P9 pulse and ceases at the end of the next, the time interval between the pulses be- I ing determined by the time constant of R and C4 in the trigger circuit of valve VTO'. Further it will be seen that all the terminals T1 to T12 are made positive for the duration of the positive-going pulse on the terminal RP. The desired stand-by conditions have thus been obtained and the register circuits 1R to 12R, as well as the timing device TR, have been benefited accordingly.

However, it is important that the normal operation of timing device TR and the registers should not be impaired by the use of the recirculation during stand-by. As soon as one of the keys is depressed for the entry of a set of figures, a gradually rising positive potential is applied to terminal ST2 on the timing device TR and, via a diode D10, is applied to, but not transmitted by, the capacitor C5. The diodes D5 and D therefore combine in a gating action which results in the swamping of dP9 pulses to capacitor C5. The voltage levels are adjusted so that very shortly after the application of the input ST2 no dP9 pulse applied to D5 can be effective in the firing of valve VTO. Thus, very shortly after the application of ST2,

12 if not at the time of application, valve VTO will be conductive and there will be no danger of the valve VTO' again conducting until all figures have been entered in the register. The delay circuit formed by R19 and C8 ensures that VTO is extinguished when VT1 becomes conductive.

However, the input ST2 *has an effect upon the trigger potential of valve VT1 since it is coupled to the trigger through resistor R20 but its effect is delayed because it is a waveform which rises slowly.

Therefore, if the positive signal of ST2 is applied when valve VTO is conductive, the passage of dP9 pulses to the trigger electrode of VTO will be quickly blocked and, shortly after the blocking of the drive to VTO, ST2 will have raised the trigger potential of VT1 sufficiently to allow the next dP9 pulse on the common input line to fire VT1 through capacitor C9. It is therefore impossible that valve VTO and VT1 could both fire simultaneously after the application of the ST2 signal and at the next dP9 pulse.

After VT1 has been fired, the stepping of the timing device TR is accomplished in the normal manner and as described in the aforementioned Patent No. 2,296,425.

From the above-described particular embodiment, it will be seen that an electronic calculating machine may be modified with little difficulty to produce pulse recirculation during stand-by in at least one timing device and in each of the registers. As previously explained, the recirculating pulses not only substantially improve the life and reliability of the registers employed in the calculating machine, but also enhance the life and reliability of the timing device in which they are generated.

What we claim as our invention and desire to secure by Letters Patent of the United States is:

1. A calculating machine including a timing device and a register, wherein the timing device includes a first stage which is associated with a stand-by condition of the machine, a plurality of second stages which are rendered operative in succession during the performance of a calc lation, a third stage coupled to said first stage, and means for rendering said first and third stages operative alternately when the machine is in the stand-by condition, and wherein said register includes a series of electric pulseoperated counting devices each having a plurality of stages, and means controlled by said third stage of said timing device and operative, when said third stage i operative, to supply bursts of pulses to said counting devices, the number of pulses in each burst being equal to the number of stages in each counting device.

2. A calculating machine as claimed in claim 1, in which each stage of said timing device and each stage of said register comprise a cold-cathode trigger tube.

3. A calculating machine including a register, a pulse generator, a keyboard for controlling the entry of pulses from said pulse generator into said register, a timing device comprising a first stage, a plurality of second stages, and a third stage, means coupling the first and second stages of the timing device to form a ring counter, means coupling the first and third stages of the timing device to form a bi-stable trigger circuit, means for applying one stepping pulse from said pulse generator to said timing device during each cycle of operation of the pulse generator, means controlled by said keyboard for preventing said stepping pulse from initiating stepping of the ring counter until a key in said keyboard has been actuated, and means for preventing the setting of said bi-stable trigger circuit after a key in said keyboard has been actuated.

4. A calculating machine including a plurality of pulseoperated counting devices, a plurality of gate circuits, one associated with each counting device, an electrical timing device operative to open the gate circuits in sequence for predetermined periods and having first and second stand-by conditions, an electrical pulse generator adapted to produce, during each of said periods a number of pulses equal to the total capacity of each of said 13 14 counting devices, a pulse entry line connected to an input References Cited of each of said gate circuits, means for deriving from the output of said pulse generator and supplying to said pulse UNITED STATES PATENTS entry line a waveform such that the potential of sai 2,864,034 12/1958 Adams 315--84.6 pulse entry line is periodically reduced at a rate equal to 5 2 944 189 7/1960 Cannon the pulse repetition rate of said pulse generator, means "T for periodically transferring the electrical timing device 3O56548 10/1962 De Llsle Nlcho'ls 315 84"6 X from the first stand-by condition to the second stand-by 3,171,059 2/1965 Falconer 315-845 condition, and means for applying an input to said pulse MAYNARD WILBUR, primary Examiner entry line and for opening all said gate circuits when the 10 timing device 1s in said second stand-by condition. MAIER, 145515111"! Exammer-

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