GB9119025D0 - Method of connecting upper and lower interconnections - Google Patents
Method of connecting upper and lower interconnectionsInfo
- Publication number
- GB9119025D0 GB9119025D0 GB919119025A GB9119025A GB9119025D0 GB 9119025 D0 GB9119025 D0 GB 9119025D0 GB 919119025 A GB919119025 A GB 919119025A GB 9119025 A GB9119025 A GB 9119025A GB 9119025 D0 GB9119025 D0 GB 9119025D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- connecting upper
- lower interconnections
- interconnections
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2244511A JPH04123458A (en) | 1990-09-14 | 1990-09-14 | Manufacture of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
GB9119025D0 true GB9119025D0 (en) | 1991-10-23 |
GB2247987A GB2247987A (en) | 1992-03-18 |
Family
ID=17119771
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB9119025A Withdrawn GB2247987A (en) | 1990-09-14 | 1991-09-05 | Metallic interconnections for semiconductor devices |
Country Status (3)
Country | Link |
---|---|
JP (1) | JPH04123458A (en) |
DE (1) | DE4130535A1 (en) |
GB (1) | GB2247987A (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR950006343B1 (en) * | 1992-05-16 | 1995-06-14 | 금성일렉트론주식회사 | Fabricating method of semiconductor device |
JPH0697288A (en) * | 1992-09-09 | 1994-04-08 | Kawasaki Steel Corp | Manufacture of semiconductor device |
KR0140646B1 (en) * | 1994-01-12 | 1998-07-15 | 문정환 | Mancefacture of semicouductor device |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4892845A (en) * | 1984-08-31 | 1990-01-09 | Texas Instruments Incorporated | Method for forming contacts through a thick oxide layer on a semiconductive device |
JPS61258453A (en) * | 1985-05-13 | 1986-11-15 | Toshiba Corp | Manufacture of semiconductor device |
US4824521A (en) * | 1987-04-01 | 1989-04-25 | Fairchild Semiconductor Corporation | Planarization of metal pillars on uneven substrates |
EP0317770A1 (en) * | 1987-11-23 | 1989-05-31 | Texas Instruments Incorporated | Self aligned planar metal interconnection for a VLSI device |
JPH10116834A (en) * | 1996-10-11 | 1998-05-06 | Toshiba Corp | Method of manufacturing semiconductor device |
-
1990
- 1990-09-14 JP JP2244511A patent/JPH04123458A/en active Pending
-
1991
- 1991-09-05 GB GB9119025A patent/GB2247987A/en not_active Withdrawn
- 1991-09-13 DE DE4130535A patent/DE4130535A1/en not_active Ceased
Also Published As
Publication number | Publication date |
---|---|
GB2247987A (en) | 1992-03-18 |
JPH04123458A (en) | 1992-04-23 |
DE4130535A1 (en) | 1992-03-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |