GB908555A - Improvements in and relating to binary counters - Google Patents

Abstract

908,555. Electric selective signalling systems. INTERNATIONAL BUSINESS MACHINES CORPORATION. May 19, 1961, No. 18285/61. Class 40 (1). [Also in Group XIX] The storage register of a binary counter is so controlled by logic circuits that in response to stepping pulses it stores odd numbers in true form and even numbers in complement form except for the lowest stage. The register controls further logic circuits so that read-out is always effected in true form. The register comprises flip-flops 10-18 and a lowest stage 44. A clear pulse sets all the flipflops to 1 except the lowest which is set to 0. In counting pulses on line 50, according to whether stage 44 is at 1 or 0 so gate 46 or 48 opens. With stage 44 at 1, a stepping pulse reverses 44 and samples gates 26-34. Any of these gates which is open because the corresponding stage is at 0 sends a pulse to all the OR gates 36-42 of higher denomination to effect complementing. If stage 44 is at 0, all the OR gates 36-42 are effective to effect complementing at the same time as 44 changes to 1. Read-out. The 1 and 0 outputs of the register flip-flops feed gates 56-64 and 66-74 respectively. One or other set is opened by gate 88 or 90, at read-out, according to whether flip-flop 44 of the lowest denomination registers 1 or 0. The read-out on leads 2<SP>5</SP>-2<SP>0</SP> is therefore in true form.