GB881651A - A circuit arrangement for producing an output which is delayed with respect to its input - Google Patents
A circuit arrangement for producing an output which is delayed with respect to its inputInfo
- Publication number
- GB881651A GB881651A GB778257A GB778257A GB881651A GB 881651 A GB881651 A GB 881651A GB 778257 A GB778257 A GB 778257A GB 778257 A GB778257 A GB 778257A GB 881651 A GB881651 A GB 881651A
- Authority
- GB
- United Kingdom
- Prior art keywords
- inductor
- rectifier
- potential
- circuit
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/145—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of resonant circuits
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Dc-Dc Converters (AREA)
Abstract
881,651. Pulse delaying circuits. ASSOCIATED ELECTRICAL INDUSTRIES Ltd. March 7, 1958. [March 8, 1957], No. 7782/57. Class 40(6). In a circuit for producing an output pulse Fig. 2 (e) after an initial pulse (a) an inductor I is connected in series with a rectifier 2 and capacitor 3. When the switch 5 is closed current flows, Fig. 2 (c) the potential across the capacitor rising to twice the value of the source potential V (b), while the potential across the inductor 1 rises according to curve (d). The circuit 1, 3 tends to oscillate but after a time t when the current would reverse, the rectifier 2 is effective to stop oscillation of the main circuit. During the charging process, the stray capacitance existing across the inductor 1 is also charged to the potential existing across the inductor and high frequency oscillations occur when the rectifier effectively disconnects the inductor from the remainder of the circuit. The potential occurring across the rectifier (e) provides the output signal. Alternatively, the capacitor 3 may be charged and subsequently discharged through inductor 1 by the switch 6. The output across the rectifier 2 may control a transistor or valve.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB778257A GB881651A (en) | 1957-03-08 | 1957-03-08 | A circuit arrangement for producing an output which is delayed with respect to its input |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB778257A GB881651A (en) | 1957-03-08 | 1957-03-08 | A circuit arrangement for producing an output which is delayed with respect to its input |
Publications (1)
Publication Number | Publication Date |
---|---|
GB881651A true GB881651A (en) | 1961-11-08 |
Family
ID=9839608
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB778257A Expired GB881651A (en) | 1957-03-08 | 1957-03-08 | A circuit arrangement for producing an output which is delayed with respect to its input |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB881651A (en) |
-
1957
- 1957-03-08 GB GB778257A patent/GB881651A/en not_active Expired
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