GB8622807D0 - Semiconductor chip constructions - Google Patents

Semiconductor chip constructions

Info

Publication number
GB8622807D0
GB8622807D0 GB8622807A GB8622807A GB8622807D0 GB 8622807 D0 GB8622807 D0 GB 8622807D0 GB 8622807 A GB8622807 A GB 8622807A GB 8622807 A GB8622807 A GB 8622807A GB 8622807 D0 GB8622807 D0 GB 8622807D0
Authority
GB
United Kingdom
Prior art keywords
chips
semiconductor chip
electrical contacts
jacket
constructions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
GB8622807A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BAE Systems Global Combat Systems Munitions Ltd
Original Assignee
Royal Ordnance PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Royal Ordnance PLC filed Critical Royal Ordnance PLC
Priority to GB8622807A priority Critical patent/GB8622807D0/en
Publication of GB8622807D0 publication Critical patent/GB8622807D0/en
Priority to GB8722368A priority patent/GB2196475B/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Measurement Of Unknown Time Intervals (AREA)

Abstract

A package for use in the firing circuit of a detonation fuze includes a conducting substrate (8), two programmable timer chips (3,5) deposited on the said substrate, a series of electrical contacts (T1-16) connected to each of the said chips and an encapsulating jacket of insulating material formed around the chips in such a way that the said electrical contacts project through the jacket. <IMAGE>
GB8622807A 1986-09-23 1986-09-23 Semiconductor chip constructions Pending GB8622807D0 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB8622807A GB8622807D0 (en) 1986-09-23 1986-09-23 Semiconductor chip constructions
GB8722368A GB2196475B (en) 1986-09-23 1987-09-23 Semiconductor chip constructions

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB8622807A GB8622807D0 (en) 1986-09-23 1986-09-23 Semiconductor chip constructions

Publications (1)

Publication Number Publication Date
GB8622807D0 true GB8622807D0 (en) 1987-02-04

Family

ID=10604600

Family Applications (2)

Application Number Title Priority Date Filing Date
GB8622807A Pending GB8622807D0 (en) 1986-09-23 1986-09-23 Semiconductor chip constructions
GB8722368A Expired - Lifetime GB2196475B (en) 1986-09-23 1987-09-23 Semiconductor chip constructions

Family Applications After (1)

Application Number Title Priority Date Filing Date
GB8722368A Expired - Lifetime GB2196475B (en) 1986-09-23 1987-09-23 Semiconductor chip constructions

Country Status (1)

Country Link
GB (2) GB8622807D0 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5084753A (en) * 1989-01-23 1992-01-28 Analog Devices, Inc. Packaging for multiple chips on a single leadframe
US5340772A (en) * 1992-07-17 1994-08-23 Lsi Logic Corporation Method of increasing the layout efficiency of dies on a wafer and increasing the ratio of I/O area to active area per die
US5532934A (en) * 1992-07-17 1996-07-02 Lsi Logic Corporation Floorplanning technique using multi-partitioning based on a partition cost factor for non-square shaped partitions
US5561086A (en) * 1993-06-18 1996-10-01 Lsi Logic Corporation Techniques for mounting semiconductor dies in die-receiving areas having support structure having notches
US6509632B1 (en) 1998-01-30 2003-01-21 Micron Technology, Inc. Method of fabricating a redundant pinout configuration for signal enhancement in an IC package

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6018145B2 (en) * 1980-09-22 1985-05-09 株式会社日立製作所 Resin-encapsulated semiconductor device
US4680617A (en) * 1984-05-23 1987-07-14 Ross Milton I Encapsulated electronic circuit device, and method and apparatus for making same
JPS62109333A (en) * 1985-11-04 1987-05-20 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Semiconductor package

Also Published As

Publication number Publication date
GB2196475B (en) 1990-01-10
GB8722368D0 (en) 1987-10-28
GB2196475A (en) 1988-04-27

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