GB852205A - An electronic multiplying apparatus - Google Patents

Abstract

852,205. Digital electric calculating apparatus. BUCKUNGSMACHINENWERK KARLMARX-STADT VEB. June 21, 1957, No. 19596/57. Class 106 (1). In an electronic multiplying apparatus a multiplier counter controls the number of series of product pulses and initiates the beginning of multiplicand transfer, and one of a series of individual pulses alternating with the product pulses concludes the multiplication, the multiplying arrangement shown comprises electronic decimal counters Z0, Z15 and Z10- Z11 for a multiplicand digit, a multiplier digit and the product respectively, each counter comprising four Eccles-Jordan trigger circuits arranged to have a counting capacity of ten. Multiplication is performed by repeated addition of the multiplicand under control of pulses A and B supplied alternately on separate output lines 2S, 3S by a multivibrator M. A start pulse sets an Eccles-Jordan trigger circuit FFO to open gate GO to allow A-pulses to pass to control counter Z8, the first pulse also setting trigger FF3 to open gate G3. B-pulses pass through G3 to multiplier counter Z15 which therefore produces, at a differential time corresponding to the multiplier digit, a carry output to set FF1 and FF4 and open.gates G6, G1 respectively. The next pulse from G3 resets FF4; and after 10 A-pulses, a carry output from Z8 passes through G6 to set FF2 to open gate G2 and resets FF3 to open G4 instead of G3. When FF2 is set it passes an additional pulse to Z15 which is then stepped to its original value. The A-pulses are now applied to multiplicand counter Z0, trigger FF3 being again set to open G3, so that during the next cycle of Z8, a carry output from Z0 sets FF10 at a differential time corresponding to the multiplier digit to allow a corresponding number of B- pulses from G3 to pass through gate G10 to units product counter Z10, and 9 B-pulses are applied to Z15 to reduce the multiplier by "1." The multiplicand is similarly transferred to Z10 during subsequent cycles of Z8, until Z15 is reduced to " 0 " just before a carry output is obtained from Z8 when the following B-pulses, instead of passing through G3 and resetting FF4, will pass through gates G4, G1 to reset the circuits to their initial condition, FFO then transmitting an end-of-multiplication pulse RV. If the multiplier digit is 0, FF1, FF4 will not be actuated and the carry output after the first cycle of Z8 will therefore pass through G5 to reset FF0 and end the multiplication operation. Provision may be made for dealing with multi-digit multipliers Specification 777,964 is referred to.