GB852205A - An electronic multiplying apparatus - Google Patents
An electronic multiplying apparatusInfo
- Publication number
- GB852205A GB852205A GB1959657A GB1959657A GB852205A GB 852205 A GB852205 A GB 852205A GB 1959657 A GB1959657 A GB 1959657A GB 1959657 A GB1959657 A GB 1959657A GB 852205 A GB852205 A GB 852205A
- Authority
- GB
- United Kingdom
- Prior art keywords
- pulses
- multiplier
- counter
- multiplicand
- digit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/491—Computations with decimal numbers radix 12 or 20.
- G06F7/498—Computations with decimal numbers radix 12 or 20. using counter-type accumulators
- G06F7/4983—Multiplying; Dividing
- G06F7/4985—Multiplying; Dividing by successive additions or subtractions
Landscapes
- Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
Abstract
852,205. Digital electric calculating apparatus. BUCKUNGSMACHINENWERK KARLMARX-STADT VEB. June 21, 1957, No. 19596/57. Class 106 (1). In an electronic multiplying apparatus a multiplier counter controls the number of series of product pulses and initiates the beginning of multiplicand transfer, and one of a series of individual pulses alternating with the product pulses concludes the multiplication, the multiplying arrangement shown comprises electronic decimal counters Z0, Z15 and Z10- Z11 for a multiplicand digit, a multiplier digit and the product respectively, each counter comprising four Eccles-Jordan trigger circuits arranged to have a counting capacity of ten. Multiplication is performed by repeated addition of the multiplicand under control of pulses A and B supplied alternately on separate output lines 2S, 3S by a multivibrator M. A start pulse sets an Eccles-Jordan trigger circuit FFO to open gate GO to allow A-pulses to pass to control counter Z8, the first pulse also setting trigger FF3 to open gate G3. B-pulses pass through G3 to multiplier counter Z15 which therefore produces, at a differential time corresponding to the multiplier digit, a carry output to set FF1 and FF4 and open.gates G6, G1 respectively. The next pulse from G3 resets FF4; and after 10 A-pulses, a carry output from Z8 passes through G6 to set FF2 to open gate G2 and resets FF3 to open G4 instead of G3. When FF2 is set it passes an additional pulse to Z15 which is then stepped to its original value. The A-pulses are now applied to multiplicand counter Z0, trigger FF3 being again set to open G3, so that during the next cycle of Z8, a carry output from Z0 sets FF10 at a differential time corresponding to the multiplier digit to allow a corresponding number of B- pulses from G3 to pass through gate G10 to units product counter Z10, and 9 B-pulses are applied to Z15 to reduce the multiplier by "1." The multiplicand is similarly transferred to Z10 during subsequent cycles of Z8, until Z15 is reduced to " 0 " just before a carry output is obtained from Z8 when the following B-pulses, instead of passing through G3 and resetting FF4, will pass through gates G4, G1 to reset the circuits to their initial condition, FFO then transmitting an end-of-multiplication pulse RV. If the multiplier digit is 0, FF1, FF4 will not be actuated and the carry output after the first cycle of Z8 will therefore pass through G5 to reset FF0 and end the multiplication operation. Provision may be made for dealing with multi-digit multipliers Specification 777,964 is referred to.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1177371D FR1177371A (en) | 1957-06-21 | 1957-06-19 | Electronic control device for performing multiplications |
GB1959657A GB852205A (en) | 1957-06-21 | 1957-06-21 | An electronic multiplying apparatus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1959657A GB852205A (en) | 1957-06-21 | 1957-06-21 | An electronic multiplying apparatus |
Publications (1)
Publication Number | Publication Date |
---|---|
GB852205A true GB852205A (en) | 1960-10-26 |
Family
ID=10132012
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB1959657A Expired GB852205A (en) | 1957-06-21 | 1957-06-21 | An electronic multiplying apparatus |
Country Status (2)
Country | Link |
---|---|
FR (1) | FR1177371A (en) |
GB (1) | GB852205A (en) |
-
1957
- 1957-06-19 FR FR1177371D patent/FR1177371A/en not_active Expired
- 1957-06-21 GB GB1959657A patent/GB852205A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
FR1177371A (en) | 1959-04-23 |
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