GB836595A - Improvements in electrolytic treatment of semiconductor bodies - Google Patents

Improvements in electrolytic treatment of semiconductor bodies

Info

Publication number
GB836595A
GB836595A GB19081/56A GB1908156A GB836595A GB 836595 A GB836595 A GB 836595A GB 19081/56 A GB19081/56 A GB 19081/56A GB 1908156 A GB1908156 A GB 1908156A GB 836595 A GB836595 A GB 836595A
Authority
GB
United Kingdom
Prior art keywords
electrolyte
etching
plating
surface area
negative
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB19081/56A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Space Systems Loral LLC
Original Assignee
Philco Ford Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philco Ford Corp filed Critical Philco Ford Corp
Publication of GB836595A publication Critical patent/GB836595A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02Electroplating of selected surface areas
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25FPROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
    • C25F3/00Electrolytic etching or polishing
    • C25F3/02Etching
    • C25F3/14Etching locally

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)

Abstract

836,595. Electrolytic plating and etching of semi - conductors; semi - conductor devices. PHILCO CORPORATION. June 20, 1956 [July 13, 1955], No. 19081/56. Classes 37 and 41. A method of selectively electroplating a local surface area of a semi-conductive body comprises the steps of bathing said surface area with an electroplating electrolyte, forming within said body by means of a negative control voltage a localized region of potential negative with respect to said electrolyte and controllable in its extension towards said surface area in response to increases in said negative control voltage, and varying said voltage to bring about the selective electroplating of the said surface area. In a preferred form the body is first electrolytically etched and then plated by applying to a local surface area of the body an electrolyte which when positive with respect to the body produces plating and when negative thereto produces etching, raising the body to a positive potential and raising a localized region on said body opposite said area to a negative potential so as to create a depletion zone within said body, and varying said negative potential so that selective etching and plating are produced as desired due to the location of the depletion zone which determines which electrolytic action takes place. The negative control voltage may be adjusted so that etching of said surface area occurs until the depletion zone is exposed to the electrolyte whereupon etching is arrested and on increasing the negative control voltage plating occurs in the exposed depletion zone. The negative control voltage may be initially adjusted so that the depletion zone extends up to the said surface area so that when electrolyte is first applied to said area plating occurs. As shown, a wafer 10 of N-type germanium having an ohmic ring contact 11 and a surface barrier rectifying contact 22 which may be formed in the recess by the jet-etching and plating technique of Specification 824,484, is treated with a jet 13 of a plating electrolyte, e.g. an aqueous solution of indium trichloride brought to pH 1.25 with hydrochloric acid, while a voltage is applied between the wafer and the electrolyte through a positive electrode 19 and a negative control voltage is applied to the contact 22. By this means etching occurs until the boundary 26 of the depletion zone 25 is reached whereafter indium is deposited at 35 upon either increasing the negative voltage applied to the contact 22 and/or decreasing the electrolyte-wafer voltage. Instead of using a jet of electrolyte, the wafer may be immersed in an electrolytic bath, the recess, rectifying contact, and lead thereto being insulated as by wax. Reference is also made to the use of silicon as the semi-conductor, non-aqueous ionizing solvents for metal salts to provide the electrolyte, and to the production of surface barrier or alloy junction transistors. Specifications 810,946 and 826,916 also are referred to.
GB19081/56A 1955-07-13 1956-06-20 Improvements in electrolytic treatment of semiconductor bodies Expired GB836595A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US836595XA 1955-07-13 1955-07-13

Publications (1)

Publication Number Publication Date
GB836595A true GB836595A (en) 1960-06-09

Family

ID=22179846

Family Applications (1)

Application Number Title Priority Date Filing Date
GB19081/56A Expired GB836595A (en) 1955-07-13 1956-06-20 Improvements in electrolytic treatment of semiconductor bodies

Country Status (1)

Country Link
GB (1) GB836595A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3275539A (en) * 1962-11-09 1966-09-27 North American Phillips Compan Method of manufacturing semiconductor devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3275539A (en) * 1962-11-09 1966-09-27 North American Phillips Compan Method of manufacturing semiconductor devices

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