769,305. Electric selective signalling. ELECTRIC & MUSICAL INDUSTRIES, Ltd. July 26, 1954 [Aug. 6, 1953], No. 21688/53. Class 40 (1). An electric selective signalling or control apparatus is provided with means for selecting messages in dependance upon multi-element pulse code recognition signals at the beginning of the messages, said means including a store for a predetermined recognition signal, and comparison means for comparing the elements of the recognition signal of an applied message individually on reception of said elements with the corresponding elements of the predetermined recognition signal. The received message, Fig. 2(a), in which the recognition signal is at the left of the dotted line A, and has a first and last digit of value 1 and the remaining digits of any predetermined value is applied at 10, Fig. 1, to a " window " 11, accepting the range of signal amplitudes beween the limits 12a, 12b. The output from the " window " 11 is applied to a " beginning element " 13, e.g. a differentiating circuit, arranged to produce a voltage spike on the occurrence of the leading edge of a pulse, the output of which is connected to a gate 14, which produces an output pulse on the occur - rence of one input pulse. The figures enclosed in the " gate " symbols denote the threshold, i.e. the number of pulses to be applied to produce a single output pulse. At the beginning of a message a spike 15 is set up by the element 13 and transmitted via gate 14 to a trigger 16 which is triggered from state 0 to state 1 to open a pulse inhibiter gate 17 and allow clock pulses from a crystal oscillator to be applied to a series divider chain consisting of triggers 18 ... 22. The period of the clock pulses, Fig. 3b, is small compared with a digit interval, Fig. 3a, the division in the chain 18 ... 22 being shown in Figs. 3c to 3g. The outputs from the right sections of triggers 19, 20, 21 and the left section of trigger 22 are applied to a pulse gate 23, which also has an inhibit input connection, and a pulse is delivered from the gate 23 when the triggers 19, 20, 21 are simultaneously in state 0 and trigger 22 is in state 1, i.e. at the change 24 of curve 25, Fig. 3g. The sampling pulses 26, Figs. 2c and 3h, from the gate 23 are fed in parallel to gates 27 and 28, and to an " end element " 29, e.g. a differentiating circuit arranged to produce a voltage spike on the occurrence of the trailing edge of a pulse. The recognition signal is stored in a shifting register 29 ... 34, e.g. of the type described in Specification 738,739, [Group XL (c)], having input connections 35 ... 40 for loading the register. The first digit of the code is represented by the state of the trigger 29, the second digit by the state of the trigger 30, and so on, the output of the shifting register being connected to a coincidence circuit 41 which also receives an input from the window 11. If the circuit 41 shows identity between the first received digit and the first stored digit an output is provided from 41 which provides the second input to the gate 27, and a pulse appears in the output of the gate 27 during the sampling pulse 26, which is applied to the beginning element 43 to produce a spike 44, Fig. 3k. The spike 44 is applied in parallel to one input of a trigger 45 and to a pulse gate 46, the gate 46 operating the shift bus-bar 47 of the register 29 ... 33, so that the trigger 29 assumes the state representing the second digit of the code, the trigger 30 assumes the state representing the third digit and so on. A spike 51, Fig. 3j, from a beginning element 48 which receives its input from the left section of device 21 provides a second input to the trigger 45, which is set to state 1 at the time of the change 49, Fig. 3f, of trigger 21 from state 0 to state 1, and this in turn removes the inhibition from a pulse gate 52. The spike 44 fed to the trigger 45 when identity has been established between the first incoming digit and the stored digit re-sets the trigger 45 to state 0 and re-establishes inhibition on the gate 52. If identity 'is not established the spike 44 does not occur, the gate 52 remaining uninhibited, and the end element 29 provides a spike 53 at the end of the sample pulse 26 which is passed through gate 52 to a gate 54. The output from the gate 54 restores the trigger 16 to state 0, restores the recognition signal to the register 29 ... 34, and through are-setting connection 55 restores the divider chain 18 ... 22 to state 0 and the apparatus is ready for testing the code signals of subsequent messages. If identity is established the divider chain continues operating and on the occurrence of the 32nd clock pulse the divider reverts to its initial state and a further cycle commences, a second sampling pulse being generated and the second digit, as shown of value 1 being tested. The third digit is 0 and the coincidence circuit 41 again delivers an input to the gate 27 since the trigger 29 of the register is in state 0. When identity is finally established between the whole of the incoming recognition signal and that stored in the register the pulse produced from the gate 46 on testing the last digit by sampling pulse 57, Fig. 2c, produces state 0 in all the register devices 29 ... 34. A pulse gate 59 of threshold 6 is connected to each of the triggers 29 ... 34 so that six pulses are applied to the gate by the registers when they are switched to the state 0 to provide a pulse 60, Fig. 2d, which is applied to a gate 28 which also has an input from the window 11. The gate 28 is thereby conditioned for the transmission of the remaining part of the message via terminal 61, the digits being transmitted only during the sampling pulses from the gate 23, Fig. 2e. The gate 59 also delivers an output to an inhibit input connection 62 of gate 52 so that no further part of the incoming message is tested. At the end of the message a pulse applied to the terminal 63 resets the apparatus for the next signal. Transmitting. The apparatus is conditioned by first storing the recognition code in register 29 ... 34 and applying a pulse 64, having a duration at least equal to that of the message being transmitted, Fig. 4a, to terminal 65 to the inhibit input connection of gate 23 and to a pulse gate 66. The leading edge 67 of the pulse 64 produces a spike from a beginning element 68 which is transmitted by gate 14 to the trigger 16 to admit clock pulses to the divider chain 18 ... 22. The final trigger 22 is connected through a beginning element 69 to the pulse gate 66 so that at the end of each digit interval the gate 66 transmits a spike 70, Fig. 4b, via gate 46 to the shift bus-bar 47 of the register. The output of the register is taken via a gate 72 to the transmitter 73. Until the occurrence of the spike 70 the transmitter 73 receives a voltage from 29 representing the first digit and the process is repeated until the register is " empty ", and a positive pulse is delivered by the gate 59. This pulse is applied to a beginning element 75 to produce a spike 76, Fig. 4d, which operates a trigger device connected to 77 to initiate the transmission of the message proper which is applied at the terminal 78 and via the gate 72 to the transmitter 73. Modifications. An A.C. pulse code may be used in which the polarity of each digit is reversed midway through the digit interval, the sampling pulses occurring either during the first half or the second half of the digit interval. In this case, and in order to reduce the possibility of incorrect acceptance when identity is not established and the divider chain and register are re-set and re-start the testing cycle, due to the fact that part of the message proper may simulate a recognition signal, delay circuits, Fig. 6 (not shown) are connected to the device 13 so that after the first pulse the gate 14 is inhibited and testing cannot be re-started until the end of the message. In the case of A.C. pulse code, means are also described, Figs. 8 and 10 (not shown), for detecting and correcting a reversal of polarity of the incoming pulses before sampling takes place.