GB2538226A - Active noise filter - Google Patents

Abstract

An active noise filter circuit is designed to operate between the final intermediate frequency stage and the demodulator stage of a radio communication receiver. It removes noise and interference from an input signal. The filter includes a negative feedforward loop comprising a phase locked loop (PLL) 5,8,9,10. The filter also includes a first upconverter 1 with a highly stable source 4 at the intermediate frequency fi. A circuit element 6 (which the applicant refers to as a second upconverter) combines a time-delayed version of the input signal with the output of the first up-converter to provide a sum signal, at frequency 3fi, in which phase shifts due to transmitted data have been removed. This sum signal is provided as an input to the PLL. The PLL effectively extracts the phase noise component of the input signal and imposes the phase noise on its VCO 5. The VCO controls a down-converter 3 which receives the output of the first upconverter as an input and outputs a signal at the intermediate frequency fi with phase noise removed.

Description

Active Noise Filter * ..

* * * 000 * * * * * * * * * * * * * 0espe * * * * 0* * * * * * 40 In UK Patent GB 2248366 B an active noise filter was described for removing gaussian noise and interference from a radio signal without reducing or spreading its information bandwidth. Its use was applied specifically to FSK and PSK signals but not exclusively. It may also be used with other types of signals employing frequency shift or phase shift techniques.

An important feature of that invention was the use of a high-gain negative feedback loop to improve the signal-to-noise ratio at the output of the filter, by reducing the noise power in the system, as the signal power is usually limited for practical reasons.

A disadvantage of that technique was the fact that at high noise frequencies, the time delay around the loop will make it difficult to reduce the output noise power substantially. The problem is overcome in this filter design by using a negative feedforward loop and suitable time delay networks to balance out any delay effects in the filter.

According to the present invention an active noise filter circuit comprises a frequency upconverter means together with a highly stable frequency source means for providing a precise offset frequency f4 to the upconverter, a second frequency upconverter means for providing a sum signal output at frequency 3f; which is the sum of the input and output signals of the first upconverter, a phase-locked loop means for extracting a phase control noise voltage, an output frequency downconverter with a voltage controlled oscillator means for imposing frequency or phase changes on the output signal via a known centre frequency 3fi and a negative feedforward loop is used for extracting the output signal with a minimum amount of noise.

Figure 1 is a block schematic of the active noise filter for a binary PSK signal.

Description

The active noise filter shown in Figure 1 is designed to o*erate between the final intermediate frequency stage And the demodulation stage of a radio communication receiver. The input signal frequency to the filter circuit is f; (together with a phase shift for for a binary PSK signal, f1 is the intermediate frequency and cips=oorTt is the phase shift due to the input digital data.

An offset frequency fi is imposed on the input signal at the upconverter 1 by means of a highly stable frequency source 4 at frequency f; and with a stability of about 1 part ** in 10 or more. In order to remove the phase shift g's, a * portion of the input signal(via a small time delay td) and * a portion of the output signal from the upconverter 1, are * both fed into the upconverter 6. The output from the on. upconverter 6 is the sum signal at a frequency 3f1 which contains only random noise because it is free of any phase shift cps due to the digital data. For instance, when gos. 0, * the total phase shift in the sum signal is (0 + 0) = 0 and 1 when the phae shift ops= 7T the total phase shift in the %.0,*° sum signal iss (7T +it) = 211 = O. 0 0 * The output from the upconverter 6 is fed into a phase-locked loop comprising a limiter 7, multiplier 8, low-pass filter 9, amplifier 10 and VCO 5. An output from the upconverter 1 at a frequency 2-fl (together with a phase shift cps) is also fed via a timb delay Td into limiter 2 and then into downconverter 3, together with an output from VCO 5 at a frequency 3fi. The phase-locked loop when properly adjusted extracts the phase noise component of the random noise or interference present in the input signal. This phase noise which is imposed on VCO 5 is subtracted at the downconverter 3 and virtually yields an output signal at frequency1 with a phase shiftcps due to the digital data only. 0 * * * **

For the optimum performance of the filter, the small time delay td should be adjusted(by trial and error) to ensure complete removal of the phase shiftcps at the output of the upconverter 6. Similarly, the time delay Td is adjusted (by trial and error) until the output noise power from the downconverter 3 is reduced to a minimum. This occurs when the total time delay in the upper arm equals the total time delay in the feedforward arm precisely. Furthermore, by means of the high-gain amplifier 10, the voltage feedforward loop gain K1 is adjusted until the output noise power is minimised and the output signal-to-noise ratio is * thereby maximised. If any further improvement is required, a * * "4-a second stage filter can also be used. * *

The active noise filter can therefore be regarded as a minimum mean squared error filter between the input and output signals. Moreover, the overall improvement is achieved without reducing or spreading the information * bandwidth of the digital signal employed. * OO

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