GB2532215A

GB2532215A - Gate boost

Info

Publication number: GB2532215A
Application number: GB1420038.0A
Authority: GB
Inventors: John Leedham Robert; Snook Mark; Lyle Robin
Original assignee: Maschinenfabrik Reinhausen GmbH; Maschinenfabrik Reinhausen Gebrueder Scheubeck GmbH and Co KG
Current assignee: Maschinenfabrik Reinhausen GmbH
Priority date: 2014-11-11
Filing date: 2014-11-11
Publication date: 2016-05-18
Also published as: GB201420038D0

Abstract

The conduction losses in an IGBT U2 may be reduced by using a boosted gate voltage, but the short-circuit withstand time of the IGBT is undefined at such high gate voltages. The gate voltage is therefore quickly reduced to an unboosted level when a short-circuit circuit is detected, and the IGBT is then safely switched off at a time when the collector current has stabilised, for example after a predetermined delay. A short circuit may be detected by monitoring the collector voltage or by sensing the voltage across the emitter lead inductance Le, which voltage is proportional to di/dt. The technique may be applied also to MOSFETs and JFETs.

Description

GATE BOOST

FIELD OF THE INVENTION

This invention generally relates to power switch drivers for driving a control terminal of a power switch to drive a load, power converter comprising such a power switch driver, and methods for controlling a drive signal to a control terminal of a power switch to drive a load.

BACKGROUND TO THE INVENTION

Power converters, such as AC to DC converters or DC to AC inverters, generally comprise networks of parallel and/or series connected power switching devices such as insulated gate bipolar transistors (IGBTs). Such converters may be for applications ranging from low voltage chips, to computers, locomotives and high voltage transmission lines. Converters may be used for example for switching in high voltage dc transmission lines of the type which may, for example, carry power from an offshore wind installation, and for medium voltage (for example greater than 1KV) switching for motors and the like, for example locomotive motors.

The following description generally relates to driving one or more power switch(es), which in turn are configured for driving a load of a power converter. As the power switch(es), IGBTs are used for example to control large currents by the application of low level voltages or currents, some IGBTs having ratings of, e.g., 1200V or 1700V, and/or 1200A. However, principles and embodiments described herein are generally applicable where the power switch(es) are instead a MOSFET such as a silicon carbide MOSFET (vertical or lateral), HEMT, JFET or other type. Thus, any mention of IGBT or power switch can generally be replaced with reference to any such device. Furthermore, the techniques we will describe are not limited to any particular type of device architecture and thus the power switching devices may be, for example, either vertical or lateral devices; they may be fabricated in a range of technologies including, but not limited to, silicon, silicon carbide or gallium nitride.

Nevertheless, the power semiconductor switching devices with which we are concerned typically have a current carrying capability of greater than 1 amp and are operable with a voltage of greater than 100 volts, for example devices that are able to carry currents of greater than 10 amps, 50 amps or 100 amps and/or are able to sustain a voltage difference across the device of greater than 500 volts or 1KV.

A typical IGBT gate drive comprises the elements shown in Fig. 1. The gate drive logic comprises digital logic circuits reference to a 3V3 or 5V power supply which receives an incoming signal (PWM) indicating when to switch the power switch (e.g., IGBT) ON and OFF. The gate drive logic creates signals (SOURCE and SINK) indicating when current is to be supplied to and removed from the power switch respectively. A level translation stage is typically required to drive the power switch over a wider voltage range, e.g., -10y to +15V. The output stage for driving an IGBT comprises transistors P and N channel MOSFETS (labelled PMOS and NMOS) or bipolar PNP and NPN transistors with a turn-ON resistor (Ron) and a turn-OFF resistor (Roff) which are chosen to match the characteristics of the power switch and/or load. The output stage transistors can handle high current and normally require a drive stage as the digital logic and level translation cannot provide enough current to turn them on and off directly.

An IGBT may be provided in a module preferably including the IGBT device and a commutation diode, i.e., free-wheeling diode, in anti-parallel. IGBT module manufacturers generally publish preferred gate resistance values for minimal losses. In the case of IGBT turn-on there is a trade-off between IGBT switching loss and diode reverse recovery loss. It is generally desired that any attempts to reduce the overall losses ensure that the diode stays within its safe operating area (SOA), which may be represented on a graph of voltage against current by a line of maximum power dissipation which is preferably not crossed. The diode may be damaged if the switching speed of the converter output circuit is too fast, for example. IGBT manufacturers generally optimise their products for minimal overall losses assuming a voltage source drive with resistance (resistive drive). For this reason it is desirable that any drive circuit (driver) is a resistive drive preferably with output (gate drive) resistance within an IGBT manufacturer's specified range.

To reduce conduction losses it is desirable for a power switch control terminal, e.g., the IGBT gate, to be held at the highest possible voltage when the device is on. Device datasheets usually state 15V as the normal operating point with absolute maximum at 20V. Silicon carbide (SiC) MOSFETs on the other hand are usually expected to be operated at 18-20V with a higher absolute maximum. To make a universal gate drive it is desirable to be able to configure the gate voltage.

Most power semiconductors have a short-circuit withstand capability. This is a time (typically 10us) during which the device can withstand excessive current without failure. It is desirable that the gate drive can detect this condition and turn-off the IGBT safely within this time. The time is usually specified at a particular gate voltage.

In order to achieve the 10us short-circuit rating, IGBT manufacturers often trade-off conduction losses or silicon area. In other words higher performance devices could be realised if the 10us requirement was relaxed. Improved measurement and control circuits are desirable to give device manufacturers the opportunity to create higher performance devices that can still be protected under abnormal conditions.

An improved method of controlling voltage levels on a power switch control terminal is therefore desired, for example to provide advantages such as, inter alia, reduced cost, reliability, low circuit complexity, low component count, and/or lower power dissipation, etc. For use in understanding the present invention, the following disclosures are referred to: published German patent application DE 10 2006 034 351 Al, 2008.02.07; and "Advantages of Advanced Active Clamping", Power Electronics Europe, Issue 8 2009, pp. 27 -29.

SUMMARY

According to a first aspect of the present invention, there is provided a power switch driver for driving a control terminal of a power switch to drive a load, the power switch driver comprising: a controllable voltage source to provide a control terminal reference voltage; a voltage control circuit for controlling voltage on a said control terminal of a said power switch according to the control terminal reference voltage, the voltage control circuit configured to provide an output signal to vary the voltage on the control terminal; and a feedback circuit to generate a signal indicating a rate of change of at least one of a current or voltage of a said power switch and to, in response to said signal indicating a reduction of impedance of an output circuit of the power switch driver, control the controllable voltage source to reduce the control terminal reference voltage, said reduction to reduce the controlled voltage.

The output circuit may comprise at least the said power switch (e.g., in one upper or lower arm of a phase leg of a bridge circuit; other power switches of the output circuit may be comprised in that or another arm of the phase leg) and optionally at least one commutation diode in anti-parallel with a power switch, and/or the (generally inductive) load. Such a diode may be in anti-parallel with the power switch having the controlled control terminal voltage, and/or with a power switch in series with the power switch having the controlled voltage, for example a power switch in another arm of a phase leg having the power switch having the controlled voltage.

In an embodiment, a short circuit condition of the output circuit may occur if a load terminal (generally a mid-point between upper and lower arms of a half bridge circuit or phase leg) becomes connected to a power rail, for example if one or more power switch(es) and/or diode(s) fails or the load becomes shorted to a power rail. Where such a short-circuit condition occurs, voltage on the above power switch control terminal is preferably to be reduced.

The reduction of impedance, e.g., resistance, of the output circuit, may represent a sudden and/or abnormal reduction in the impedance. An embodiment may be applied to protect the power switch, e.g., IGBT, by reducing the voltage on the control terminal (e.g., gate) when current through the power switch increases, while allowing lower power dissipation under safer operating conditions. Thus, the reduction of the controlled voltage may occur upon detection of a potential short-circuit condition of the output circuit during operation of the power switch at a boosted control terminal voltage. Such voltage reduction may reduce the extent to which the power switch is turned on. Advantageously, the power switch may then operate at a safe voltage, e.g., at a control terminal voltage below the manufacturer's recommended normal operating voltage.

A specific embodiment may for example monitor rate of change of current through the power switch, e.g., by detecting voltage across a (preferably stray) inductance, for example inductance of an IGBT Kelvin emitter, in order to indicate the said rate of change. The controllable voltage source may comprise a digital-to-analogue converter (DAC). The control of voltage on the control terminal may comprise controlling current of a current sink or source providing current to/from the control terminal. Thus, the output signal may be a current signal.

It is noted that the references to reduction of control terminal reference voltage and/or controlled voltage may refer only to magnitude of the voltage(s).

The voltage control circuit may comprise a gate voltage feedback circuit configured to control an output stage of the power switch driver dependent on the control terminal reference voltage and an indicator of voltage on a said control terminal, the output stage configured to control the reduction of controlled voltage according to an output of the gate voltage feedback circuit. Such an output stage may comprise a current source or sink, or may comprise a controllable resistor (e.g., variable and/or programmable Roff or Ron) and/or a control switch (e.g., NMOS or PMOS). Such a controllably output resistor may replace the fixed output resistor of a standard gate drive such as is shown in Fig. 1. The gate voltage feedback circuit may comprise a comparator to receive a first input depending on the control terminal reference voltage and/or control terminal voltage, and a second input to receive a bias signal, the output of the comparator to control the output stage. An amplifier and/or voltage buffer may further be provided to forward the comparator to a drive stage, e.g., resistor emulation stage, to control the drive output stage and thus control terminal voltage.

Thus, a gate voltage feedback circuit may control terminal voltage based on a control terminal reference voltage, an indicator of the control terminal voltage and/or a signal indicating an output stage impedance reduction.

There may further be provided the power switch driver, comprising: an input line to receive a turn-on signal to instruct turn-on of the power switch, wherein: the voltage control circuit is configured to, in response to a said turn-on signal, raise the voltage on the control terminal to a boost voltage; and said reduction of the controlled voltage is a reduction from the boost voltage. The raising the voltage may occur immediately, or at a preferably (i.e., optionally) predetermined delay, after the turn-on signal. The boost voltage is preferably a higher voltage than the normal operating point of the power switch (e.g., as indicated in a manufacturer's datasheet). The boost voltage is similarly desired to be lower than the maximum safe voltage of the power switch (e.g., as indicated in a manufacturer's datasheet). The input line (comprising, e.g., a track, wire, connector and/or pin, etc.) may receive the turn-on signal in the form of an edge of a pulse width modulation signal.

The feedback circuit may comprise a comparator to receive the signal indicating a said rate of change and to compare the received signal to a threshold, e.g., threshold value, the comparator configured to output a result of a said comparison to provide the indication of reduction of impedance.

The voltage control circuit may be configured to, in response to the turn-on signal, control the output signal to generate a first voltage on the control terminal of the power switch, the voltage control circuit configured to further control the output signal to generate the second, boost voltage on the control terminal of the power switch at a time delay after the first voltage is generated. The first voltage is preferably sufficient to turn the power switch on. The boost voltage may turn the power switch on to a harder, or lower loss, state compared to that of the first voltage. In embodiment, this may mean that the power switch control terminal is raised to its normal operating voltage before it is boosted. The time delay may be for ensuring that the power switch has not turned on into a short circuit. For example, the time delay may be a few micro-seconds, e.g., 5-7us.

The reduced control terminal reference voltage below the boost voltage may have the same voltage level as the first voltage, though more preferably is less (in magnitude) the first voltage. This may mean that the voltage of the power switch control terminal is pulled back to the normal operating voltage, or lower, when a short-circuit condition of the output circuit is detected. The power switch may thus be pulled back to a safer and/or higher loss state.

Further in this regard, the reduced control terminal reference voltage preferably maintains the power switch on. In such an embodiment, while the boost voltage may have been temporary, the power switch may remain on after the reduction from the first voltage.

The feedback circuit may be configured to, at a (preferably predetermined) time delay after the control to reduce the control terminal reference voltage, control the controllable voltage source to reduce the control terminal reference voltage to turn a said power switch off. Thus, the control terminal reference voltage may be turned off in stages from the boost voltage via a reduced, preferably recommended normal, operating voltage.

In a preferred embodiment, the power switch driver may be combined with an adaptive drive. An adaptive drive advantageously comprises a circuit for impedance emulation, e.g., resistor emulation, rather than using a fixed or variable output stage resistor for example.

The power switch driver may have a negative feedback circuit to control current delivered to the control terminal, the negative feedback circuit comprising: a current output circuit comprising at least one of a current source and a current sink, the current output circuit for providing a said current of a said control terminal and configured to receive an output current control signal to control magnitude of the current provided by the current output circuit; a terminal voltage input circuit for receiving a voltage from a said control terminal and to output an indication of said voltage; an amplifier coupled to amplify the terminal voltage indication to generate an amplifier output; and a reference voltage input circuit for receiving a reference voltage, comprising at least one resistor, the reference voltage input circuit coupled to a charge supply input of the amplifier, wherein the power switch driver is configured to generate the output current control signal dependent on the amplifier output, and wherein the power switch driver is configured to reduce the current provided by the current output circuit responsive to an increase in the voltage received by the terminal voltage input circuit.

In an embodiment, such a power switch driver may present a controlled output impedance to drive the power switch. Advantageously, such controlled output impedance may be considered to be an emulated resistance. Specifically, one or more of a fixed, variable and/or programmable resistor(s) may in an embodiment allow a supply or reference current (Iref) to be set to the amplifier, the reference current further depending on a fixed reference voltage (e.g., OV or 3V3). Preferably, impedance of the reference voltage input circuit is substantially (e.g., exactly) purely resistive. A resistive impedance may then be emulated by the power switch driver to effectively provide a resistive output impedance to the power switch control terminal.

In embodiments, the at least one resistor may therefore determine an emulated resistance of the power switch driver.

(The amplifier, considered in an embodiment to amplify the terminal voltage indication, may comprise a voltage buffer and/or current amplifier, the amplifier preferably having high input impedance and/or low output impedance. The reference voltage input circuit may be coupled to the charge supply input of the amplifier, the charge supply input in embodiments being referable to as a power, current or charge supply input).

The output impedance of such a power switch driver may thus not be determined by an output component, e.g., a fixed resistance such as Ron or Roff as shown in the arrangement of Fig. 1, but may be at least partially determined by component(s) such as resistor(s) on an input stage of the driver. Indeed, such output resistors may not be necessary. Power dissipation may be reduced and/or thermal constraints relating for example to board layout and/or number or choice of components, may be mitigated.

The component(s) of the reference voltage input circuit may be programmable and/or controllable by digital or analogue means, to present variable impedance. For example, the at least one resistor may in embodiments comprise be at least one a digital resistor and/or controllable resistor network. Thus, an embodiment may be suitable for driving a wide range of power switches preferably with a wide range of (generally inductive) loads, advantageously without needing to change gate drive resistors according to power switch module and/or load characteristics, and/or requiring an operator to stock different power drives for different power switches and/or loads.

Further regarding the emulation, the current delivered by the current source is preferably reduced substantially (e.g., exactly or within, e.g., 1%, 2%, 5% or 10%) in proportion to the increase in the voltage received by the terminal voltage input circuit.

The power switch driver may comprise a coupling switch to disable dependency of control of the amplifier on the terminal voltage input circuit. Similarly, a coupling switch may be provided to enable dependency of control of the amplifier on the control terminal reference voltage. Thus, resistor emulation may be disabled while the driver is operated in a gate boost mode.

The power switch driver may be configured to monitor voltage across an inductance (e.g., preferably stray, inductive part of a terminal of the power switch module) to provide the signal indicating a said rate of change of current of a said power switch. For example, the inductance may be of a Kelvin emitter terminal of an IGBT module.

The power switch driver may comprise the power switch (optionally with commutation diode) and/or the load.

It is noted that a power switch driver as described above may comprise the power switch. Similarly, a power converter may be provided comprising a power switch driver as described above.

Furthermore, any power switch driver or power converter as described above may be provided, wherein the power switch comprises an IGBT (preferably including an anti-parallel diode, i.e., a so-called free-wheeling diode, optionally in the same module as the IGBT), a MOSFET such as a silicon carbide MOSFET, a HEMT or JFET, or other type of power switch. Any of these switches may be based on silicon carbide, gallium nitride or silicon technology.

According to a second aspect of the present invention, there is provided a method for controlling a drive signal to a control terminal of a power switch to drive a load, comprising: in response to a turn-on signal, controlling the drive signal to generate a boost voltage on the control terminal, the boost voltage to turn the power switch on; when the voltage on the control terminal is the boost voltage, monitoring at least one of current and voltage of the power switch to detect a reduction in impedance of an output circuit comprising the power switch; and reducing the voltage on the control terminal below the boost voltage when the monitored current or voltage indicates a said reduction of impedance.

Similarly as for the first aspect, the reduction of impedance, e.g., resistance, of the output circuit, may represent a sudden and/or abnormal reduction. An embodiment may be applied to protect the power switch, e.g., IGBT, by reducing the voltage on the control terminal (e.g., gate) when current through the power switch increases, while allowing lower power dissipation under safer operating conditions. Thus, the reduction of the controlled voltage may occur upon detection of a potential short-circuit condition of the output circuit during operation of the power switch at a boosted control terminal voltage. Such voltage reduction may reduce the extent to which the power switch is turned on, in an embodiment turning the power switch off. Advantageously, the power switch may then operate at a safe voltage, e.g., at a control terminal voltage below the manufacturer's recommended normal operating voltage.

Further similarly, the output circuit may comprise at least the said power switch (e.g., in one upper or lower arm of a phase leg of a bridge circuit; other power switches of the output circuit may be comprised in that or another arm of the phase leg) and optionally at least one commutation diode in anti-parallel with a power switch (as described above for the first aspect), and/or the load. In an embodiment, a short circuit condition may occur if a load terminal (mid-point between upper and lower arms of a half bridge circuit or phase leg) becomes connected to a power rail, for example if one or more power switch(es) and/or diode(s) fails or the load becomes shorted to a power rail. Where such a short-circuit condition occurs, voltage on the above power switch control terminal may be reduced.

An embodiment may be applied to protect the power switch, e.g., IGBT, by reducing the voltage on the control terminal (e.g., gate) when current through the power switch increases, while allowing lower power dissipation under safer operating conditions. Advantageously, the power switch may then operate at a safe voltage, e.g., at a control terminal voltage below the manufacturer's recommended normal operating voltage.

Preferably, the voltage reduction reduces the extent to which the power switch is turned on. Thus, the reduction may immediately turn the power switch off, more preferably however may maintain the power switch on at a reduced control terminal voltage. The reducing the voltage below the boost voltage may comprise reducing the voltage to the first voltage, or less than the first voltage, e.g., may fully turn off the power switch.

The controlling the drive signal to generate the boost voltage may comprise: in response to the turn-on signal, controlling the drive signal to generate a first voltage on the control terminal, the first voltage to turn the power switch on; and at a time delay after said turn-on signal, further controlling said drive signal to generate a second voltage on the control terminal, wherein the second voltage is the boost voltage, said further controlling to turn the device on to a lower loss state. The generation of the first and/or second voltage may result in a step change relative to the first voltage, or may be done gradually and/or in multiple steps. The time delay may be for ensuring that the power switch has not turned on into a short circuit. For example, the time delay may be a few micro-seconds, e.g., 5-7us.

Preferably, the time delay expires when a voltage on or across the power switch (e.g. collector or collector-emitter voltage) falls below a threshold value. To provide such a time delay, the driver may be configured to wait until the voltage falls to the normally on state (e.g., voltage on or across the power switch is 1-4V). This may ensure that the device has not turned on into a short circuit. A suitable threshold value may be, e.g., 5V, 10y or 20V.

In an embodiment, the power switch may be turned off at a time delay after said reducing the voltage on the control terminal below the boost voltage, preferably wherein said time delay is a preset time delay. Alternatively, the expiry of the time delay may be determined by comparison of a threshold value to at least one of a voltage signal and current signal of the power switch (e.g., collector current or voltage, or rate of change thereof; references herein to 'collector' or 'emitter' being replaceable by 'source' or 'drain' depending on the power switch). For some power switches (e.g., some types of IGBT), it may be desirable to wait for the power switch collector current to stop rising to determine the time delay. Detection of a positive di/dt below a threshold may allow the end of the power switch rise to be detected. Additionally or alternatively, the time delay may be determined by detecting when the voltage across the power switch has risen beyond, e.g., above, a threshold indicating desatu rati on.

Consistent with the above, the monitoring may comprise monitoring rate of change of current through the power switch. The monitored rate of change of current may be compared to a threshold value to provide the indication of reduction of impedance.

Further in this regard, the monitoring may be to detect a short-circuit condition of a said output circuit comprising the power switch and optionally a load coupled to an output of the power switch. The output circuit may further comprise a commutation diode coupled in anti-parallel with a power switch.

Preferred embodiments are defined in the appended dependent claims.

Any one or more of the above aspects and/or any one or more of the above optional features of the preferred embodiments may be combined, in any permutation. Furthermore, apparatus (method) may be provided corresponding to any of the above methods (apparatus).

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, in which: Fig. 1 shows a drive stage of an IGBT gate drive; Fig. 2 shows an exemplary drive stage of an IGBT gate drive; Fig. 3 shows a modulation of output transistor to change apparent resistance; Fig. 4 shows that resistor behaviour may be copied to the output transistor; Fig. 5 shows a current mirror that may be used to set variable resistance; Fig. 6a shows an adaptive drive comprising an output current sink (labelled for ease of representation (source) and resistor emulation stage; this may form a lower voltage side of a power switch drive; Fig. 6b shows an adaptive drive comprising higher and lower voltage sides; Fig. 7 shows example resistor selection; Fig. 8a shows an adaptive drive embodiment comprising a gate voltage feedback circuit; this may form a lower voltage side of a power switch drive; Fig. 8b shows an adaptive drive embodiment comprising gate voltage feedback for higher and lower voltage sides; Fig. 9 shows a gate voltage feedback circuit with di/dt detection, optionally to be combined with Fig. 8 or 8b to control Vref1; Fig. 10 shows an example turn on sequence with shod-circuit detection; Fig. 11 shows a power converter; Fig. 12 shows phases of an example IGBT switching waveform; Fig. 13 shows an example resistive drive with transorb clamping; Fig. 14 shows an arrangement that performs measurement of clamp voltage using a potential divider; Fig. 15 shows example timing diagram of comparator feedback with source and sink signals; Fig. 16 shows an example cycle-by-cycle control scheme for Roff or Ig selection; Fig. 17 shows an arrangement for measurement of DClink, preferably based on Vce, and changing Roff for a next cycle; Fig. 18 shows an example of measuring DClink, preferably based on Vce, and feedback circuit; Figs. 19a, b show two alternatives for an output stage; the example of Fig. 19b for a gate boost implementation is implemented with two additional PMOS transistors as shown, and may require an additional voltage rail (e.g., 18V) with associated capacitors; and Fig. 20 shows an embodiment of a gate boost method.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The following describes concepts and related embodiments, such as e.g.: a circuit for an emulated resistor, showing how a current source may be used with feedback to control the effective resistance; gate boost to reduce conduction losses including detection of high di/dt for protection under abnormal conditions; method and apparatus for controlling dv/dt by measuring time in certain states and altering the resistance to keep constant; adaptive scheme for allowing high DC link voltage, clamp levels and algorithm; a current source that behaves like a resistor (which may be disabled when in gate voltage feedback mode); - a gate voltage feedback loop with device protection under short circuit; a method for controlling dv/dt by measuring load current and adapting the drive characteristics; and - a method for preventing over-voltage by selecting appropriate resistors in a control loop depending on DC link voltage, feedback from a voltage measurement, dv/dt measurement and/or di/dt measurement.

Any one or more of the above may be achieved and/or implemented in a single embodiment. Thus, a single product that can address multiple power switching applications may be provided.

Gate Boost To reduce conduction losses it is desirable for a power switch control terminal, e.g., the IGBT gate, to be held at the highest possible voltage when the device is on. In this regard, it is desirable that a gate drive can detect a high current and turn-off the IGBT safely within the short-circuit withstand capability time.

The time is usually specified at a particular gate voltage. If the IGBT is operated at a higher gate voltage, this time is undefined, therefore it is desirable to detect a high current condition and reduce the gate voltage, e.g., to 15V, very quickly. To limit the current flowing in the IGBT it may be preferable to reduce the voltage even further (e.g. 10V) until the current stabilises and then the IGBT can be switched off a safely. An IGBT can be destroyed if it is turned-off quickly whilst the current is still changing.

It is further desirable to make a universal gate drive able to configure the gate voltage(s) at which the power switch control terminal may be held.

In view of the above, operation of a power switch such as an IGBT at higher control terminal voltage may reduce power dissipation. However, in order to protect the power switch, it is desired to reduce the voltage when high current occurs through the switch. 'Gate boost' control of gate voltage may be advantageous for driving a power switch such as an IGBT at a high voltage while allowing reduction of the voltage under a short circuit condition. Such advantages may be achievable where the power switch is provided in a power converter to drive an, e.g., inductive, load.

For controlling voltages on the control terminal, e.g., gate, it could be considered to implement two power supply rails (e.g. +15V and +18V) and switch between them. However, this may require additional power supply smoothing capacitors and/or a more complex DC-DC converter. Furthermore, capacitance in the converter and/or driver may significantly slow down switching between rails.

In embodiments, a feedback circuit may be employed to allow control terminal voltage adjustment for protecting the power switch. An embodiment may use just one rail, the rail having a voltage above the normal, e.g., manufacturer recommended, operating voltage of the power switch. The control terminal may then be operated at a high voltage, which may however be reduced by a feedback circuit upon detecting an indication of high power switch current, e.g., such current through a collector (lc), emitter, source or drain terminal of the power switch. The indication may indicate a high said current as such, or a high rate of change (preferably increase in magnitude) of such a current or, in embodiments, a high rate of change of voltage across/on the power switch.

For example, voltage across an inductance in series with the power switch (e.g., stray inductance of the power switch module) may be measured to indicate the rate of change of current di/dt, and this indication fed back to control circuitry (e.g., gate drive logic) to adjust parameter(s) to thereby reduce the power switch control terminal voltage. Additionally or alternatively voltage, or rate of change thereof, across/on the power switch (e.g., Vc, Vice), may be monitored to feed an indication back to the ctonrol circuit to adjust the parameter(s). When a value (e.g., magnitude) of, e.g., current, di/dt, voltage and/or dv/dt beyond (e.g., above) a threshold is detected, the power switch may be controlled to reduce the control terminal voltage from, e.g., 18V to 15V.

Such feedback to preferably reduce control terminal voltage in the event of a (potential) short circuit condition may be applied with or without an adaptive drive such as that of Fig. 6a or 6b. For example, such feedback may be used to control the drive of Fig. 1 to adjust gate voltage (an alternative output stage is shown in Fig. 19b). It is noted that the use of resistor emulation is not required to implement a gate boost embodiment, preferably however, the feedback is provided with an adaptive drive as for example shown in Figs. 6a, 6b and 8a/b, which may be considered as showing a negative feedback circuit comprising the (source component of an current output circuit, component R7 of a terminal voltage input circuit, an amplifier comprising 01, a reference voltage input circuit comprising resistor R5 and coupled to the emitter (in this case, the charge supply input) of the amplifier. The output signal to control the control terminal voltage may be a current signal from a current source (sink) as shown in Figs. 6a, 6b and 8a/b.

Figs. 8a and 8b show that an adaptive drive such as that of Fig. 6a or 6b may be combined with a gate voltage feedback circuit having an input (Vref1). The gate voltage feedback circuit may enable the gate to be held at any of number of different voltage levels, where the number is set for example by a digital-to-analogue converter (DAC) input to Vref1, preferably based on an above mentioned high current indication. Such voltage levels may comprise +15V (on) and/or -10V (off) for an IGBT. Such a DAC is an example of a controllable voltage source to provide a control terminal reference voltage, e.g., Vref1.

Figs. 8a and 8b may further be considered as showing a voltage control circuit comprising, e.g., the current source (sink), R8, Q2 and the amplifier having gain k1, such a circuit preferably being active when the resistor emulation is disabled by coupling switch SW1 (SW1 in an embodiment selectively disabling dependency of amplifier control on output of a terminal voltage input circuit). To enable control terminal voltage control by the gate voltage feedback circuit, the constant current and resistor emulation functions of an adaptive drive may be disabled by a switch, e.g., SW1 of Fig. 6a, 6b. The voltage control circuit may be enabled by coupling switch SW2 (SW2 in an embodiment selectively enabling dependency of amplifier output on Vref1). When resistor emulation is turned off, the control terminal voltage may be controlled by an output signal from the driver output stage preferably comprising a current output circuit, e.g., source or sink (labelled (source in Fig. 8a). It is further noted that the resistor R8 may provide the indicator of voltage on the control terminal (i.e., the controlled voltage), i.e., IGBT gate, to the gate voltage feedback circuit.

The voltage at node Vref1 may be for example OV for IGBT ON (load driven to +Vsupply by the reciprocal source circuitry (not shown in Fig. 8a)) and 3V3 for IGBT OFF (load driven to -Vsupply). With SW2 in the position shown in Figs. 8a and 8b, the gate voltage feedback circuit is disabled as Q2 is turned off. With SW2 connected to Vbias2, the gate voltage feedback control loop may be enabled. Vbias2 is a voltage in the range of, e.g., OV to 3V3, and may be chosen to ensure that the circuit does not dissipate excessive power. The Vref1 control, e.g., by DAC, may enable the voltage range to be adjusted to suit different power switches, e.g. -10y to +15V for an IGBT, -5V to +20V for a silicon carbide MOSFET. Vbiasl may be a voltage in the range OV to 3V3, e.g., 1V65 in a 3V3 system, but its value is less important.

Such control of gate voltage may be further refined to enable driving of a power switch, e.g., IGBT, at a high voltage, but reducing the voltage under a short circuit condition. Fig. 9 shows an example of how the rate of change of power switch current may be measured and fed back to control a gate voltage feedback circuit such as that of Fig. 8a or 8b, preferably by means of gate drive logic. Specifically, the signal fed back from the power switch to indicate a reduction in impedance of the output circuit (preferably using a threshold comparison) may be used to control Vref1. Alternatively or additionally, the collector voltage (and/or rate of change thereof) may be fed back to indicate the reduction in output circuit impedance. Preferably this may be achieved using a potential divider wherein R1, R2 step the voltage down and optional capacitors C1 and/or C2 improve the speed of response Merely for clarity, the gate voltage feedback is not shown in Fig. 9, which for example short-circuit detection circuitry. However, the gate voltage feedback and control is shown Figs. 8a, 8b. Di, U2 and Li of Fig. 9 are part of a power converter, an example of which is shown in Fig. 11.

In view of the above, as shown in Fig. 9 the voltage detector coupled to the inductance L2, and comparator coupled to the feedback (F/B) input, may be considered to form at least part of a feedback circuit to generate a signal (e.g., a signal on the IN+ input of the comparator of Fig. 9) indicating rate of change of current or voltage of the power switch and respond to such a signal indicating a reduction of impedance of the driver output circuit (e.g., the output circuit comprising, e.g., the power switch U2, a commutation diode D1 and/or load (not shown in Figs. 8a, 8b and 9)).

Thus, Fig. 8a and/or 8b may be combined with Fig. 9 such that the output from the di/dt comparator is fed back to gate drive control circuitry (e.g., gate drive logic of Fig. 9), which in response to the output indicating an above mentioned reduction of impedance controls a reference voltage input Weft Additionally or alternatively a comparator may be provided, e.g., within the gate drive logic, for comparison of a collector voltage feedback signal to a threshold value. Similarly may be provided for comparison of a rate of voltage change.

An example sequence of events is shown in Fig. 10. Specifically, Fig. 10 shows a turn on sequence with short-circuit detection, wherein a turn-on signal (e.g., an edge of a pulse width modulation (PWM) signal) is received (for example on the PWM input line of Fig. 9) and the driver begins to turn on the power switch. Thus, the control terminal voltage Vge is increased, optionally non-linearly as shown in Fig. 10. After turn-on and a preferably predetermined/preset delay, e.g., a suitable settling time to allow the voltage across the device to fall (i.e. suitable such that generally the switch does not turn on into a short circuit), the gate voltage Vge may be raised (e.g. to +18V). This increase of Vge may be in response to a BOOST signal responsive to expiry of the delay. If high di/dt of the collector current is detected while BOOST is active, the high di/dt signalling a short circuit of the IGBT and/or load, the BOOST signal may return to an inactive state and the gate voltage consequently immediately returned to, e.g., +15V (or lower), before being turned off after a further (preferably predetermined) delay. This "gate boost" capability may in an embodiment enable conduction losses to be reduced, e.g., by approximately 10%.

It is noted that the BOOST signal in Fig. 10 may be responsive to the feedback signal (F/B) indicating rate of change of collector current Ic (or drain-source current for a MOSFET) beyond a threshold. The same or different thresholds may be used to activate and deactivate BOOST. Use of the BOOST signal however is optional. Any one or more of the timing(s) of raising Vge to the boosted voltage, returning Vge to the lower voltage and/or turning off the power switch may be determined for example by a detection based on the measurement of di/dt, measurement of voltage on/across the power switch (e.g., Vc, Vice) and/or use of a timer to implement any delay beyond such a detection. For example, the gate drive may act to turn the power switch turned off when the di/dt has not exceeded a threshold value during a preset delay time after the return of the gate voltage to the lower level (e.g., 15V).

Consistent with the above, the features 1 -6 as shown in Fig. 10 correspond to, respectively,: (1) signal to turn on; (2) gate voltage increased; (3) short circuit occurs; (4) dlc/dt threshold exceeded; (5) gate voltage reduced; and (6) turn-off after Ic stabilises. The Vge voltage preceding feature 2 may be considered to be a first voltage and the Vge voltage between features 2 and 5 a second, boost voltage. The Vge voltage between 5 and 6 may be substantially (e.g., exactly or within 10%) equal to, or less than, the first voltage.

There are many different ways to detect current and/or di/dt, such as that shown in Fig. 9 involving measuring voltage across a stray inductance (Le) between the auxiliary or kelvin emitter (ke) and the power emitter (e). If this voltage exceeds a specific threshold, then the gate drive may be signalled to lower the gate voltage.

Emulation In a typical implementation, Ron and Roff are physical resistors. In some instances it is desirable to be able to change the resistors without soldering. It may therefore be advantageous to make the resistors programmable so that the resistors can be changed under software control, either statically or dynamically during operation.

One way to achieve this, now conceived of by the present inventors while devising the invention claimed herein, is to replicate the level translation, drive and output stages a number of times. Ron and Roff resistors can then be combined in different combinations to select various resistances. With N resistors there are 2N-1 combinations of resistors, e.g. 8 output stages would allow 255 different resistor settings.

An arrangement now conceived of by the present inventors is shown in Fig. 2 where the level translation and drive stages are combined, and the output stage has been separated into source and sink blocks. (Note that the source and sink parts of the circuit are complementary. Other circuit diagrams provided herein may just show either the sink or source part).

This approach may be desirable in circumstances; however there may be a number of disadvantages. Firstly a very large number of components may be required to provide a reasonable (>10) set of resistor values and this may lead to excessive board area. Also, power dissipation in the output stage transistors and resistors may not be evenly distributed across all components, as some may be permanently OFF in a particular implementation. This leads to over-rating components which may in turn lead to increased board area and/or cost.

Another approach is to replace each of Ron and Roff with a digitally programmable resistor. However, while such parts exist, they are generally not suitable in this context as they may need to be able to handle pulsed currents and high power dissipation.

Power dissipation and/or thermal performance may thus be of concern regarding resistive drive designs, bearing in mind for example that control of the ambient environment, e.g., by providing a fan, is generally not possible and/or desirable (for example due to cost). Similarly, mitigating high power dissipation by monitoring of temperature and/or derating a circuit, e.g., by limiting switching speeds, may be undesirable from the point of view of, inter alia, cost and/or converter performance.

As discussed above with reference to Figs. 1 and 2, in some instances it may be desirable to be able to change the output stage resistances of a gate drive circuit without soldering. Preferably this is done while allowing for, e.g., good power conversion and/or thermal performance of a power converter.

An addition or alternative to the digitally programmable resistor or replicated stages as discussed above is to turn the output stage transistors ON an OFF (e.g., switch them in and out of the circuit) with a varying duty cycle as shown in Fig. 3. (This idea is similarly now conceived of by the present inventors). The turn-OFF resistor value (Roff) is proportional to R1 and the duty cycle of the transistor M1. For this to be effective the modulation frequency of M1 is preferably high (>1MHz) and suitable to smooth the current flowing into and out of the power switch; some inductance may be required. Generally, high frequency leads to high switching power dissipation in M1 and extra inductance may limit the speed at which the control terminal (e.g., gate) current can be changed, which is undesirable in some control applications.

A further development of this idea is shown in Fig. 4. In this case a fixed resistor R2 is used so that the output stage has the characteristics of a resistor. However the variable resistance is created by driving transistor M2 in its linear region so that its resistance is a multiple of R2. The voltage drop across R2 is R2*control terminal current. This voltage is measured and then passed through an amplifier with gain k1. This is compared to the voltage measured across M2. M2 is driven with an amplifier of gain k2. A feedback control loop is created which in its steady state ensures that the voltage drop across M2 is the multiple of k1 and the voltage drop across R2. Therefore, in this case Roff is equal to R2*(1+k1).

Such a circuit may be desirable in circumstances. However, one potential disadvantage of this circuit is that a variable gain amplifier (k1) may be needed, and this may be difficult to implement and drive from digital logic.

A modification of Fig. 4 is shown in Fig. 5. Here, R2 is replaced by transistor M4 with a further transistor M5 used to set its resistance. Preferably M4 and M5 are co-packaged so they have the same characteristics and as M4 and M5 share a common gate connection, the resistances of M4 and M5 are equal. The voltage drop across M5, and therefore its resistance, is set by an input voltage reference (Vref) which can be driven from logic levels. In this design, gains k1, k2 and/or k3 can be fixed. However the circuit uses a number of expensive operational amplifiers and depends on good matching of M4 and M5 for accuracy.

A preferred approach is however a power switch driver in the form of an 'adaptive drive' as shown for example in Fig. 6a or 6b. An adaptive drive advantageously comprises a circuit for resistor emulation, rather than using a fixed or variable output stage resistor. In the example circuit of Fig. 6a or 6b, this is generally achieved by using a current source to provide a control terminal current that is equivalent to the current flowing through a resistor. The reference voltage (Vref) is provided by digital logic. The reference voltage input can be at OV, logic level high (e.g. 3V3) or open circuit for example. The reference voltage input circuit receiving reference voltage Vref may comprise resistor R5 used to select the resistance desired to be emulated. A logic high voltage on Vref causes current Iref to flow through R5, Q1 and R4. At least Q1 and R4 may be considered as providing an amplifier with the amplifier output being considered as current through, or voltage across, R4. (The amplifier may have a standard configuration, e.g., of a buffer and/or collector follower). In Fig. 6a or 6b, the emitter of Q1 may be considered to be a charge supply input of the amplifier. Note that R6 and R7 may have significantly higher impedance (e.g. 50x) compared to R5, R4 and the on resistance of 01, so that no appreciable current flows in this path. (R6 may be considered as a coupling between the terminal voltage input circuit and the reference voltage input circuit). The voltage measured across R4, amplified with gain (k1), is used to set the current level of a current output circuit such as a current source (Isource; in another embodiment the current level of a current sink may be set instead). In one implementation k1 is set so the ratio of Iref to Isource is 1:250, but various combinations of gain and source/sink current could be chosen to match the requirements of different power switches. The output of the amplifier with gain k1 may be considered in an embodiment to be an output current control signal.

The voltage at the control terminal varies over a range of, e.g., -10y to +15V for a power switch such as an IGBT. In a resistive drive, the control terminal current may be proportional to the difference between the supply voltage and the control terminal voltage. In other words, during turn-ON, as the control terminal (gate) voltage gets closer to +15V the current reduces to zero. Regarding a terminal voltage input circuit, R6 with/without R7 may be used to measure the control terminal voltage. As the voltage at the node between R6 and R7 increases the transistor Q1 is driven so that the current in R4 is reduced in proportion. This may in turn reduce the control terminal current in a way that emulates the behaviour of a resistor. Thus a negative feedback loop for allowing an output current source/sink to emulate a resistor may be formed.

Regarding an offset voltage input circuit preferably comprising the comparator and buffer leading to SW1 as shown in Fig. 6a or 6b, the offset voltage Vdc_offset on an input line of the comparator may allow the voltage range of the control terminal to be varied. This may be achieved by the comparator generating an amplification control signal. For an IGBT the voltage range might be -10V to +15V. For a silicon carbide (SiC) MOSFET the gate voltage range might be -5V to +20V. A constant voltage applied at Vdc_offset, in combination with R6 and R7, may set the translation between the logic levels (e.g. OV and 3V3) and the control terminal voltage.

Optional coupling switch SW1 may allow the resistor emulation function to be turned off (base of Q1 open-circuit), operated as a constant current sink (base of Q1 connected to ground) or enabled. A current drive may be preferable to a voltage source and resistance (resistive drive) under certain conditions described later.

An embodiment of an adaptive drive circuit such as that of Fig.6a or 6b can be implemented with a small number of components and so may be compact. Furthermore, in embodiments the power dissipation may always be in the transistors that implement the Output Stage current source or sink, and this may lead to a simplified layout and/or easier cooling.

To vary the emulated resistance, it is preferable that R5 can change. This can be implemented with a circuit shown in Fig. 7, for example. In such an embodiment, SW1a is used to select either a logic 0 or 1 through a buffer to drive resistor R1. SW1b is used to enable or disable the output, thus R1 is driven with OV, 3V3 or is open circuit. SW2a/b and R2 form the next resistance in sequence, where the value of R2 is twice that of R1. SW3a/b and R3 form the next stage where R3 is 4 times R1. This continues for as many stages as required, N in Fig. 7, giving 2N-1 possible resistors. The switches and buffers are easily implemented in digital logic circuits (such as a PLD or FPGA) and the resistors can be small signal types as they are not required to dissipate the power switch control terminal current, only a small fraction of it. An advantage of this is that, in embodiments, multiple resistance values can be emulated with very little board area.

It is noted that to satisfy a range of different IGBT modules and power loop topologies (stray inductance), it is desirable that the emulated resistance is configurable. An adaptive drive embodiment, based for example on Fig. 6a or 6b, may enable the resistance to be set with an n-bit digital-to-analogue converter (DAC). For example an 8-bit DAC allows 256 (2 to the power 8) resistance values to be configured. Such a scheme could be implemented with multiple parallel resistors, but this may have a number of drawbacks including: adding extra bits takes more board area as the pulse resistors can dissipate significant power; and/or power dissipation is not uniformly distributed across the resistors. It is further noted that such embodiments of the adaptive drive may require one extra pin (on a programmable device) and/or two tiny resistors for each extra bit, so the board area is negligible and the power dissipation is concentrated in the output transistors regardless of the emulated resistance.

In an embodiment, power dissipation may be constrained to the output stage making it easier to manage for a wide range of emulated resistors. Thus, improved thermal performance may be achieved.

Control regarding dv/dt A typical power converter, an example of which is shown in Fig. 11, may comprise multiple power switches, e.g. IGBTs (U1 to U4), a load (L1), and a capacitor bank (C1) which maintains a voltage across the converter (DClink). Fig. 11 may be considered as showing two half bridge circuits (U1/D1 + U2/D2, and U3/D3 + U4/D4) providing a full bridge circuit to drive the load L1. Thus, U1 and U2 (similarly U3, U4) provide a series connection of first and second power switches of a half bridge circuit. In Fig. 11 each power switch is coupled in anti-parallel with an optional freewheeling diode (D1 -D4).

To control power flow the current in the load (for example a motor) may be measured and fed back to a control unit. The DC link voltage may also be monitored and preferably regulated to ensure it does not rise above the maximum blocking voltage of the power switches.

In situations where the load is a wound component, such as a motor, it is sometimes desired to limit the maximum rate of change of voltage (dv/dt) seen across the load.

This is because the insulation of the wound component can be damaged due to current flowing through the insulation capacitance between windings. As the IGBTs switch they may impose a sudden change in voltage (dv/dt) at the mid-point between U1 and U2, and U3 and U4. This dv/dt can in embodiments be controlled by the gate drive attached to each IGBT.

If the gate drive is a voltage source and resistance (resistive drive) then the dv/dt seen by the load is proportional to the resistance at turn-ON and turn-OFF. At high load currents, the dv/dt is low and at low load currents the dv/dt is high (e.g. 4 times greater). If it is desired to limit the dv/dt at low load, then it may be preferable to select a larger gate resistor than would be the case at high load. A side effect of this may be to increase power dissipation which is undesirable in a power converter.

The adaptive drive described above, e.g., as shown in Fig. 6a or 6b, may provide a cost effective solution to this problem. Because the emulated resistance can in embodiments be changed, e.g., under software control, the resistance can in embodiments be changed depending on the load conditions. A feedback control scheme may measure the load current and send a signal to the gate drives (e.g. CTRL1-4) to set a resistance proportionally.

Additionally or alternatively the current in the IGBT may be measured locally by the gate drive and an appropriate resistance set without the intervention of the system controller. Various means of measuring current at the gate drive may be employed, such as integration of di/dt which is found by measuring the voltage developed by the stray emitter inductance (Le in Fig. 9). Other methods include Hall-effect sensors, magneto-resistive sensors, or power switches with a current sense emitter (IGBT) or current sense source (MOSFET, JFET or HEMT).

An additional or alternative way to control dv/dt is to drive the IGBT with a constant current. In this case dv/dt is proportional to the source or sink current and does not depend on the load. The resistor emulation circuit can be turned into a constant current source by turning off the emulation function, SW1 in Fig. 6a or 6b.

In some circumstances it is desirable to change between resistor emulation and a current source.

Considering the example waveforms as shown in Fig. 12, during each phase (1-10) of an IGBT switching waveform different drive mechanisms may be employed to optimise behaviour. In this regard, the waveform of Fig. 12 shows one switching cycle of the IGBT has an ON interval having: (i) a fully on period comprising at least phases 4 to 6 of 3 to 6; 00 a fully off period comprising phases 1 and 10; a turn-on period comprising phases 2 and/or 3; a turn-off period comprising phases 7 to 9. (Phase 3 may be considered to be part of the turn-on period, or an ON phase that is a subsequent period, i.e., immediately following, relative to turn-on phase 2).Thus, Fig. 12 shows that a switching cycle may comprise an ON interval and an OFF interval of the IGBT. In some circumstances a voltage source with resistance to set the drive current is optimal, at other times a current source is preferable, and at others it is better for the gate to be held at a specific voltage. An adaptive drive such as that of Fig. 6a or 6b may fulfil these three tasks in one optimal circuit design. The drive profile can be fixed or changed during operation, either within a single cycle, from cycle to cycle due to change in load conditions, or over the long term due to parameter variance (e.g. degradation due to ageing).

With reference to Fig. 12, and considering specifically how to change between resistor emulation and a current source, consider for example turn on during the turn-on period comprising phase 2 and/or 3. The peak in collector current (lc shown in red) between phases 2 and 3 is due to diode reverse recovery. To protect the diode from excessive power dissipation it is preferable to ensure the diode stays within its safe operating area (SOA) during this phase where both voltage across the diode and current through it may be high. The diode characteristics may be tuned with a resistive IGBT gate drive as the reference drive circuit. During phase 2 therefore a resistive emulation may be preferable. In the case where dv/dt is desired to be controlled, it may be considered to either change the resistance based on the load, or employ a constant current source. Therefore in phase 3 (which may be considered to be a period subsequent to a turn-on period comprising phase 2), where the voltage is changing rapidly it may be desirable to switch to a different resistor setting or to constant current source.

Similarly during turn OFF, phases 7-9, there may be a need to change gate current or resistance in order to limit the dv/dt, the maximum voltage across the IGBT (Vice shown in blue), or the rate of change of collector current (dlc/dt).

An adaptive drive circuit for example based on Fig. 6a or 6b may enable these configuration changes without the need to use two or more different circuits.

One method to measure the load current without the need for additional circuits is to measure the time in certain phases. During turn-ON, the time spent in phase 2, or 2 and 3, may give an indication of the magnitude of the load current. During turn-OFF the time spent in phase 8 may similarly indicate the magnitude of the load current.

This is particularly true if the di/dt is constant or changing little with load. Certainly resolution is sufficient to select a small number of different resistors. For example a system clock of 100MHz can measure, using a counter, the time the IGBT spends in each phase to an accuracy of 1Ons. An example time in phase 2 or 8 might be 0 to 500ns, which corresponds to a count value of 0 to 50. In this case it may be appropriate to select one of 5 different resistors for counts of 0-10, 11-20, 21-30, 3140, and 41+ for example.

Further regarding the above, it is noted that: the start of phase 2 may be indicated by detecting with a di/dt sensor a positive measurement (generally small) of di/dt (the current i being for example a collector current). Such a measurement may indicate voltage dropped across emitter stray inductance in an embodiment; the start of phase 3 may be indicated by detecting a reversal in direction of rate of change of current, e.g., collector current. Such a reversal may occur when the di/dt goes negative; the start of phase 4 may be detected when the voltage across the power switch, e.g., Vice of an IGBT) goes below a threshold, e.g., 10V; and/or the start of phase 8 may be detected when di/dt goes negative. The end of phase 8 may be indicated by detecting when di/dt goes below a negative threshold, this indicating in an embodiment that current is not changing.

Clamping In a power converter, at turn-off there is generally a relationship between the DC bus voltage (Vdc), the rate of change of current (di/dt), the commutation loop inductance (L) and the peak voltage (Vpeak) experienced by the power semiconductor. This is described in the equation, Vpeak = Vdc + L di/dt. The peak voltage is preferably kept below the IGBT maximum rating. For a given layout topology the inductance is fixed. There may be a trade-off between maximum allowable DC bus voltage and maximum switching speed (di/dt).

This may be achieved by either measuring and limiting di/dt to a pre-determined value, or by measuring the voltage across the IGBT and limiting its switching speed to keep the voltage within its rating. The latter is known as active clamping and is often performed by a string of transient voltage supressors (TVS or transorbs) connected between the collector and gate. A TVS is a type of passive component that conducts when the voltage across it exceeds a specific value. If the voltage across the IGBT exceeds a pre-determined clamp voltage, the TVS chain conducts injecting current into the gate. This has the effect of opposing the turn-off current flowing out of the gate, slowing down the switching process and limiting the di/dt.

A TVS clamp circuit may have any of the following limitations: Power dissipation of the TVS chain is limited which means the clamp circuit can only be used periodically and is not normally suitable for continuous operation.

The relationship between current and breakdown voltage (the point at which the TVS begins to conduct) has a wide tolerance. The breakdown voltage also varies with temperature which means it is difficult to precisely guarantee the clamp voltage and derating is required, leading to a lower maximum DC bus voltage than would otherwise be required.

It is necessary to detect the current flowing in the TVS chain and turn off the drive circuit to prevent the two circuits opposing each other leading to excessive power dissipation (this is known as advanced active clamping).

The clamp voltage required to protect the IGBT during turn-off may be too low to allow normal operation of the converter. It is not possible to dis-connect the TVS chain, so a work-around is to employ a 2-level clamp so that the clamp voltage can be raised when the IGBT is off.

Creepage and clearance (spacing between components) of the high-voltage TVS chain means the board area required is significant. The area is even greater with the added complexity of advanced active clamping and 2-level turn-off.

For these reasons an improved clamping scheme is desired to address any disadvantage(s) such as one or more of the above.

In an embodiment, a clamp voltage can be precisely set with an n-bit DAC. During turn-off (and only during turn-off), if the voltage across the IGBT goes beyond, e.g., exceeds the clamp voltage, the drive circuit which is sinking current, may be turned off and current injected into the gate, slowing down the turn-off and limiting rate of change of collector current (di/dt). In an embodiment where a common drive stage is used and the drive circuit cannot simultaneously source and sink current, there may generally be no possibility of excessive power dissipation. The voltage may be measured by a potential divider, which may have similar creepage and clearance requirements to a TVS chain, but as there may generally be no appreciable power dissipation in the potential divider, the components can be reduced in size (compared to the TVS chain) and/or also encapsulated in a "potting" compound to reduce size further.

In embodiments, the clamp voltage can be set over a wide range making a single design applicable to a range of IGBTs and operating conditions. Furthermore, the voltage measurement circuit can be shared with other functions, such as overcurrent protection (measurement of the on-state voltage drop across the IGBT). One enhancement found to be advantageous is to add in a component of dv/dt which gives advance warning of the IGBT reaching the clamp voltage.

Considering clamping using transorbs, Fig. 13 shows part of the H-bridge circuit from Fig. 11. IGBT U2 is shown with its commutation diode D1 and some stray inductance (Lstray) which is always present in a practical implementation. The output stage of the gate drive is shown with a voltage clamping circuit comprising T1 and R1.

During turn-OFF of U2, a voltage develops across Lstray due to the change in current di/dt. The voltage is proportional to Lstray and di/dt. This voltage adds to the voltage across C1. If the sum of these voltages exceeds the maximum voltage rating of the IGBT (U2) then it may be destroyed. The clamping circuit is employed to limit the voltage across the IGBT. T1 is a transient voltage suppressor (TVS) also known as a transorb. T1 has a breakdown voltage, and when exceeded current will flow from the IGBT collector (c) to the gate (g). The effect is to inject current into the gate and effectively slow down the turn-OFF. This limits di/dt and therefore the maximum voltage developed across Lstray.

In another scheme, the NMOS transistor is turned off when current is detected in R1 to avoid excessive power dissipation and increase the effectiveness of the clamping action.

Transorb T1 may be replaced with two or more devices to reach a specific breakdown voltage to match the IGBT. For example in a gate drive for a 1200V IGBT, a string of six 130V transorbs may be used to give a breakdown voltage of 780V. If the voltage across the IGBT exceeds 780V then current will flow in the transorbs and limit or clamp the voltage. However, transorbs exhibit wide tolerance range and temperature dependence. This is why it is preferable to set the breakdown voltage at 780V for a 1200V device. If the DC link is above 780V the transorbs may be continuously conducting. This is undesirable as power dissipation limits lifetime. In practice therefore such an approach generally only works well for infrequent or abnormal conditions, unless the transorbs are significantly over-rated. The maximum DC link voltage may also be limited well below the IGBT limit.

Embodiments however use a potential divider to measure the voltage across the power switch, e.g., IGBT (U2). An example is shown in Fig. 14, showing merely for example a first power switch U2 of a lower arm of a half bridge circuit (an optional commutation diode of this arm not shown) and a commutation diode D1 of an upper arm of the half bridge circuit (a second power switch, i.e., that of an upper arm, not shown). The generally inductive load L1 is coupled to an output line connected between the lower and upper arms. The combination of R1/C1 and R2/C2 series capacitive impedances form a potential divider. (Example component values being R1=3KOhms, R2=1.5MOhms, C2=20pF and/or C1=10nF). The voltage across R1 is measured and compared by the clamp comparator to a reference voltage (Vclamp). Thus, in this example the R1 voltage is used as an indicator of a power switch variable in the form of the emitter-collector voltage of the power switch U2. If the voltage across R1 exceeds a clamp value Vclamp, the output of the comparator is a logic high (1) and if less than Vclamp the output is a logic low (0). Preferably the series impedances have a ratio such as 500:1 for, e.g., R1C1:R2C2, over the required bandwidth from DC to a high frequency beyond which the ratio may roll off/up.

The comparator output is fed back to the gate drive control logic which in turn reverses the current flow. The sequence of events is shown in Fig. 15.

The drive stage shown here could be a standard resistive drive, or an adaptive drive described earlier, e.g., as shown in Fig 6a or 6b. The signals SOURCE and SINK denote whether the drive circuit is sourcing or sinking current, preferably regardless of the implementation.

For more effective operation it is preferable to minimise the propagation delay of the feedback, e.g., from voltage sense, through the Comparator, Gate Drive Logic, Drive Stage and Output Stage. In practice it is difficult in some embodiments to achieve high bandwidth of this feedback control circuit, even if the digital logic is removed and the full circuit is implemented in analogue electronics. With insufficient bandwidth in the loop, the result may be overshoot beyond the clamp voltage (Vclamp) as shown in Fig. 15.

However, a cycle-by-cycle control scheme may be used to select an appropriate turn-OFF resistor or reduce an output current, e.g., the current provided by the current output circuit of Fig. 6a or 6b (such output current being determined for example by a controllable resistor R5). In embodiments such a scheme may reduce or prevent such overshoot. An example of such a scheme is shown in Fig. 16. For embodiments, Fig. 16 may be understood as referring to a resistor Roff (see Fig. 1 or 13) that is in embodiments controllable (e.g., digital resistor and/or resistor network), the voltage across the power switch (collector-emitter voltage Vice for an IGBT), control terminal (e.g., gate) current of the power switch (Ig), rate of change of current through the power switch (e.g., collector current di/dt of an IGBT), rate of change of the voltage across the power switch, and/or a clamp value Vclamp.

By default a high value resistor Roff may be chosen. If the voltage on/across the power switch (Vc, Vice)) at turn-OFF does not exceed the set clamp voltage, the resistor setting may be reduced on the next cycle. This may continue until the clamp is reached. If the clamp voltage is exceeded then the resistor setting may be increased. The comparison to the clamp voltage may be performed by a limit comparator, e.g., the above-mentioned clamp comparator of Fig. 14.

More generally, the comparison may be of rate of change of current through the power switch (dlc/dt for an IGBT) relative to a di/dt limit value, or of rate of change of the voltage on/across the power switch (e.g., dVc/dt) relative to a dv/dt limit value.

A similar scheme using a constant gate current (Ig) could be implemented. Such a scheme may reverse a current between the switch drive and control terminal. This may comprise switching or changing a fixed and/or constant current or emulated resistor. With a resistive drive, the rate of change of voltage (dv/dt) across the power switch may give some advanced indication of the di/dt (rate of change of, e.g., collector current) that will occur. Measurement of dv/dt, implemented for example with a capacitor to the IGBT collector terminal (c), may be used in the feedback control loop described in Fig. 16. Similarly di/dt could be used as an input to this process.

Additionally or alternatively, resistance may be changed based on the DC link voltage, for example by making use of a standard drive as in Fig. 1 albeit with controllable output resistance(s), or an adaptive drive such as that shown in Fig. 6a or 6b. If the turn-OFF resistance is increased, or turn-off current reduced, the turn-OFF di/dt will be reduced, and in turn the voltage overshoot due to the stray inductance will be reduced. The turn-OFF resistance may be Roff of Fig. 1 when implemented as a controllable resistor having controllable output resistance, Roff here in series with an NMOS control switch (in another embodiment the control switch may be p-type). In an embodiment having adaptive drive, e.g., as in Fig. 6, the controllable output resistance may be an emulated resistance, e.g., emulation of R5 in Fig. 6a or 6b.

A high value resistor is undesirable at low DC link voltages, where clamping may not be necessary as the power dissipation (turn-OFF switching loss) in the IGBT be increased. At high DC link voltages, the power dissipation may be dominated by the energy stored in the stray inductance, so using a high value resistor (switching slowly) may result in the same power dissipation as switching fast and clamping.

A feedback control scheme based on monitoring the DC link is proposed. This could be implemented in a central controller or the gate drive.

Fig. 17 shows an example a timing diagram with DC link rising over time. The DC link is measured, preferably based on collector voltage for example by means of a potential divider (see Fig. 18), and Roff changed to limit the switching speed at the next turn-OFF event. In practice the change in DClink would be slow so it may not be necessary to change resistor setting on every switching cycle, but it is possible.

For a given converter Lstray can be measured, and a look-up table created to select an appropriate resistor for a measured DC link voltage.

Fig. 18 shows a feedback control diagram implementing the scheme using an adaptive drive such as that of Fig. 6a or 6b. A DC link is shown as comprising capacitor Cl coupled across both the U1/U2 and U3/U4 phase legs. A DC link voltage on the line labelled DClink' in Fig. 18 may be monitored, preferably by means of Vice.

A further refinement is to measure the load current as well as the DC link voltage and create a more complex look-up table. This is particularly useful for situations where the DC link voltage varies with load. For example in a solar converter, the DC link can be high under low load conditions (e.g. when the converter is disconnected from the grid), however under normal operating conditions the DC link operates at a lower voltage. Two separate resistors could be selected for the two cases.

Further Comments It is particularly noted that a single embodiment may implement any one or more of the techniques or circuits as discussed above under any one or more of the headings "Emulation", "Control regarding dV/dt, Clamping" and "Gate Boost".

Example advantages that may be achievable by any one or more such embodiment are, inter alia, any one or more of the following: ability to emulate various resistors in one circuit that can be controlled by software; thus multiple stages multiple stages may not be required; reduce conduction losses, preferably still protecting the device under short circuit; reduce conduction losses, e.g by improved trade-off of losses for a given dv/dt; protect motor windings from high dv/dt which causes insulation degradation; greater power throughput in a converter, e.g., by operation of a power converter at higher DC link voltage; - reduced or better compromise of switching losses through a specific profile of drive current; reduced conduction losses, e.g., by boosting the gate voltage; improved over-voltage clamp -removing the need for transorbs; emulation of turn-on and/or turn-off resistors; - reduction of product variants through the use of a building block that can be

configured in the factory or field;

- reduced cost and/or reduced board area, e.g., for a design that incorporates multiple features; constant rise/fall time (dv/dt), e.g., through ability to adapt on a cycle by cycle basis; limit over-voltage clamping, e.g., through ability to adapt on a cycle by cycle basis.

It is further noted that any embodiment of the present invention may additionally or alternatively conform to the definitions of any one or more of the arrangements as in El to E34 below: El. A power switch driver for driving a control terminal of a power switch to drive a load, the power switch driver having a negative feedback circuit to control current delivered to the control terminal, the negative feedback circuit comprising: a current output circuit comprising at least one of a current source and a current sink, the current output circuit for providing a said current of a said control terminal and configured to receive an output current control signal to control magnitude of the current provided by the current output circuit; a terminal voltage input circuit for receiving a voltage from a said control terminal and to output an indication of said voltage; an amplifier coupled to amplify the terminal voltage indication to generate an amplifier output; and a reference voltage input circuit for receiving a reference voltage, comprising at least one resistor, the reference voltage input circuit coupled to a charge supply input of the amplifier, wherein the power switch driver is configured to generate the output current control signal dependent on the amplifier output, and wherein the power switch driver is configured to reduce the current provided by the current output circuit responsive to an increase in the voltage received by the terminal voltage input circuit.

E2. Power switch driver of El, wherein the current output circuit is configured to emulate the reference voltage input circuit.

E3. Power switch driver of El or E2, wherein the at least one resistor comprises a controllable resistor.

E4. Power switch driver of any one of El to E3, wherein the terminal voltage input circuit has a coupling to the reference voltage input circuit, to effectively increase a said impedance presented to a said control terminal.

E5. Power switch driver of any one of El to E4, wherein the power switch driver has an offset voltage input circuit having an input line to receive an offset voltage and comprising a comparator to compare an indication of said voltage of the terminal voltage input circuit to the offset voltage, the offset voltage input circuit to allow a limit of variation of a said voltage from the power switch control terminal to be set by the offset voltage when the power switch driver is operated to drive a said power switch.

E6. Power switch driver of any one of El to E5, comprising a coupling switch to disable dependency of control of the amplifier on said voltage of the terminal voltage input circuit, preferably wherein the driver comprises a current detector for monitoring a current through a said load and is configured to disable said dependency when the current detector indicates a said monitored current below a threshold current, the power switch driver to provide a substantially constant said current of the current output circuit when the dependency is disabled.

E7. Power converter comprising the power switch driver of E6, the power converter comprising at least one half bridge circuit comprising a series connection of a first power switch and a second power switch, the first and second power switches configured to alternately pass current for driving a said load coupled to an output line of the half bridge circuit, each said power switch coupled in parallel with a diode, wherein the power converter comprises at least one said power switch driver to drive a respective said power switch, wherein the at least one resistor of the power switch driver comprises a controllable resistor, the power converter comprising: a turn-on detector to indicate at least a start of a turn-on period of increasing current through at least one of the power switches, wherein the power converter is configured to control the coupling switch of at least one said power switch driver based on the turn-on detector indication to allow a said dependency of control of the amplifier of the driver on said voltage of the terminal voltage input circuit of the driver during a said turn-on period.

E8. Power converter of E7, wherein the turn-on detector is configured to detect an increase in rate of change of the current through the at least one power switch and a subsequent decrease in the rate of change to indicate pendency of the turn-on period.

E9. Power converter of E7 or E8, configured to control the coupling switch of at least one said power switch driver to allow a said dependency of control of the amplifier of the driver on said voltage of the terminal voltage input circuit of the driver during a period subsequent to the turn-on period, the power converter configured to increase resistance of the controllable resistor of the driver at the start of the subsequent period.

E10. Power converter of E7 or E8, configured to control the coupling switch of at least one said power switch driver to disable said dependency of control of the amplifier of the driver on said voltage of the terminal voltage input circuit of the driver during a period subsequent to the turn-on period, the power converter to deliver a substantially constant said current of the current output circuit of the driver during the subsequent period.

Ell. Power converter of any one of E7 to E10, comprising a timing detector to indicate at least one of: a reversal of direction of rate of change of the current through the at least one power switch at a start of the subsequent period; a decrease in the rate of change of the current through the at least one power switch at the end of the subsequent period; and a voltage across the power switch below a threshold value at the end of the subsequent period, wherein the power converter is configured to perform the control of the coupling switch to control a duration of said dependency responsive to at least one said indication.

E12. Power converter comprising the power switch driver of any one of El to E6, the power converter comprising at least one half bridge circuit comprising a series connection of a first power switch and a second power switch, the first and second power switches configured to alternately pass current for driving a said load coupled to an output line of the half bridge circuit, each said power switch coupled in parallel with a commutation diode, wherein the power converter comprises at least one said power switch driver to drive a respective said power switch, wherein the at least one resistor of the power switch driver comprises a controllable resistor, the power converter comprising: a timer circuit to measure duration of at least one phase of a switching cycle of a said power switch, wherein the power converter is configured to adjust resistance of the controllable resistor in response to at least one said measured duration.

E13. Power converter for driving an inductive load comprising a winding, the power converter comprising at least one half bridge circuit comprising a series connection of a first power switch and a second power switch, the first and second power switches configured to alternately pass current for driving a said load coupled to an output line of the half bridge circuit, wherein the power converter comprises at least one power switch driver according to any one of El to E6 to drive a respective said power switch, wherein the at least one resistor of the power switch driver comprises a controllable resistor, the power converter comprising: a current detector for monitoring a current through a said load, wherein the power converter is configured to increase the resistance of the controllable resistor of at least one said driver when the current detector indicates a said monitored current below a threshold current.

E14. Power converter of E13, wherein a said power switch driver coupled to drive a said respective power switch comprises a said current detector configured to monitor a current through the respective power switch, the power switch driver configured to increase the resistance of the controllable resistor of the power switch driver when the current detector detects the monitored current below a said threshold current.

E15. Power converter of E13 or E14, configured to increase the resistance of the controllable resistor substantially in inverse proportion to the monitored current.

E16. Power converter of any one of E13 to E15, the increase of the resistance for reducing rate of change of voltage on the output line during current commutation from at least one of said first and second power switches of the half bridge circuit.

E17. Power converter of any one of E13 to E16, comprising at least two said half bridge circuits, the power converter configured for driving a said load by passing a said current through a said first power switch of a first said half bridge circuit and a second power switch of a second said half bridge circuit, the power converter configured to increase the resistance of the controllable resistor of at least one of the first power switch of the first half bridge circuit and the second power switch of the second half bridge circuit, said increase for damping a rate of change of voltage across the winding of a said load.

E18. Power converter comprising at least one power switch driver for driving a control terminal of a power switch to drive a load, the power converter comprising at least one half bridge circuit comprising a series connection of a first said power switch and a second said power switch, the first and second power switches configured to alternately pass current for driving a said load coupled to an output line of the half bridge circuit, each said power switch coupled in parallel with a diode, wherein the at least one power switch driver is configured to drive a respective said power switch and the power converter comprises: at least one clamp comparator to compare an indicator of a variable of the power switch to a clamp value, wherein the power switch driver is configured to reverse a direction of current flow between the power switch driver and the control terminal of the power switch when a said clamp comparator indicates that the power switch variable indicator exceeds the clamp value, wherein the power switch variable comprises at least one of: voltage across the power switch; rate of change of current through the power switch; and rate of change of voltage across the power switch.

E19. Power converter of E18, configured to perform said reversal when the clamp comparator indicates that the power switch variable indicator exceeds the clamp value during an OFF period of the power switch.

E20. Power converter of E18 or E19, wherein the power converter comprises a capacitive impedance coupled across the power switch, preferably wherein the capacitive impedance comprises a potential divider having impedances in series across the power switch, a coupling of said series impedances configured to provide the indicator of voltage across the power switch, wherein each said series impedance comprises a capacitance.

E21. Power converter of any one of El 8 to E20, wherein the power switch driver is as defined in any one of El to E6.

E22. Power converter of any one of E18 to E21, wherein the power converter comprises: at least one limit comparator to compare an indicator of a variable of a said power switch to a limit value, wherein the power switch driver is configured to, during each of a series of on-off switching cycles of the power switch,: reduce a circuit variable if a said limit comparator indicates that the power switch variable indicator remains less than the limit value during an OFF period of the power switch; and increase the circuit variable if a said comparator indicates that the power switch variable indicator exceeds the limit value during an OFF period of the power switch, wherein the circuit variable comprises at least one of: a controllable output resistance of the power switch driver; and current to a control terminal of the power switch, and wherein the power switch variable comprises at least one of voltage across the power switch; rate of change of current through the power switch; and rate of change of voltage across the power switch.

E23. Power converter of E22, wherein the circuit variable comprises the controllable output resistance and the power switch driver comprises an output stage comprising a series connection of a control switch and a controllable resistor having the controllable output resistance, the series connection for bleeding a current of a said control terminal, a said current for turning a said power switch off.

E24. Power converter of E22, wherein the power switch driver is according to any one of El to E6, wherein the circuit variable comprises the controllable output resistance and the power switch driver is configured to adjust resistance of the at least one resistor to perform at least one of said increase and decrease of the circuit variable.

E25. Power converter of E22, wherein the power switch driver is according to any one of El to E6, wherein the current to the control terminal is the current provided by the output circuit.

E26. Power converter of any one of E18 to E25, the power converter having at least two phase legs and a DC link coupled across each of the phase legs to have a voltage in common to the phase legs, wherein the power switch driver comprises: an output stage providing a controllable output resistance, the output stage for conducting a current of a said control terminal, a said current for turning a said power switch off; a feedback line to receive an indicator of a said voltage in common; and a drive stage controller coupled to the feedback line and configured to control the controllable output resistance based on a said voltage indicator received on the feedback line.

E27. Power converter of E26, wherein the drive stage controller is configured to increase the controllable output resistance when the voltage indicator indicates an increase in said voltage in common.

E28. Power converterof E26 or E27, wherein the drive stage controller is configured to increase the controllable output resistance when the voltage indicator indicates a said voltage in common above a threshold link voltage value.

E29. Power converterof any one of E26 to E28, comprising a central controller for controlling a plurality of power switch drivers, the central controller comprising the drive stage controller.

E30. Power converter of any one of E26 to E29, wherein the output stage comprises a series connection of a control switch and a controllable resistor having the controllable output resistance.

E31. Power converter of any one of E26 to E29, wherein the power switch driver is according to any one of El to E6, the output stage comprising the current output circuit, wherein the power switch driver is configured to adjust resistance of the at least one resistor to perform the control of the controllable output resistance.

E32. Power converter of any one of E26 to E31, the power converter comprising the DC link.

E33. A power converter comprising the power switch driver of any one of El to E6, the power converter preferably further according to any one of claims 7 to 32.

E34. Power switch driver of any one of El to E6 or Power converter of any one of E7 to E33, wherein the power switch comprises one of an IGBT, MOSFET, HEMT or JFET, the power switch preferably comprising silicon carbide, gallium nitride and/or silicon.

No doubt many other effective alternatives will occur to the skilled person based on reading the above. For example, during each phase (1-10) of an IGBT switching waveform (Fig. 12) different drive mechanisms can be employed to optimise behaviour. In some circumstances a voltage source with resistance to set the drive current is optimal, at other times a current source is preferable, and at others it is better for the gate to be held at a specific voltage. An adaptive drive such as that of Figs. 6 or 8 may fulfil these three tasks in one optimal circuit design. In an embodiment, the drive profile may be fixed or changed during operation, either within a single cycle, from cycle to cycle due to change in load conditions, or over the long term due to parameter variance (e.g. degradation due to ageing).

It will be understood that the invention is not limited to the described embodiments and encompasses modifications apparent to those skilled in the art lying within the spirit and scope of the claims appended hereto.

Claims

CLAIMS: 1. A power switch driver for driving a control terminal of a power switch to drive a load, the power switch driver comprising: a controllable voltage source to provide a control terminal reference voltage; a voltage control circuit for controlling voltage on a said control terminal of a said power switch according to the control terminal reference voltage, the voltage control circuit configured to provide an output signal to vary the voltage on the control terminal; and a feedback circuit to generate a signal indicating a rate of change of at least one of a current or voltage of a said power switch and to, in response to said signal indicating a reduction of impedance of an output circuit of the power switch driver, control the controllable voltage source to reduce the control terminal reference voltage, said reduction to reduce the controlled voltage.
2. Power switch driver of claim 1, wherein the voltage control circuit comprises a gate voltage feedback circuit configured to control an output stage of the power switch driver dependent on the control terminal reference voltage and an indicator of voltage on a said control terminal, the output stage configured to control the reduction of controlled voltage according to an output of the gate voltage feedback circuit.
3. Power switch driver of claim 1 or 2, comprising: an input line to receive a turn-on signal to instruct turn-on of the power switch, wherein: the voltage control circuit is configured to, in response to a said turn-on signal, raise the voltage on the control terminal to a boost voltage; and said reduction of the controlled voltage is a reduction from the boost voltage.
4. Power switch driver of any preceding claim, wherein the feedback circuit comprises a comparator to receive the signal indicating a said rate of change and to compare the received signal to a threshold, the comparator configured to output a result of a said comparison to provide the indication of reduction of impedance.
5. Power switch driver of any one of claims 1 to 4, wherein the voltage control circuit is configured to, in response to the turn-on signal, control the output signal to generate a first voltage on the control terminal of a said power switch, the voltage control circuit configured to further control the output signal for generating the second, boost voltage on the control terminal of the power switch at a time delay after the response to the turn-on signal.
6. Power switch driver of any one of claims 1 to 5, wherein the first voltage is for turning a said power switch on.
7. Power switch driver of claim 6, wherein the reduced control terminal reference voltage below the boost voltage is the first voltage, more preferably below the first voltage.
8. Power switch driver of any one of claims 1 to 7, wherein the reduced control terminal reference voltage is to maintain the power switch on.
9. Power switch driver of any one of claims 1 to 8, wherein the feedback circuit is configured to, at a time delay after the control to reduce the control terminal reference voltage, control the controllable voltage source to reduce the control terminal reference voltage to turn a said power switch off.
10. Power switch driver of any one of claims 1 to 9, the power switch driver having a negative feedback circuit to control current delivered to the control terminal, the negative feedback circuit comprising: a current output circuit comprising at least one of a current source and a current sink, the current output circuit for providing a said current of a said control terminal and configured to receive an output current control signal to control magnitude of the current provided by the current output circuit; a terminal voltage input circuit for receiving a voltage from a said control terminal and to output an indication of said voltage; an amplifier coupled to amplify the terminal voltage indication to generate an amplifier output; and a reference voltage input circuit for receiving a reference voltage, comprising at least one resistor, the reference voltage input circuit coupled to a charge supply input of the amplifier, wherein the power switch driver is configured to generate the output current control signal dependent on the amplifier output, and wherein the power switch driver is configured to reduce the current provided by the current output circuit responsive to an increase in the voltage received by the terminal voltage input circuit.
11. Power switch driver of claim 10, wherein the current output circuit is configured to emulate the reference voltage input circuit.
12. Power switch driver of claim 10 or 11, comprising: a coupling switch to disable dependency of control of the amplifier on said terminal voltage input circuit.
13. Power switch driver of any one of claims 10 to 12, comprising: a coupling switch to enable dependency of control of the amplifier on the control terminal reference voltage.
14. Power switch driver of any one of claims 1 to 13, configured to monitor voltage across an inductance to provide the signal indicating a said rate of change of current of a said power switch.
15. Power switch driver of any one of claims 1 to 14, wherein the power switch comprises one of an IGBT, MOSFET, HEMT or JFET, the power switch preferably comprising silicon carbide, gallium nitride and/or silicon.
16. Power switch driver of any one of claims 1 to 15, comprising the power switch.
17. Power converter comprising the power switch driver of claim 16.
18. Method for controlling a drive signal to a control terminal of a power switch to drive a load, comprising: in response to a turn-on signal, controlling the drive signal to generate a boost voltage on the control terminal, the boost voltage to turn the power switch on; when the voltage on the control terminal is the boost voltage, monitoring at least one of current and voltage of the power switch to detect a reduction in impedance of an output circuit comprising the power switch; and reducing the voltage on the control terminal below the boost voltage when the monitored current or voltage indicates said reduction of impedance.
19. Method of claim 18, wherein the controlling the drive signal to generate the boost voltage comprises: in response to the turn-on signal, controlling the drive signal to generate a first voltage on the control terminal, the first voltage to turn the power switch on; and at a time delay after said turn-on signal, further controlling said drive signal to generate a second voltage on the control terminal, wherein the second voltage is the boost voltage, said further controlling to turn the device on to a lower loss state.
20. Method of claim 18 or 19, wherein said time delay expires when a voltage across the power switch falls below a threshold value.
21. Method of any one of claims 18 to 20, wherein the reducing the voltage below the boost voltage comprises reducing the voltage to the first voltage.
22. Method of any one of claims 18 to 21, comprising turning the power switch off at a time delay after said reducing the voltage on the control terminal below the boost voltage, preferably wherein said time delay is a preset time delay, alternatively preferably wherein expiry of the time delay is determined by comparison of a threshold value to at least one of a voltage signal and current signal of the power switch.
23. Method of any one of claims 18 to 22, wherein the monitoring comprises monitoring rate of change of current through the power switch.
24. Method of any one of claims 18 to 23, comprising comparing the monitored rate of change of current to a threshold value to provide the indication of reduction of impedance.
25. Method of any one of claims 18 to 24, wherein the monitoring is to detect a short-circuit condition of a said output circuit comprising the power switch and a load coupled to an output of the power switch.
26. A power converter or power switch driver as described herein, preferably as described and illustrated herein.