GB2494522A - Array substrate for fringe field switching mode liquid crystal display device and method of fabricating the same - Google Patents

Abstract

A fringe field switching (FFS) mode LCD device and method for fabricating the same are discussed, whereby the device includes a gate line 103 formed In one direction on a surface of a first substrate 101; a data line113a formed on the first substrate and crossed with the gate line to thereby define a pixel region; a thin-film transistor T formed on the first substrate and formed at an intersection of the gate line and the data line; an insulating layer 107 having an opening portion121 located at an upper portion of the thin-film transistor to expose at least a gate portion of the thin-film transistor; a pixel electrode 123a formed at an upper portion of the insulating layer, and connected to the drain 113c of the exposed thin-film transistor; a passivation layer 127 formed at the upper portion of the insulating layer; and a plurality of common electrodes133a formed at an upper portion of the passivation layer and separated from one another. This arrangement allows the size of the black matrix to be reduced from A1 to A2 which provides an increase in the transmittance of the pixel.

Description

ARRAY SUBSTRATE FOR FRINGE FIELD SWITCHING MODE LIQUID

CRYSTAL DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME

BACKGROUND OF THE INVENIflON

1. Field of the invention

[9001] Embodiments of the invention r&ate to a liquid crystal display device., and. more p?ricularly, to an array substrate for a fringe field switchiri.g (FFS) mode liquid crystal display device and method for fabricating the same.

2 Descripflon of the related art [0002] In general, the driving principle of a liquid crystal display device is based on optical anisotropy and polarization of liquid crystals. Liquid crystals having an elongated structuie exhibit directivity in molecular arrangement, and thus, the direction of their molecular arrangement can be controlled by artificially

applying an electric field to liquid crystals.

[0003) Accordingly, if the molecular arrangement direction of liquid crystals is arbitrarily controlled, then the molecular arrangement of liquid crystals may be changed, and light is refracted in the molecular arrangement direction of liquid crystals by optical anisotropy tQ exhibit image information [00041 At present1 an active matrix liquid crystal display device (AM-LCD; hereinafter, abbreviated as a "liquid crystal display device") in which thin-film transistors and pixel electrodes connected to the thin-film transistors are arranged in a matrix form have been widely used due to its resolution and video implementation capability.

[0005] The liquid crystal display device may include a color fiRer substrate (i.e., an upper substrate) formed with common electrodes, an array substrate (i.e., a lower substrate) formed with pixel electrodes, and liquid crystals filled between the upper and lower substrates, in which liquid crystals are driven by an electric field applied in the vertical direction between the common electrode and pixel electrode, thereby having excellent transmittanceand aperture ratio.

[0006] However, the driving of liquid crystals by an electric field applied in the vertical direction has a drawback of provithng insufficient viewing angle characteristics, Accordingly, a driving method of liquid crystals by in-plane switching has been newly proposed to overcome the foregoing drawback, and the driving method of liquid crystals by in-plane switching has excellent viewing angle characteristics.

[0007] Such an in-plane switching mode liquid crystal dispay device may include a color filter substrate and an array substrate facing each other, and a liquid crystal layer is interposed between the co'or filter substrate and the array substrate.

[0008] A thin4ilm transistor, a common electrode and pixel electrode are provided for a plurality of pixels, respectively, defined on a transparent insulating substrate on the array substrate.

[0009] Furthermore, the common electrode and pixel electrode are configured to be separated from each other in parallel on the same substrate, (0010] In addition, the color filter substrate may include a black matrix at a portion corresponding to a gate line, data line, and a thin-film transistor on a transparent insulating substrate, and a color filter corresponding to the pixel.

[0011] Moreover, the liquid crystal layer is driven by a horizontal electric field between the common electrode and pixel electrode.

[0012] In this instance, the common electrode and pixel electrode are formed with a transparent electrode to secure brightness.

(0013] Accordingly, a fringe field switching (FFS) technique has been proposed to maximize the trightness enhancement effect. The. FF8 technique aflows liquid crystals to be controlled in a precise manner, thereby obtaIning high.

contrast ratio with no color shift (0014] A method of fabricating a fringe field switching (FFS) rtode liquid crystal display device according to the related art will be described with reference to FIGS. 1 through 3.

(0015] FIG. us a schematic plane view illustrating a fringe field switching (FFS) mode liquid crystal display device according to a related art. FIG. 2 is an enlarged plane view illustratin.g a portion "A" of FIG. 1, and schematically illustrates a black matrix (SM) for c. overing a drain contact hole portion by taking a bonding margin into cosideçation. FIG. a is a. schematic crosssectional view along line 111111 of FIG. 1, and Fliustrates a fringe field switching (FF8) mode liquid crystal display device..

[0016] An array substrate for a fringe field switching (FF5) mode1"quid crystal display device according to the related art may include a plurality of gate lines 13 extended in one direction on a transparent insulating substrate ii to be separated from one another in parallel; a plurality of data lines 21 crossed with the gate lines 13 to define pixel regions in the crossed areas: a thin-film transistor (T) provided at an intersection o the gate line 13 and the data line 21, and made of a gate electrode 13a extended from the gate line 13 in the vertical direction, a gate insulating layer 15, an active layer 17, a source electrode 23 and a drain electrode 25; a photo acryl layer 29 formed on a front surface of the substrate including the thin-film transistor (T); a common electrode 33 having a large area formed on the photo acryl layer 29; a passivation layer 35 formed on the photo acryl layer 29 in.duding the common electrode 33 to expose the drain electrode 25; and a plurality of pixel electrodes 37 formed on the passivaUon layer 35 to be electrical'iy connected to the drain electrode 25, as illustrated in FIGS. 1 through 3.

(0017] In this instance, a common electrode 33 having a large area is disposed on a front surface of the pixel region with a space separated from the gate line 13 and the data line 21.

(0018] Furthermore, a plurality of rod-shaped pixel electrode.s 37 are disposed art the common electrode 33 by interposing the passivation layer 35 therebetween, In this instance, the common electrode 33 and the plurality of pixel electrodes 37 are formed of indium Tin Oxide (ITO) which is a transparent conductive materiaL [0019] In addition, the pixel electrode 37 is electrically connected to the drain electrode 25 through a drain contact hole 3 formed On the photo acryl layer (0020] Moreover, as shown in FIGS. 2 and 3, a colcr filter layer 41 and a black matrix 43 disposed between the color filter layers 45 to block the transmission of light are deposited on a color filter substrate 41 separated from and bonded to the insulating substrate 11 formed with the common electrode 33 and a plurality of pixel electrodes 37, In this instance, as illustrated in FIG. I the black matrix 43 may be formed on the color filter substrate 41 corresponding to a portion of the drain contact hole 1 including the gate line 13 and the data line 21.

(0021] Furthermore. as shown in HG 3. a Uquid crystal layer 51: may be formed between the color ifiter substrate 41 and the insulating substrate 11 bonded to each other.

[0022] As described above, in the related art; a photo acryl layer may be used to redube a parasitic. capacitance.

[0023] However, a drain contact hole 31 shoUld be formed to connect a pix& electrode 37 and a drain electrode 25 of the thin-fun transistor Tto the photo acryl layer, and a liquid crystal disclination region hole is created at the circumference of the drain contact hole 31 during the formation of the drain contact hole 31, thereby causing light leakage.

(0024] Accordingly, in the related art, in order to prevent light leakage caused by creating a liquid crystal disclination region at the circumference of the drain, contact hole 31, all circumference portion of the drain contact hole 31 should be covered by using a black matrix 43 and thus, an opening region thereof, namely, an area of the transmission region, may be reduced, thereby decr easing the transmittance of a pixel. in particular, as illustrated in FIG. 2, a part of an open region including the drain contact hole 31 should be covered with a black matrix 43 by taking a bonding margin into consideration as much as an area (Al) to prevent light leakage caused by a thsclination region of liquid crystals created by the drain contact hole 3i as Ulustrated in FIG. 2, and thus, the transmission region of a pixel may be reduced as much as the distance, thereby decreasing the transmittance to an extent.

MMARY OF THE INVENTION

[00251 The invention is provided to enhance the foregoing problems, and seeks to provide a fringe field switching (FF8) mode liquid crystal display device capabl& of maimizing an opening region of the pixel without separately forming a drain contact hole fof contacting a drain electrode to increase transmittance, and methodfor fabricating the same..

[0026] Seekrng to accomplish the foregotng, there is provtded an array substrate for a fringe field switching (FF8) mode liquid crystal display device, and the array substrate may include a gate line formed in one direction on a surface of the substrate; a data line crossed with the gate line to thereby define a pixel region; a thin-film transistor formed at an intersection of the gate line and the data line; an insulating layer having an opening portion located at an upper portion of the thin-film transistor to expose at least a gate portion of the thin-film transistor; a pixel electrode formed at an upper portion of the insulating layer and directly connected to the exposed thin-film transistor; a passivation layer formed at the up per portion of the insulating layer including the pixel electrode; and a plurality of common electrodes formed at an upper portion of the passivation layer and separated from. one another.

[0027] Seeking to accomplish the foregoingr there is provided a method of fabricating an array substrate. for a fringe field switching (FF8) AH-IPS mode liquid crystal display device, and the method may include forming a gate line in one direction on a surface of the substrate; forming a data line crossed with the gate line to thereby define a pixel region, and a thin-film transistor at an intersection of the gate line and the data line on the first substrate; forming an insulating layer having an opening portion located at an upper portion of the thin-film transistor to

C

expose at least a gate portion of the thin-film transistor: forming a pixel electrode connected to the exposed thin-film transistor at an upper portion of the insulating layer ahd forming a passivation layer at the upper pQrtlon of the insulating layer including the pixel electrode; and forming a plurélity of common electrodes separated from one another at an upper portion of the passivation layer.

(0028] Seeking to acconipllsh the foregoing, there is provided an array substrate for a fringe field switching (FFS) mode liquid crystal display device7 and the array substrate may include a gate line formed in one direction on a surface of the substrate; a data line crossed with the gate line to thereby define a pixel region; *a thin-film transistor formed at an intersection of the gate line and the data line; an insulating layer having an opening portion located at an upper portion of the thinfilm transistor to expose a source electrode and a gate portion of the thin-film transistor; a pixel electrode formed at an upper porUon of the insulating layer, and directly connected to the exposed thin-film transistor: a passivalion Faer formed at the upper portion of the insulating layer including the pixel electrode; and a plurality of common electrodes formed at an upper portion of the passivation layS and separated from one another.

[0029] A.n array substrate for a fringe field switching (FES) mode llquid crystal display device and method for fabricating the same in accordance with an embodiment of the invention may have the following effects.

(0030] According to an array substrate for a fringe field switching (FFS) mode liquid crystal display device and method for fabricating the same in accordance with an embodiment of the invention, a drain contact hole in a related art that has been formed to electrically connect a drain electrode to a pixel electrode is removed, and an opening portion for exposing an upper portion of the thin-film transistor is formed on an organic insulating layer such that the exposed thin4ilm transistor and the pixel electrode are electrically connected to each other in a direct manner and thus an area that has been used to form a drain contact hole in the related art, that is an area covered by the black matrix, can be used as an opening area to remove a drain contact hole formation portion in the related art that has been a cause Qf transmittance reducflon, thereby enhancing transmittance by more than about 20 percent compared to the relsied art.

[0031] Furthermore, according to embodiments of the invention, a photosensitive photo acryl layer used to reduce a parasi& capacitance in the related art can be used as is, thereby reducing power consumptlon

BRIEF DESCRIPTION OF THE DRAWiNGS

(00321 The accompanying drawings, which are included tQ provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

[0033] In the drawings: [0034] FIG. 1 is a schematic plane view illustrating a fringe field switching (FFS) mode liquid crystal display device according to a related art; [0035] HG. 2 is an enlarged plane view illustrating a portion "A' of FiG. 1 and schematically illustrates a black matrix (BM) for covering a drain contact hole portion and the drain contact hole portion by taking a bonding margin into consideration; [0036] FIG. 3 is a schematic cros&sectionaf view along line 111111 of FIG. 1, and illustrates.a fringe field switching (FF5) mode liquid crystal display device;

S

[0037] FIG. 4 is a schematic plane view Hiustrattng a fringe field switching (FF8) mode liquid crgstal display device according to an embodiment of the invention; [0038] FIG. 5 is a schematic cross-sectional view along line V-V of FIG. 4..

and illustrates an AH-IPS mode liquid crystal dispiay device accorthng to an embodiment of the invention; (0039] FiGS. 6A through.0 are fabrication process cross-sectional views illustrating an array substrate for a fringe field switching (FF8) mode liquid crystal display device according to an embodiment of the inventiori (0040] FIG. 7 is a. schematic cross-sectional view illustrating a fringe field switching (FF5) mode liquid crystal display device according to another embodiment of the invention; and [0041] FIGS. 8A through 80 are fabrication process cross-sectional, views illustrating an array substrate fora fringe field switching (FF5) mode liquid crystal display device according to another embodiment of the invention.

DETAILED DESCRPT ROF THE EMBODIMENTS

[0042] Hereinafter. an array substrate for a fringe field switching (FF8) mode liqwd crystal display device and method for tabiicatirg the same according to example embodiments of the invention will be described in detail with reference to the accompanying drawings.

[0043] FIG. 4 is a schematic plane view illustrating a fringe field switching (FF8) mode liquid crystal display device accoiding to an embodiment of the invention.

[0044] FIG. 5 is a schematic cross-sectional view illustrating a fringe field switching (FF5) mode liquid crystal display device according to an embodiment of the invention, as a cross-sectional view along the The V-V of FIG 4.

[0045] A fringe field switching (FFS) mode liquid crystal display device accordi® to an embodiment of the invention, as illustrated in FIGS. 4 and 5, may include a gate line 103 formed in one direction on a surface of the insulating substrate 101; a data line liSa crossed with the gate line 103 to define a. pixel region; a thin-film transistor (1) formed at an intersection of the gate line 103 and the data ne 113a; an organic insulating layer 117 having an opening portion 121 located at an upper portion of the thin-film transistcr (T) to expose the thin-film transistor (1); a pixel electrode. 123a formed at an upper portion of the organic insulating layer 117, and directly connected to the exposed thin-film transistor (I); a passivation layer 127 formed at an upper portion of the organic insulating layer 117 including the pixel electrode 123a; and a plurality of common electrodes 133a formed at an upper portion of the passivation layer 127 and separated from one another.

[0046] In this instance, a pixel electrode 123a having a large area is disposed on a front surface of the pixel region with a space separated from the gate. line and the data line liSa, and a plurality of transparent rod-shaped common electrodes 133a are disposed to be. separated from one another by a predetermined distance at an upper side of the pixel electrode 123a by interposing the passivation layer 127 therebétween.

[0047] Furthermore, as illustrated in FIG. 5, the pixel electrode 123a is electrically connected to a drain electrode 113c in a direct manner through an opening portion 121 located at an upper pcrtion of the thin-film transistor [F) without having a separate drain contact hole. In this instance, the opening portion 121 is formed to expose a channel region (refer to reference numeral 109a in FIG. 6J) and a portion of the drain electrode 113c of the thin-film transistor (T), j0048] On the other hand, red, green and blue color filter layers 145 and a black matrix 143 disposed between the. color fiRer layers 145 tO block the transmission of light are deposited on a colOr filter substrate 141 separated from and bonded to the insulating substrate 101 formed with the pixel electrode 123a and a pluraRty of common electrodes 133a, [0049] In this instance, as illustrated in FIGa 4 and 5, a portion covered by the black matrix 143 may be covered by as much as the opening portion 121 at an upper portion of the thin-film transistor T) by taking a bonding margin to the insulating substrate 101 into consideration, [0050] In this instance, the black matrix 143 covers an upper portion of the thin-film transistor (1), but the black matrix 43 in the related art should cover up to an upper portion of the drain contact hole region formed at an upper portion of the drain electrode 25 protruded from the gate line 13 as well as an upper portion of the *thin$Hm transistor (T) as illustrated in FIG, I by as much as an. area (Al), and thus, the opening region may be reduced to an e xtent in the related art.

[0051] However, in an embodiment of the invention, as illustrated in FIG. 4, a drain contact hole formation region in the related art is removed, since the black matrix 143 merely covers only an area A2, so that a part area (AS) of the removed drain contact hole formation region is used as an opening area to secure a region that has been covered by the black matrix 143 as an opening area, thereby enhancing the transmittance of a pixel.

[0052] Furthermore, as iIlutrated ri FiG. 5, a cohjmn spacer 147 for maintaining a ceH gap with respect to the insulating substrate 101 is protruded at an upØer portion of the red, green and blue color filter layers 145 to be inserted into the opening portion 121 formed at an upper portion of the thin-film transistor (1) formed on the insulating substrate 101.

[0053] ln addition, a liquid crystal layer 151 is formed between the color filter substrate 141 and the insulatin9 substrate 101 bonded to each other to configure a fringe field switching (FF5) mode liquid crystal display device according to an embodiment of the invention.

[00541 Through the foregoing configuration, the plurality of common electrodes 133a supply a reference voltage for driving liquid crystals. namely, a common voltage, to each pixel.

[0055] The plurality of common electrodes 133a are overlapped with the pixel elecUode 123a having a large area by interposing the passivation layer 127 therebetween at each pixel region to form a fringe field.

[0056] In this manner, if a data signal is supplied to the pixel electrode 123a through the thin4uni transistor CT), then the common electrode 133a supplied by a common voltage forms a ifinge field so that liquid crystal molecules aligned in a horizontal direction between the insulating substrate 101 and the color filter substrate 141 are rotated by dielectric anisotropy, and thus, the light transmittance of liquid crystal molecules passing through a pixel region varies according to the rotational degree, thereby implementing gradation.

[0057] Accordingly, according to a fringe field switching (FFS) mode liquid crystal display device having the foregoing configuration in accordance with an embodiment of the invention, a photosensitive photo acryl layer used to reduce a parasitic capacitance in the related art can be used as is, thereby reducing power consumption.

[0058] Fufthern,o,e, acoording to an embodiment of the invention a draIn contact hole In the related art that has been formed to electrIcally cOit ct a drain electrode to a pixel electrode is removed, and an Opening pottio, for exposing an Upper portion o the thln-Thm trnnsistor Is formed on wi organic nsjlatin layer such that the exposed SlUm: transistor aM the pixel electrode aie.eleqtE1vJly connected toeach other in a dfre& manner, abd thus, a; part area A3ofaa area Al thas been used to fonnadrakicOntact hole flif related art cap bt used as an opening area to remove a drain contact hole formation portion in, the related art.

that has been a cause of transmittance reØuction, thereby enhancing transmittance by more than about 20 percent compared to the related art.

[0059] On the other hand, a method of fabricating an array substrate lbr a frmflg: field switching (FF8) mode liquid crystal 4ipIiycdevice having the ftragbFg configuration according to an ernb ent ofthe invention Will be descibedbeiqw with referencet Flea $AJbrough6Q 100601 FiGS. 6A through 60 are tabticatian Pttce: cross-sactionat views illustrating an array subétrate ibr a fringe fleSswihing <FF8) mode iiq4d crystal display, device according ten embodiment Of-the inv*jitio.

[0001] As illustrated in Pie. 6A, a plurality ef pixel regions including a switching function are define on a ttansparent insuLatp,g substrate 1 l, arid a flrst conductive metal layer 102 Is deposited or the tjisparept insulating substrate 101 by a sputtering method, In this Instance, at least one selected from the group consisting of alumInium $1),, igsten (W), copper (Cu), molybdenuth (Mo)! chiroitlum (C!), titanium (fl), fn*l$uPgsten (Mot&), may itniurn (MOTI), ooppex/ moly-titanium CuJMoTi) may be used for a target material for forming the first conductive metal layer 102.

[0062] Next, a photoresist having a high transmittance is deposited at an upper portion of the first conductive metal layer 102 to form a first photosensitive layer 105.

(0063] Subsequently as illustrated in FIG. 66, n exposure process is carried out on the first photosensitive layer 105 through a photolithography process technology using an exposure mask, and then the first photosensitive layer 105 is selectively removed through a development process to form a first photosensitive pattern 105a, [0064] Next, as illustrated in FIG. 60, the first conductive metal layer 102 is selectively etched by using the first photosensitive pattern 1 05a as a blocking layer to form a gate line 103 (refer to FIG. 4), a gate electrode 103a extended from the gate line 103, and a common line separated from and in parallel with the gate inc 103 at the same time. Further, the first photosensitive pattern lOSa is removed, and then a gate insulating layer 107 made of silicon nitride (SiNx) or sificon oxide SiO2) is formed at a front surface. of the Substrate 101 including the gate electrode 1 03a.

[0065] Next1 amorphous silicon, layer a-Si:H) 109 and amorphous siEcon layer (n+ or p+) 111 containing impurities are sequentiafly deposited on the gate insulating layer 107, Al this time, the amorphous silicon layer (aSJ:H) 109 and amorphous silicon layer (n+ or p+) 111 containing impurities are deposited using a Chemical Vapour Deposition (OVO) method. At this time, an oxide-based material layer such as indium gallium zinc oxide (1Gb) instead of amorphous silicon layer (a-Si:H) 109 may be formed on the gate insulating layer 107 and applied to an oxide thin4ilm transistor.

[0066] Subsequently, a second conductive layer 113 is deposited at a front surface of the substrate including the amorphous silicon layer (n+ or p+) 111 containing impurities using a sputtering method. At this time, the second conductive layer 113 may be a single layer or a multi-layer, and iPclude at least one s&ected from the group consisting of aluminium (Al), tungsten (W): copper (Cu, molybdenum (Mo), indium tin oxide (ITO), CuIITO, chromium (Crj, titanium (Ti), moly-tungsten (MoW, moly-titanium (MoD), copper! rnoly-tftanium (Cu/Mom may be used for a target material for forming the second conductive mei,F layer 113.

(0067] Subsequently, a photoresist having a high transmittance is deposited at an. upper portion of the second conductive layer 113 to form a second photosensitive layer.

(0068] Next, an exposure process is carried out on the second photosensitive layer through a photolithography process technology using an exposure mask, and then the second photosenitive layer is selectively removed through a development process to form a second photosensitive pattern 115, 10069] Subsequently as iliusfrate.d in FIG. 6E, the second conductive layer 113 is s&ectively wet.etched by using the second phOtosensitive pattern 115 as an etching mask to define a source electrode and drain electrode formation region together with the data line liSa crossed with the gate line 103 in a vertical direction (or with a vertical separation).

(0070] Next, as illustrated in FIG. 6F, a portion of the conductive layer 113 corresponding to the source electrode, and drain electrode formation region and the amorphous silicon layer (n÷ or p4) 111 containing impurities and amorphous silicon layer (aSi:H) 109 below the data line il3a are sequentially etched through a dry etching process to form an ohmic contact layer lila and an active layer 10a. At this time, a portion of the conductive leyer 113 corresponding to the source electrode and dram electrode formation region and the amorphous sihcon layer (n+ or p+) 111 containing impurities and amorphous siljcon layer (a-Si:K) 109 below the data line 113a are patterned at the same fime, and thus, an active tail will not occur [0071] Subsequently1 the second photosensitive pattern 115 is removed, and, then an inorganic insulating layer or organic insulating layer 117 is deposited at a front surface of the substrte including the active layer 109a and ohmic contact layer lila, a portion of the conductive layer 113 corresponding to the source electrode and drain electrode formation region and the data Fine ll3a. At this lime, a photo acryl material or Other photosensitive organic insulating materials exhthiting photosensWvfty may be Used for the organic insulating layer 117. Furthermore, since the photo acryl exhibits photosensitivity, an exposure process can be carried out without forming a, separate photoresist during the exposure process. Furthermore, any one selected from silicon nitride (SiNx and other inorganic, insulating materials my be used for th,e inorganic insulating layer.

[0072] Next, as illustrated in FJG. 6G, an exposure Ø'rocess is carried out on the organic insulating layer 117 through a photQUthography process technotogy using an exposure mask, and then the organic insulating layer 117 is selectively removed through a development process to form an opening portion 121 for exposing an upper portion (or a part thereof) of the conductive layer 113 corresponding to the source electrode and drain electrode formation region. At this time, the opening portion 121 is formed at a portion of the thin..film transistor (T), namely, a source electrode and drain electrode formation region. Furthermore a sidewall of the ohmic contact layer lila and active layer lOGs including an upper portion of the conductive layer 113 corresponding to the source electrode and drain electrode formation region and a partial upper surface of the gate insulating layer 101 are exposed by the opening pothon 121. The opening portion 121 exposeS an upper portion of at least a gate portion above the gate electrode 1 OSa.

[0073] Subsequently, as. illustrated in FIG. SF1, a transparent conductive material is deposited at an upper portion of the organic insulating layer 117 including the opening portion 121 using a sputtering method to form a. first transparent conductive material layer 123. At this time, any one composition target selected from a transparent conductive material group including Indium Tin Oxide (ITO), Indium Zinc Oxide (lZO), and the like is used for the transparent conductive material. Furthermore, the first transparent conductive material layer 123 is directly brought into contact with a surface of the conductive layer 113 corresponding to the source electrode and drain electrode formation region and a side wall of the ohmic ccntadt layer lila and active layer tOGa.

[0074] Next a photoresst having a high transmittance is deposited at an upper portion Of the first transparent conductive material layer 123 to form a third photosensitive layer.

[0075] Subsequently, an exposure process is carried out on the third photosensitive layer through a photolithography process technology using an exposure mask, and then the third photosensitive layer is selectively removed through a development process to form a third photosensitive pattern 125. At this time, the third photosensitive pattern 125 exposes a portion of the conductive layer 1*3 fOr the source electrode and drain electrode formatIon corresponding to a channel region of the active layer 109a.

(0076] Next, as illustrated in FIG. 81, t,,,,, first transparent conductive mateilal layer 123 is selectively etched by using the third photosensitive pattern an etdhing mask to form a pixel electrgde W electrically tOflflectedt to the. drafr, tfr*d 113c Jn a ted manna, together with tie source electrode flab and tin ele trodóil3c at the same bme Al This time, the pixel eletroØa 1231 is direcijy brought jiito pontact with a side wall at the ohmic contact layer ills and adjve layer lOBa togH r with the drain Seottoøe DiSc Through tPe opening portion 121.. Furthermore,, a portion, ot the ohmic contact layer 111a between the source electrode 1'lSb and drain eettrode uSc is also exposed' during the formation of the, soirce electrode llSb and drain electrode 113c. Then, a dummy transparent conductive layer pattern 123b' Is formed at a side wall of the opening portion 121 induding' the source elect,. 113b, Accordingly, the pen1flg potion 121 expt''s the: upper portions of' a portion of' S. so,wte electrode 113b, the gats portiOn: above the gate *dtrct 1O31 the active layer 104t corresponding tb a thannel region'; and the drain electrode I 13o.

SMbsejuent1y, ,as illustrated in FIG 64., a po#lan Of The exposeø ohrni di"fltebt': layer 1a Is sefaØ, ,, Iy etched' th e$pOSe a ohaMel' region of the active layIr I'09a, (00711 Next, as Wustrated in FIG. 6K, the thfrd photosensitive pattern, 125.. is removed, and,'then an inorganiq Insulating material, at Organic insulating matérial is deposited at a front surface of the substrate including the source electrode 113b, drain eJectrode 113c and pixel electrode 123ato fbffii a'passivation layer'j27,. 18'

[0079] Subsequently, as illustrated in FIG. 6L, a transparent conductive material is deposited at an upper portion of the passivation layer 127 using a sputtering method to form a second transparent conductive material layer 133. At this time, any one composition target selected from a transparent conductive material group including indium Tin Oxide (ITO), indium Zinc Oxide (170), and the like is used for the sccnd transparent conductive material 133.

(0080] Next, a photoresist having a high transmittance is deposited at an upper portion of the second transparent conductive material layer 133 to form a fourth photosensitive layer 135, (0081] Subsequently as illustrated in FIG. EM, an exposure process is carried out on the fourth photosensitive layer 135 through a photolithography process technology using an exposure mask, and then the fourth photosensitive layer 1.35 is selectively removed through a development process to form a fourth photosensitive paffern 135a.

[0082j Next, as illustrated fti FIG. 6N, the second transparent conductive material layer 133 is selectively etched by using the fourth photosensitive pattern 1 35a as an etching mask to form a p.lvrality of common electrodes I 33a separated from one another while being overlapped with the pixel electrode 123a [0083] Next the remaining fourth photosensitive pattern 135a is removed to complete the process of fabtating an array substrate for fringe field switching (FF8) mode liquid crystal display device according to an embodiment of the invention.

[0084] Then, as illustrated in FIG. 60, a black matrix layer 143 for blacking light being entered into a region excluding the pixel area is formed on the color filter substrate 141.

[0085] In this instance, the black matrix 143 covers an upper portion of the thin-film transistor (I), but the black matrix 43 in the related art should cover up to ar upper portion of the drain contact hole region formed at an upper portion of the drain electrode:25 protruded from the gate line 13 as well as an upper portion of the thin-film transistor (T) as illustrated in FIG I by as much as an area (Al) and thus, the opening region may be reduced to an extent in the related art.

[00863 Howeves in an embodiment of the invention,. a drain contact hole formation region in the related art is removed, since the black matrix 143 merely covers only an area AZ, so that a part area A3 of the removed drain contact hole formation region is used as an opening area to secure a reyton that has been covered by the black matrix 143 as an opening area thereby enhancing the transmittance of a pixel.

[0087] Next, red., green and blue color filter layers 145 are formed on the color filter substrate 141 including the black matrix layer 143.

[0.088] Subsequently, a column spacer 147 for maintaining a cell gap between the color filter substrate 141 and the insulating substrate 101 bonded to each othe.r is formed at an upper portion of the color flltar layer 145 to complete the process of fabricating a color filter array substrate. At this time, the process of forming an alignment layer on a surface of the color fifler layer 145 may be additionally carried out. Furthermore. in the instance where the color filter substrate 141 and the insulating substrate 101 are bonded to each other, the column spacer 147 is inserted into the opening portion 121 formed on the insulating substrate 101 to prevent the insulating substrate 101 from being released in a horizontal direction, and thus, the bonding is properly carried out without'any twisting. In other words, the opening portion 121 plays a role of tixing, the column spacer 147.

(0080] Subsequently, tit process of forming a liquid crystal tayer 151 between the color lifter substtE' 141 and the insulating substrate 101 It oarrled out to complete the pr*cess ot fabtlcating a fringe field switching, (FF6) mode liquid crystal display device accotdtng!c ant,,:,. , Iment ot the lnventiàn, M901 On the ether hand, an array' substrate fqr a flings field, SWilChing (FES) mode liquid cystaj diSplay device aqtording to another ethbodimeflt Of 1h* Invefltton will described ¶MTh reference to the:'acoompansing drawings.

[00911 na 7 iS a sotiemati cross-sectional view illustrating' a fdpge field switching (FFS) mode llquk' ryatai display device according to another embodiment of the invention.

(0092] A, fringe field switching (FFS) mode liquid crystal display device according' to: anqther embodiment of the inventIoç, as iflustrated in FIG 71,, may' Includef a gate line (refer to reference numeral 103 in FIG 4) Mmed' in one direction on' a surface S the insulating substrate 201; a data PM 21:Sa crossed wil'' the gate line to define a i*eP regiom a tt*4Ifrn,, transistor fl) formed at an intersectiA,'of'the gate Iih4'shd the data Une213a; an iorganic inSUlatihg layer 217 h*ing an opening pôrdon 221 located at, an upper' portion of the thifl-fUn tjBnsjtOr (Ito, expose the ttilrr-fflrn transistor (T); a pixel electrode flsa tomied at an upper portion of the organic Insulating layer 217, arid directly conne ted tp the exposedIhin-flIm transistor Cr); a passivation layer 227 formed atan upper portion of the organic insulating layer 217 including the pixel electrode 22$a; and a plurality 0 common eiettrodes 233a formed at'rni upper portion of the passivation layer 227 afl4 separated from one another.

[00931 In this instance, a pixel electrode Z23a haying. a. large area is disposed on a front Surface of the pixel region with a space: separated from the gate tine ai the data Jine 21 a, and a plurally tf transparent rod-Shaped common eiodtodes 2333 are disposed to be separated from. one another y a predetentfled distance at an upper side of the picel electrode 223a by interposing The Pasnlayerfli therebetween, [0094] Fwtherrnore, as illustrated in FIG L the pixel Sell 22aa is :efect,iQy connected tG a difl electrodt 213c fr a thtett manner thrugh an opening: portion 221 located an upper portion of the Thin-film franiistor (fl *hQvt havhg. a separate dRift contact hole. in his instance, the opening po#tón 221 ja tanned to expose a óhannel region (refer to: reference numeral 209b in FIG 8J) and,a portion of the drain electrode 213c of the thin-film transistor (1).

t0095] On the other har4 red, green and bive. color flitem layers 245 and a biatk matrix. (BM) 243 Sposed between the color fitter layers 245 to bbck the trnmissibti, of light are deposited on a color fitter substrate 241 sepatated fittrs and bonded lb the insulatjng substrate 201 formed with the pixel electrode 223a and a kitlity tfcomnion,pdcs233a 1.6]: in This Jnstance, a portion covered by the black n*fr 243 may be covered bY as much as the: opening portion 221 at an upper portion ot the thin-tUrn translstqr (fl. by taking a bonding margin to the inSulating substrate 201 into consideration.

(009fl In this instance, the black matrix 24$ covers an upper portion of the thin-film transistor çr), but the black matrix 243 in the related art should cover up to an upper portion of the drain contact hole region formed at an upper portion of the drain electrode protruded from the gate line as well as an upper portion of the thin-film transistor (1) as illustrated in FIG 1 by as much as an area (Al), and thus, the opening region may be reduced to the edent in the related art.

jOO9Zj Accordlngiy in an embodiment of the irivernion, as iflustated Ih FIG 4, a draIn éotitact hole formation region in the related art is remoyed, arid a, part area A3 Of the removed drin contact hole formation region' Is used a an openipg area to secure a region tat' has been veted y the bladc matrix, Z43' as an' Opaiipg: are'1. thereby'enbandng the tmnsMIftan eta pbcel.

(0099] Furthermore,, as illustrated ifl na 7 a. column spacer 247' tr maintaining a celt gap With' røpi'' IC' the insulating.substi'ate 201 is protruded at an upper podion of the red, green and blue cólqr IjIter Jayers 245 to be, inserted Into the ppeniri9 portion 221 tOned at an upper portion of the thin-film transiltor (1) formed on the insulating sUbstrate 201.

jooiopj In addition, a oqui crystal' layer 25j is' formed between the. color lifter sub"' 241 and the frtsuiating substrat 201 bonded to each Other to tonfigure" a fiiflge field switching (ITS) mode ffquid, crystal display' thdce accordingta an embodiment of the Invention.

tooi:oii Through the foregoing onguraiion, the plurality $ rrmon sled, dØs 23$ supply a reterence voltage for driving liquid cryatals, im Øly a oi vSge, to *,, pixel.

(00102] The pluraHty of common electrødes 23'3a are overlapped with me pixel electrode 223a having a large area by interpfling the passivation layer 227 therebi,n af each pixel region to form a friñge'fleid.

[00103] In this marmei if a data signal is supplied to the pixel electrode 223a through the thin-film transistóv (1), then the common electrode 233a sqpplted. by a ornon voltage forms a fringe held so that liquid crystal, molecules aligned lit a horizontal direction between the insulating substrate 201 and the color filter substrate 241 are rotated by dielectric anisotropy, and thus, the light transmittance of liquid crystal molecules passing through a pixel region varies according to the rotational degree, thereby implementing gradation.

[00104] Accordingly, according to a fringe field switching (FF8) mode liquid crystal display device having the foregoing configuration in accordance with an embodiment of the inventIon, a photosensitive photo acryl layer used to reduce a parasitic capacftance in the related art can be used as is, thereby reducing power consumption.

[00105] Furthermore, according to an another embodiment of the invention, a drain contact hole in the related art that has been formed to electricaUy connect a drain electrode to a pixel electrode is removed, and an opening portion for exposing an upper portion of the thin-film transistor is formed on an organic insulating layer such that the exposed thin-film transistçr and the pixel electrode are electrically connected to each other in a direct manner and thus, a part area A3 of an area Al that has been used to form a drain contact hole in the related art can be used as an opening area to remove, a drain contact hole formation portion in the related art that has bean a cause of transmittance reduction, thereby enhancing transmittance by more than about 20 percent compared to the related a:1j [001 On the other hand, a method of fabricating an array substrate for a fringe field switching (FFS) mode liquid crystal display device having the foregoing configuration according to an embodiment of the invention will be described below with relerence to FIGS. SAthrough 80.

[001071 FIGS. BA through 80 are fabrication process crosssectiorial views illustrating an array substrate for a fringe fi&d switching (FF9) mode liqthd crystal display device according to another embodiment of the invention.

[00108] As illustrated in FIG, BA, a plurality of pixel regions including a switching function are defined on a transparent insulating substrate 201, and a first conductive metal layer 203 is deposited on the transparent insulating substrate 201 by a sputtering method; rn this instance, at least one selected from the group conssttng of alumirnurn (Al), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti, molytungsten (MoW), rnoly-titanium (MoTi), copper! moly-titaniurn (CuIMoTI) may be used for a target material for forming the first conductive metal layer 203.

1001091 Next, a photoresist having a high transmthance is deposited at an upper portion of the first conductive metal layer 203 to form a first photosensitive layer 205.

(00110] Subsequently, as illustrated in FIG. SB, an exposure process is carried out on the first photosensitive layer 205 through a photolithography :Pwcs technology using an exposure mask, and then the first photosensitive layer 205 is selectively removed thrpugh a development process to form a first photosensitive pattern 205a, [00111] Next, as illustrated in FIG. 80, the first conductive metal layer 203 is selectively etched by using the first photosensitive pattern 205a as a blocking layer to form a gate line; refer to reference numeral 103 in FIG. 4), a gate electrode 203a extended from the gate line, and a common line separated from and in parallel with the gate line at the same time..

(00112] Subsequently, the first photosensitive pattern 205a is removed, and then a' gate insulating layer 207 made of silicon nitride (SiNx) or silicófl oxide (Si02) is formed at a front sqrf,ge of the substrate tuding the gate electrode 203a.

[00113J Next, : illzfrr in AG 8D amorphous Silicon layer (a$tH) 209 and amoyphws silicon layer (ut or p÷) 2t1 contarling impurities areS seqqerifahy Øeposited on the gate insulating layer 2*7. At thiS tim1 the amorphc us' silicon layer' (a'Si*I) 12G9 and amcrphous,slllcon layer (it'-or p-F) 211 conlng impS': a'e deposited. using a Chemical'Vapour Deposition (CVI)) method. At this time an oxkleMased material lays-such as indium gatilu,zic oxide (l$ZQ) Instead of the, amorphous silicon layer *Si:H) 209 may. be: formed on the gate Insulating, layer 207 and applied to an oMe thin-film transistor.

(001141 Stthsequen, a,second Conductive layer 213 is deposited at a: front sujS'dthe substrate 20i inc1qing the amorphous siticon layer,(n+ Or p4)211 coitinihg httpurities using a sputtering metbot. At this time, at least one $let', from tt group consisting al aluminium (Al), tungsten WV). copper' (Cu), molybdenum (Mo),, Qhcc,miurn (Ct titanium (7), rn"4*tungsten (toW), moly-titanium (MoTI), copper! rnoly-titaniUm (Cu/Mini) may$eus;forafargetrnatervp fOrfrig fle second conductive metal layer 21& (OOttjJ SUbsequently; a pfiotbreslst having a, high i,, smittaj-ic i"deposfted at an upper portion of the second conductive layer 213 to form a second photosensitive layer.

(00116] Next, an exposure process is carded out on the second photosensitive layer through a photolithography process technology' using an exposure mask, and then the second photosensitive layer is selectively removed through a development process to form a second photosensitive pattern.2 15.

[00117J Subsequently as illustrated in FIG, BE, the second conductive layer 213 s selectively wet-etched by using the second photosensitive pattern 215 as an etching mask to define, a source electrode and drain electrode formation region together with the data line 21.3a crossed with the gate line 203 in a vertical direction (or with a vertical separation), [00118] Next, as illustrated in FIG. BE, a portion of the conductive layer 213 corresponding to the source electrode and drain electrode formation region and the amorphous silicon layer (n+ or p+) 211 containing impurities and amorphous silicon layer (a-Si:H) 209 below the data line 213a are sequentially etched through a dry etching process to form an ohmic contact layer 211a and an active Layer 209a. At this time, a portion of the conductive iayer 213 correspondirg lo the source electrode and drain electrode formation region and the amorphous silicon layer (n$-or p±) 211 containing impurities and amorphous silicon layer (a-SiH) 209 below the data line 213a,re patterned at the same time, and thus, an active tail will not occur.

[00119] Subsequently, the 5econd photosensitive pattern 215 is removed, and then an inorganic insulating layer or organic insulating layer 217 is deposited at a front surface of the substrate including the active layer 209a and ohmic contact layer 211a, a portion of the conductive layer 213 corresponding to the source electrode and drain electrode formation region and the data line 213a. At this tinie, a photo acryl material or other photosensitive organic insulating materials exhibiting photosensitivity may be used for the organic insulating layer 217. Furthermore, since the photo acryl exhibits photosensitivity, an exposure process can be carried out without forming a separate photoresist during the exposure process. Furthermore, any one selected from silicon nitride (SINx) and other inorganic insulating materials may be used for the inorganic insulating layer.

£001201 Next, as illustrated in FIG, 80, an exposure. process is carried out on the organic insulating layer 217 through a photolithography process technology using an exposure mask, and then the organic insulating layer 217 is selectively removed through a development process to form an op. fling portion 221 for exposing an upper portion (or a part thereof) of the conductive layer 213 corresponding to the source electrode and drain electrode formation regie n. At this time, he opening portion 221 is formed at a portion at the thin-film transistor (T), namely, a source electrode and drain electrode formation region. Furthermore, a side wall of the ohmic contact layer 211a and active layer 209a including an upper portion of the conductive layer 213 corresponding to the source electrode and drain electrode formation region and a partial upper surface of the gate insulating layer 207 are exposed through the opening portion 221.

[001 21j Subsequently, as illustrated in FIG. 8K, a transparent conductive material is deposited at an upper portion of the organic insulating layer.217 including the opening portion 221 using a sputtering method to form a first transparent conductive material layer 223. At this time, any one composition target selected from a transparent conductive material group including Indium Tin Oxide (ITO). Indium Zinc Oxide.(lZO), and the like is used for the transparent conductive material. Furthermore, the first transparent conductive material layer 223 is directly brought into contact with a surface of the conductive layer 213 corresponding to the source electrode and drain electrode formation region and a side wafl of the ohmic contact layer 2111a and active layer 209a.

(00122J Next, a photoreslat having a high transmittance is deposited at an upper portion of the first transparent conductive material layer 223 to fmi a third photosensitive layer.

[001231 Subsequently. an expoure process is cirded ot4 qii the third photosensitive layer through a. photolitho9ra,hy process techn*gy using an exposure nask, and. then tne third Photosensitive' lyer j aelec tely removed through a development prOtest to form a third phqlgsens1 pattern 225, At this time, the third, photosensitive Paft'cn Z25' expos, all porflcns exckiding the pbS' electrode bttBtiOfl region ln'tt*'flrsflransparent conductive mateilal layer 22L (iOi'fl] Next, as iflflated in FIG $1, the first transparent: tbñducthe material liyer 223 and the second conductive layer213 at a tower portion thereof are selectively etched by using the third photoseniitbse pattern 225 as an etching mask to form a pixel electro4e 223a electrically t"niiected to the drain electrode 213cm a direct manner, togett*r with the source' electrode 21Sb and drain electrode2i3oat thesarnetirne, At this time, thepixel electrodefl3als diPetjy brought info contact w$th a %ide wall of the ohmic contact layer 21:ta and active: :layer 209a tpgether with the anelecti"' 21 3cihrougfrthe opening portion 221..

Fwthermort a portion Of the ohmic contact: layer 211a between, the source: electrode 21 3b' and drain c' e2t3c Is also e,,,ø during the formadon of' the souretectrode 213b and drain electrode213c. Then, an,upper porvon of the esurce electrode 21 3b and' a portion of the transparent conductive i''r 223 covered ofl the organic insulating layer 217 corresponding to the source electrode 213b are also removed through an etching process. Accordingly,, the opening portion 221 exposes the upper porion of the gate portion above' the gte electrode 203a, the active layer 209a corresponding to a channel region, and the drain electrode 213c.

[001251 Subsequently, as illustrated in FIG, 8J, a portion of the exposed ohmic contact layer 211a is selectively etched through a dry etching process to expose a channel region 209b of the active layer 209a at a lower portion of the ohmic contact layer 211a.

[001263 Next, as liustrated n FIG 8K, the third photosensitive pattern 225 is removed, and then an inorganic ihsulating material or organic insulating material a deposited at a front surface of the substrate including the source electrode 213b, drain &ectrode 213c and pix& electrode*223a to form a passivation layer 227.

(00127] Subsequently, as illustrated in FIG. BL, a transparent conductive material is deposited at an upper portion of the passivation layer 227 using a sputtering method to form a second transparent conductive material layer 233. At this time, any one composition target selected from a transparent conductive material group including Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), and the !.ike is used fOr the second transparent conductive material 233.

[0O128] Ne4 a photoresist having a high transmittance is deposited at an upper portion of the second transparent conductive material layer 233 to form a fourth photosensitive layer 235.

(00129J Subsequently, as illustrated in FIG. 3M, an exposure process is carried out on the fourth photosensitive layer 235 through a photolithography process technology using an exposure mask, and then the fourth photosensitive layer 235 is selectively removed through a development process to form a fourth photosensftive pattern 235a. :30

[00130] Next, as illustrated in FIG. 8N, the second transparent conductive material layer 133 is selectbeely etched by using the fourth photosensitive pattern 235a as ap etching mask to form a plurality of common cectrodes 233a separated from one another while being overlapped with the pixel electrode 223a.

[00131] Next, the remaining fourth photosensifive pattern 23% is removed to complete the process of fabricating an array substrate for an AH-IPS mode hquLd crystal display device according to an embodiment of the invention.

[00132] Then, as illustrated in FIG. 80, a black matrix layer 243 for blocking light being entered into a region excluding the pixel area is formed on the color filter substrate 241.

(00133] In this instance, the black matrix 243 covers an upper portion of the thin-film transistor (T), but the black matrix 43 in the related art should cover up to an upper portion of the drain contact hole region formed at an upper portion of the drain electrode 25 protruded from the gate line 13 as well as an upper portion of the thin-film transistor (T) as illustrated in FIG. 1 by as much as an. area Al, and thus, the opening region may be reduced to an extent in the related art.

[00134] However, in an embodiment of the invention, a drain contact hole formation region in the related art is removed, since the black matrix 243 merely covers only an area A2, so that a part area AS of the removed drain contact hole formation region is used as an opening area to secure a region that has been covered by the black matrix 243 as an opening area thereby enhancing the transmittance of a pixel.

[00135] Next, red, green and blue color filter layers 245 are formed on the color filter substrate 241 including the black matrix layer 243. 33.

[001361 Subsequently, a column spacer 247 for maintaining a cell gap between the color filter substrate 241 and the insulating substrate 201 bonded to each other is formed at an, upper portion of the color filter Jayer 245 to complete the process of fabricating a color filter array substrate..At this time, the proces $ of forming an alignment layer on a surface of the co'or filter layer 245 may be additionally carried out. Fhrthermore, in the instance where the color filter substrate 241 and the insulating substrate 201 are bonded to each other, the column spacer 247 is inserted into the opening portion 221 formed on the insulating substrate 201 to prevent the insulating substrate 201 from being released in a horizontal direction, and thus, the bonding is properly carried out without any twisting. in other words, the opening portion 221 plays a role cf fixing the coumn spacer 247.

[00137] Subsequently, the process of forming a liquid crystal layer 251 between the color filter substrate 241 and the insulating substrate 2C1 is carried out to complete the process of fabricating an AftIPS mode liquid crystal display device according to an another embodiment of: the invention.

100138] On the other hard, a fringe field switching (FFS) mode liquid crystal display device and method for fabricating the same according to another embodiment of the invention may be applicable to a liquid crystal display device having a color filter on IFT (COT) structure.

[00139] As described above, according to embodiments of the invention, a drain contact hole in the related art that has been farmed to electrically connect a drain Sectrode to a pixel electrode is removed, and an opening portion for exposing an upper portion of the thin-film transistor is formed on an organic nsulatinU layer such that the exposed thin-film transistor and the pixel electr ode are electrically connected to each other in a direct manner, and thus, a part area A3 of an area Al that has been used to form a drain Contact hole in the;e1ed art can be, as an opening aa to remove a drain cchtact hole formation portion in the related, art that has been a cause f transmittance reduction, thereby sOh$nohig ttansrnlttatice y more than about 20 percent compared to øe iss: t001401 Eurtherrnorei: aCcording: to an array substrate for a fEh%ge field switbhing' (PFS) mode liquid ctystal, display device arid method for fabrttating"the.

same in accordance with an embodiment of the Invention, a photoseftsitive photo acri Jay& used to reduce a parasiti' capacftancie in the related art cafl be t*ed. as Is thereby reducing power'consumption.

(00141] Although the example embodiments of the invention have been described, in detail, it should be understood by thc'se' Skifled in the art that yarlous modffl*tions and other equivalent embodiments tweEt can be made.

[001421 Consequentl,c, the scope of the irnjeni Is not $frnfted' to tt wn'bodiments, and vatious modifoatlons and improvements theretG made by those skilted: in the art: using the baslo concept of the:jnveng as defined in the accompanying claims will fail in the scope of'the inyentiit