GB2489353A - LSI, fail-safe LSI for railways, electronic device, and electronic device for railways - Google Patents

LSI, fail-safe LSI for railways, electronic device, and electronic device for railways Download PDF

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Publication number
GB2489353A
GB2489353A GB1211339.5A GB201211339A GB2489353A GB 2489353 A GB2489353 A GB 2489353A GB 201211339 A GB201211339 A GB 201211339A GB 2489353 A GB2489353 A GB 2489353A
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United Kingdom
Prior art keywords
signal
lsi
line
external
circuit
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GB201211339D0 (en
Inventor
Tetsuaki Nakamikawa
Kotaro Shimamura
Hideo Sakuyama
Takeshi Takehara
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Hitachi Ltd
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Hitachi Ltd
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B61—RAILWAYS
    • B61L—GUIDING RAILWAY TRAFFIC; ENSURING THE SAFETY OF RAILWAY TRAFFIC
    • B61L27/00—Central railway traffic control systems; Trackside control; Communication systems specially adapted therefor
    • B61L27/50—Trackside diagnosis or maintenance, e.g. software upgrades
    • B61L27/57—Trackside diagnosis or maintenance, e.g. software upgrades for vehicles or trains, e.g. trackside supervision of train conditions
    • B61L27/0094—
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B9/00—Safety arrangements
    • G05B9/02—Safety arrangements electric
    • G05B9/03—Safety arrangements electric with multiple-channel loop, i.e. redundant control systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11898—Input and output buffer/driver structures
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/007—Fail-safe circuits
    • H03K19/0075—Fail-safe circuits by using two redundant chains
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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    • H01L2027/11877—Avoiding clock-skew or clock-delay
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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    • H01L2027/11874—Layout specification, i.e. inner core region
    • H01L2027/11879—Data lines (buses)
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Abstract

Conventional fail-safe LSIs have been used for the placement of processors and comparators in chips, but have not been used for the placement of package signal pins. The adaptability of fail-safe LSIs to various peripheral circuits and high speed memory has also not been considered. An integrated internal interface, in which the output from two processors is matched, is connected to a common line internal bus, and a plurality of external interface circuits are connected to the common line internal bus. Furthermore, signal pins corresponding to two systems are disposed at opposite corners of a package, and signal pins corresponding to a common line are disposed therebetween.

Description

Description
Title of Invention:
LSI, FAIL-SAFE LSI FOR RAILWAYS, ELECTRONIC DEVICE, AND
ELECTRONIC DEVICE FOR RAILWAYS
Technical Field
[0001) The present invention relates to a semiconductor chip (LSI) including,a microprocessor. More specifically, the present invention relates to a fail-safe semiconductor chip (LSI) for railways used for a control system requiring high security such as a signal system in railways, an electronic device including the semiconductor chip (LSI), and an electronic device for railways.
Background Art
[0002] In a control system requiring high security such as a signal system for railways, apparatuses are designed based on the idea of "fail-safe". Even when something goes wrong with the apparatus in the system, the system is safely stopped and is not put at risk. It is * necessary to reliably detect an abnormality of the apparatus for ensuring fail-safe operation. Accordingly, in a control system using a microprocessor, the processor is multiplexed and monitored alongside each other for detecting an abnormality of the processor. For example, an electronic device having an LSI with a fail-safe function including a nicroprocessor is adopted in a signal system for railways. If an abnormality of an apparatus in the system mounted in a vehicle is detected by the LSI, a control signal indicating that the abnormality is occurred in the railway vehicle is transmitted based on an abnormality detection signal from the electronic device for railways to a railway vehicle controller provided on the ground. This control signal is transmitted by wireless. The railway vehicle controller, which receives the control signal, transmits a vehicle stop signal to each vehicle by wireless to safely perform the travel control of the railway vehicle.
[00031 Due to high integration of a semiconductor in recent years, one LSI chip can include two processors, so that the processing results of the two processors can be compared. The comparison method is disclosed in, for example, Patent Literature 1. The single-chip fail-safe LSI is disclosed in Non-Patent Literature 1.
Citation List Patent Literature [0004] Patent Literature 1: Japanese Patent Laid-Open Publication No. 6-161798 Non Patent Literature [00051 Non Patent Literature 1: K. Shimamura, et al.: "A Single-Chip Fail-Safe Microprocessor with Memory Data Comparison Feature", IEEE 12th Pacific Rim International Symposium on Dependable Computing (PRDC'06), (18-20 Dec. 2006)
Summary of Invention
Technical Problem [00061? As a result of high integration of a semiconductor, peripheral circuits which are conventionally provided Outside can be incorporated in a chip. Furthermore, an external high-speed and large-capacity memory is necessary for a high-speed processor.
[0007] The number of chips and the number of signal pins of a package storing the chip need to be increased to allow various peripheral circuits and external high-speed memories to connect to a chip. Further, the wiring delay and the difference in electric characteristics need to be considered for arrangement of signal pins because the operating frequency of the peripheral circuit is made faster.
[0008] In the conventional art, the arrangement of plural processors in a chip and the arrangement of a comparison circuit for detecting an abnormality of the processor are explained for ensuring reliability, but the arrangement of signal pins of a package and the arrangement of parts of a device board are not considered. Moreover, only one type of general-purpose bus is provided for peripheral circuits connected to the external portion of the chip in the conventional art, and the adaptability to various peripheral circuits and external high-speed memories is not considered.
[0009] Generally, in an LSI including a processor, an external signal pin often has a plurality of functions which are switched as necessary to deal with various uses.
In other words, a pin multiplex is used. Accordingly, a limited number of signal pins can be effectively used.
In the conventional art, however, the pin multiplex in the fail-safe LSI is not considered.
[0010] An object of the present invention is to ensure security and high efficiency of LSI chips including peripheral circuits.
Solution to Problem [0011] For ensuring security and high efficiency of LSI chips including peripheral circuits, signal pins of two lines including processors are arranged at opposing corners of a package, i.e., at the most remote positions.
Moreover, signal pins of a common line are arranged between the signal pins of the two lines. The signal pins of the two lines do not need to be arranged at the most remote positions in a precise sense as long as security and high efficiency can be ensured. When there are two peripheral circuits of the common line, signal pins relating to each peripheral circuit are arranged between signals relating to the two lines at two positions.
Advantageous Effect of Invention [0012] Since the signal pins of the common line are arranged between the signal pins of the two lines, the distance between the signal pins of the two lines can be extended. Accordingly, the possibility that an error operation is caused simultaneously in the two lines by a single factor such as electromagnetic noise can be reduced.
S
Brief Description of Drawings
[0013) [Figure 1] Figure 1 is a block diagram showing an outline of an internal arrangement of a fail-safe LSI according to the present invention.
[Figure 2A] Figure 2A shows a physical structure of the fail-safe LSI shown in Figure 1, and a cross-section of the fail-safe LSI 10.
[Figure 23] Figure 28 shows the physical structure of the fail-safe LSI, and is an overhead view of the fail-safe LSI 10 shown in Figure 214 from which a sealing member 102 is removed.
[Figure 20] Figure 20 shows the physical structure of the fail-safe LSI, and a circuit surface of an LSI chip 100 shown in Figure 28.
[Figure 3] Figure 3 is a block diagram showing an internal arrangement of a fail-safe LSI according to a first embodiment of the present invention.
[Figure 4] Figure 4 shows an outline of wiring connected to a common line internal bus 21 shown in Figure 3.
[Figure 5] Figure 5 shows an example of wiring on an internal arrangement of the common line internal bus 21 shown in Figure 3.
[Figure 6) Figure 6 is a timing chart for explaining an operation of the internal bus 21 shown in Figure 5.
[Figure 7] Figure 7 shows an example of an internal arrangement of a comparison device shown in Figure 3.
[Figure 8] Figure 8 shows a signal waveform for explaining an operation of an alternating signal generator 201 shown in Figure 7.
[Figure 9] Figure 9 shows an example of an internalS arrangement of a bus comparator 202 shown in Figure 7.
[Figure 10] Figure 10 shows an example of an internal arrangement of a duplex control circuit shown in Figure 7.
[Figure 11] Figure 11 shows an example of an internal arrangement of a general-purpose input/output circuit (general-purpose 1/015) shown in Figure 3.
[Figure 12] Figure 12 is an illustration for explaining a layout of a logic circuit and an arrangement of an input/output pad in the LSI chip according to the present invention.
[Figure 131i] Figure 13A is an illustration for explaining an arrangement of external pins of the LSI according to the present invention, and shows the arrangement of the external pins from directly above of the LSI 10 as viewed from an observing point outside of the LSI 10 shown in Figure 13B.
[Figure 13B} Figure 138 is an illustration for explaining the arrangement of the external pins of the LSI according to the present invention, and shows the observing point in Figure 13A.
[Figure 14] Figure 14 shows an example of an arrangement of parts on an electronic circuit board according to the present invention.
[Figure 15] Figure 15 is a block diagram showing an example of an internal arrangement of a fail-safe LSI according to a second embodiment.
[Figure 16] Figure 16 shows an example of an internal arrangement of a general-purpose input/output circuit and a pin function selector according to the second embodiment - [Figure 17] Figure 17 is an illustration for explaining a layout of a logic circuit and an arrangement of an input/output pad in an LSI chip according to the second embodiment.
[Figure lSA} Figure iSA is an illustration for explaining an arrangement of external pins of the LSI according to the second embodiment.
[Figure 188] Figure 188 is an illustration for explaining the arrangement of the external pins of the LSI according to the second embodiment, and shows an observing point in Figure iSA.
[Figure 19A} Figure 19A shows an outline of the fail-safe LSI having a physical structure different from that according to the first embodiment of the present invention, and shows a cross-section of the fail-safe LSI.
S
[Figure 198] Figure 196 shows the outline of the fail-safe LSI having the different physical structure, and is an overhead view of the fail-safe LSI shown in Figure 19A from which a sealing member is removed.
{Figure 1SC] Figure 19C shows the outline of the fail-safe LSI having the different physical structure, and shows a circuit surface of an LSI ship shown in Figure 191k.
[Figure 20A} Figure 20A is an illustration for explaining an arrangement of external pins in the fail-safe LSI having the external pin structure different from that according to the first embodiment of the present invention, and shows an example when no external pins are provided at a central portion of a package in the first embodiment.
[Figure 208] Figure 208 is an illustration for explaining an arrangement of external pins in the fail-safe LSI having the external pin structure different from that according to the first embodiment of the present invention, and shows an example when external pins are provided at the central portion of the package but the central portion is composed of only power-supply pins.
[Figure 20C] Figure 20C is an illustration for explaining an arrangement of external pins in the fail-safe LSI having the external pin structure different from that according to the first embodiment of the present invention, and shows an example when external pins are provided at the central portion of the package and the central portion is composed of signal pins.
Description of Embodiments
[0014] A first embodiment of the present invention will be explained below with reference to Figures 1 to 14.
Figure 1 is an illustration for explaining an outline of an LSI according to the present invention. The LSI 10 includes two systems of processing devices having the same structure including processors and external interface (hereinafter referred to as I/F) circuits. In this embodiment, two systems are referred to as an A line and a B line. The processing device of each line includes at least one processor and at least one external I/F circuit, which are connected to an internal bus inside the system. The processing results of the processor in each line are shown in the internal bus. A comparison device connected to the internal bus of the A line and the internal bus of the B line compares signals from both of the internal buses (specifically, the signals from the buses correspond to address, write data, read data, and the like) to confirm whether the processing devices of two lines perform the same operation. A signal indicating normality is outputted when both of the processing devices perform the same operation, and a signal indicating abnormality is outputted when the processing devices perform different operations. These signals are outputted as a normal/abnormal discrimination signal 200 to the outside of a fail-safe LSI chip 100 (see Figure 21k) . When the situation is normal, i.e., when the internal buses of two lines output the same signals, the comparison device selects either one of them and outputs it to a common line internal bus. When the common line internal bus outputs a signal to the processing devices of two lines, the comparison device outputs it to both of the processing devices. Since the signals are transmitted through one bus, the same processing can be performed in the two lines at the same operation timing. The common line internal bus is connected to a plurality of common line external I/F circuits. The external I/F circuits of two lines and the common line external I/F circuits are connected to external devices, respectively. The internal interface for checking the output from the two processors is not directly connected to the outside of the chip as in the conventional method, and is connected to the common line internal bus which is connected to the plurality of external I/F circuits. Accordingly, various peripheral circuits can be connected thereto and thus the performance of the LSI can be improved.
[0015] In other words, since the plurality of external I/F circuits can be included due to the common line internal bus, the plurality of external devices can be directly connected to the chip. When the external device includes an external memory, a signal voltage of the memory in the external device connected to the external I/F circuits of two lines is set to be at least partially different from a signal voltage of the common line external I/F circuit.
The concrete examples thereof will be explained later.
[0016] Figures 211⁄2, 2B, and 2C show the outline of the physical structure of the fail-safe LSI according to the first embodiment. Figure 211⁄2 shows the cross-section (internal arrangement) of the fail-safe LSI 10 in Figure 1. A signal and a power source (not shown) of an external I/F circuit of the LSI chip 100 are electrically connected to a package substrate 101 by a bonding wire 103 and is connected to the outside via solder balls 104 provided below the package substrate 101. In other words, the LSI chip 100 mounted on the package substrate 101 is electrically connected to the solder balls 104 via the bonding wire 103. The upper portion of the LSI chip 100 is protected by a sealing member 102.
Figure 28 is an overhead view of the fail-safe LSI 10 from which the sealing member 102 is removed. The LSI chip 100 is arranged on the package substrate 101 so that the circuit surface of the LSI chip 100 faces upward, and is connected to the package substrate 101 via the bonding wire 103. Figure 2C shows the circuit surface of the LSI chip 100 and the package substrate 101. The LSI chip 100 is composed of a logic circuit mounting region 105 where logic circuits such as the processing devices of two lines and the comparison device are formed and an input/output pad region 106 for connecting the signals and the power source. In the embodiment, the processing device of the A line is arranged at the left side, the processing device of the B line is arranged at the right side, and the common line circuit is arranged at the center of the LSI chip 100. The arrangement in the chip will be explained later.
[0017] Figure 3 shows one example of the internal arrangement of the fail-safe LSI and the external devices according to this embodiment. The fail-safe LSI 10 includes: processors hA and llB of two lines (A line and B line); internal buses l2A and 12B of two lines; and high-speed memory I/F circuits 13A and 13B, external bus I/F circuits l4A and 148, and general-purpose input/output circuits iSA and 158 as external I/F circuits of two lines. The high-speed memory I/F circuits 1311⁄2 and 138 are connected to external RANs 13111⁄2 and l3lB as external devices, and the external bus I/F circuits 14A and l4B are connected to external ROMs 14Th and l4lB as external devices. The fail-safe LSI 10 further includes: a comparison device 20; a common line internal bus 21; and a system bus I/F circuit 22 and a network I/F circuit 23 as common line external I/F circuits. The system bus I/F circuit 22 is connected to a system bus bridge 221 as an external device, and the network I/F circuit 23 is connected tO a network physical layer 231 as an external device. The comparison device outputs the normal/abnormal discrimination signal 200.
[0018] Figure 4 shows the outline of wiring connected to the common line internal bus 21 (see Figure 3) according to this embodiment. The common line internal bus 21 is connected to an I/F signal line 205 for the comparison device 20, an I/F signal line 222 for the system bus I/F circuit 22, and an I/F signal line 232 for the network I/F circuit 23. The I/F signal lines 205, 222, and 232 are divided into master ports 205M, 222M, and 232M for transmitting a read/write request to the internal bus, and slave ports 205S, 222S, and 232S for receiving the read/write request from the internal bus. All of the three modules (i.e., the comparison ciicuit 20, the network I/F circuit 23, the system bus 1/F circuit 22) connected to the common line internal bus 21 include the master ports and slave ports according to this embodiment.
Generally, however, it is only required that these three modules include either master ports or slave ports. The internal buses 12A and 128 of two lines have the same structure and function as the common line internal bus 21 except that the number of modules connected thereto is different, and thus the detailed explanation thereof is omitted. For example, the I/F between the high-speed memory I/F circuits 13A and 133 includes only slave ports.
[0019] Figure 5 shows the internal arrangement of the common line internal bus 21 and the detailed arrangement of the wiring connected thereto according to this embodiment. In Figure 5, the master ports 205M, 222M,.
and 232M are shown separately from the slave ports 205S, 222S, and 232S for facilitating the explanation of the flow of signals. The common line internal bus 21 is composed of wiring connected to a bus control circuit 211 and the ports 205M, 222M, 232M, 205S, 222S, and 232S.
The bus control circuit 211 is composed of a request control circuit 212 and a response control circuit 213.
Each master port 205M, 222M, 232M is composed of six types of signals: address (output) 2051M, 2221M, 2321M; write data (output) 2052N, 2222M, 2322N; command (output) 2053M, 2223M, 2323M; grant (input) 205*1, 222*1, 232*1; read data (input) 2055M, 2225M, 2325M; and valid (input) 205614, 222614, 232614. Each slave port 2053, 2223, 2323 is composed of seven types of signals: address (input) 20513, 22213, 23213; write data (input) 20523, 22223, 23223; command (input) 20533, 22233, 23233; busy (output) 2057S, 22273, 23273; port number (output) 20583, 22283, 23283; read data (output) 20553, 2225S, 23253; valid (output) 20563, 22263, 23263. The input and output are performed from each port to the bus control circuit 211. The request control circuit 212 arbitrates a forwarding request from each master port 20514, 22214, and 23214 to decode the address 205114, 222114, 232114, and selects the slave port 2053, 2223, or 2323 for outputting. The bus arbitration and address decoding is a well-known technique in the field, and thus the detailed explanation thereof is omitted. The response control circuit 213 arbitrates a read data returning request from each slave port 2053, 2223, 2323, and outputs the master port 20514, 22214, 232M which originally sends the request. The response control circuit 213 includes a buffer (not shown) that temporarily stores the read data for each slave port. Accordingly, the returning request from each slave port 2053, 2225, 2323 is not retarded.
[0020] Figure 6 is a timing chart for explaining the operation of the common line internal bus 21. Figure 6 shows the operation of writing and reading data between the master port 205M and the slave port 2223. The common line internal bus 21 transfers data every one clock cycle in synchronization with a clock signal shown in the upper portion of the drawing (which is indicated as a clock cycle in Figure 6) -For example, when an address (A0) indicating a register inside the system bus I/F circuit 22 as the address 2051M and signs (DO, W4) indicating four byte write as the write data 2052N1 and command 2053M are given to the bus control circuit 211 from the comparison circuit 20 (see Figure 3) during the clock cycle i, the request control circuit 212 confirms that there are no requests from the other master ports and that the slave port to which the request is sent is not in a busy state, and asserts the grant 2054M to notify the requestor that the request is accepted. At the sane time, the request control circuit 212 outputs the address 22213, write data 22223, and command 22233 to the slave port 2223 to which the request is sent. The system bus I/F circuit 22 (see Figure 3) connected to the slave port 222S receives the address and writes the write data to a register in its module in accordance with the address.
[0021] When an address (Al) indicating a register inside the system bus bridge 221 connected to the system bus I/F circuit 22 as the address 2051M and a sign (R4) indicating four byte read as the command 2053M are given to the bus control circuit 211 during the clock cycle j, the request control circuit 212 determines the state of the bus, and asserts the grant 2054M to notify the requestor that the request is accepted. At the same time, the request control circuit 212 outputs the address 2221S and command 2223S to the slave port 222S to which the request is sent. The system bus 1/F circuit 22 (see Figure 3) connected to the slave port 222S receives the address and outputs a read request to the system bus bridge 221 (see Figure 3) in accordance with the address.
During the clock cycle j + 1, the system bus I/F circuit 22 asserts the busy 2227S and notifies the request control circuit 212 that other requests cannot be accepted. When the return of the read data from the system bus bridge 221 is prepared during the clock cycle J+ 2, the system bus I/F circuit 22 outputs to the response control circuit 213 the sign (P0) indicating the master port 205M that is a requestor as the port number 2228S of the slave port 2223, the read data 22253 (Dl), and the valid 22263. The response control circuit 213 outputs the read data 2055t4 (Dl) and the valid 2056M to the port 205M indicated by the port number 2228S.
[0022] As described above, the data transfer is performed between the connected modules with use of the corrirnon line internal bus 21. Especially, in this bus, the request control and the response control are separated from each other, and accordingly, even during the read request from one module, the data transfer between other modules cannot be prevented. In short, so-called split transaction is achieved. Even when a module transfers a large amount of DMA data such as the network I/F circuit (see the numeral number 22 in Figure 3) and the system bus I/F circuit (see the numeral number 23 in Figure 3), the bus is not occupied. Thus, the bus throughput is not reduced. Since each port is independently connected to the bus control circuit, the operation speed of the bus as a whole is minimally affected by wiring delay even when the modules are remotely disposed.
[0023) Figure 7 shows the internal arrangement. of the comparison device 20 according to this embodiment. The comparison device 20 includes: a bus comparator 202 that compares the bus signal from the internal bus l2lA of the A line with the bus signal from the internal bus 12Th of the B line and outputs the comparison result (comparison discrepancy signal 204) to an alternating signal generator 201; a duplex control circuit 203 that is connected between the internal buses of two lines and connected to the output part of the bus comparator 202; and the alternating signal generator 201 that receives the comparison discrepancy signal 204 from the bus comparator 202 and outputs a normal/abnormal discrimination signal 200 (High/Low). The comparison device 20 is connected to the internal bus 212A of the A line, the internal bus 1218 of the B line, and the internal bus 21 of the common line (see Figure 3). The duplex control circuit 203 receives the comparison discrepancy signal 204, which is an output signal from the bus comparator 202, and controls the internal bus 2l2A of the A line and the internal bus 1218 of the B line.
[0024] Figure 8 shows the operation of the alternating signal generator 201 according to this embodiment. The alternating signal generator 201 outputs the normal/abnormal discrimination signal 200 in accordance with the comparison discrepancy signal 204 (alternating signal) outputted from the bus comparator 202. When one level signal indicating the normality or abnormality is outputted to the outside, a failure mode in which a signal level is fixed to ON (High) or OFF (Low) cannot be avoided. In the signal system for railways, the "alternating signal", in which the normality is indicated when the ON state and the OFF state are repeated under a certain frequency and otherwise the abnormality is indicated, is conventionally used. In this embodiment, the alternating signal generator 201 outputs a desired frequency signal when the comparison discrepancy signal 204 (alternating signal) is consistent, i.e., normal, and outputs a level signal when the comparison discrepancy signal 204 is not consistent, i.e., abnormal. The technique of generating the alternating signal by the alternating signal generator 201 is commonly known, and thus the detailed explanation thereof is omitted.
[0025] Figure 9 shows the internal arrangement of the bus comparator 202 according to this embodiment. The bus comparator 202 always compares the signal outputted from the internal bus 12Th of the A line and the signal outputted from the internal bus l2lB of the B line, and turns ON the comparison discrepancy signal 204 when detecting that the signals are not consistent. The bus comparator 202 compares the address l2llMA to 1211MB, the write data 1212MA to 1212MB, the command 1213MA to 1213MB, the busy 1217SA to 1217SB, the port number 121SSA to 121BSB, the read data l2lSSA to 121SSB, and the valid 12163A to 1216SB. When the bus comparator 202 detects the discrepancy even once, the flip-flop is set inside the bus comparator 202 and the ccmparison discrepancy signal 204 is turned ON. Incidentally, for detecting the error operation of the bus comparator itself, the technique of duplexing the comparator or intentionally occurring an error every predetermined period is known.
Such a technique for a reliable comparator is commonly kflOWflr and thus the detailed explanation thereof is omitted.
[0026] rigure 10 shows the internal arrangenent of the duplex control circuit 203 according to this embodiment.
The duplex control circuit 203 outputs the signal outputted from the internal bus 121A of the A line to the common line internal bus 21 unless the bus comparator 202 detects the comparison discrepancy. Specifically, the duplex control circuit 203 outputs the address l2llMA, write data 12l2t4A, command 1213MA, busy 1217SA, port number 1218SA, read data 1215SA, and valid 12165/A as the address 2051M, write data 2052N1, command 2053M, busy 20575, port number 20585, read data 20553, and valid 2056S.
When the comparison discrepancy is detected, the comparison discrepancy signal 204 stops the output of the command 1213MA and valid 12165/A. Accordingly, the common line internal bus 21 does not detect the issue of the request and response, and consequently, the output of the inconsistent data to the common line internal bus 21 is stopped.
[0027] The signal outputted from the common line internal bus 21 is simultaneously transmitted to the internal bus l2lA of the A line and the internal bus 1218 of the 8 line. Specifically, the grant 2054M, read data 2055M, valid 205GM, address 20513, write data 20523, command 20533 are respectively transmitted to the grant 2014MA and 1214MB, read data 1215MA and 1215MB, valid 1216MA and 1216MB, address 1211SA and 1211SB, write data l212SA and 121238, and command 1213SA and 1213SB. Due to the duplex control circuit 203, the internal bus 121A of the A line and the internal, bus 1218 of the B line work as one bus (port 205) for the common line internal bus 21. Moreover, the operation timing of the internal bus 12Th of the A line coincides with that of the internal bus 1218 of the B line, and accordingly, the processing devices of two lines work in the same way.
[0028] The processors hA and 118 are commonly-known general microprocessors, and thus the detailed explanation thereof is omitted. The high-speed nemory I/F circuits 13A and 138 are commonly-known general- purpose high-speed memories such as double data rate-synchronous DRAM (DDR-SDRAM), and thus the detailed explanation thereof is omitted. An 1,/F voltage tends to be reduced for speed-up compared to a general-purpose external bus. Specifically, the I/F voltage of the general-purpose external bus is 3.3V and the I/F voltage of the DDR-SDRAN is 2.SV. The LSI is required to deal with a plurality of I/F voltages. The external bus I/F circuits 14A and 148 are common-known external buses of a general microprocessor composed of a chipselect, address, data, read/write strobe, and the like, and thus the detailed explanation thereof is omitted.
[0029] Figure 11 shows the internal arrangement of the general-purpose input/output circuit l5A (see Figure 3) according to this embodiment. The general-purpose input/output circuit 158 has the same arrangement. The general-purpose input/output circuit iSA includes a general-purpose 10 read data register (PIORRA) 1MA, a general-purpose write data register (PIOWRA) 152A, a general-purpose 10 function setting register (9IOFRA) 153A. These registers read and write values by the processor llA via the internal bus 12A. PIORRA and PIOWRA have a data width of eight bits, and are connected to an external signal line l5OA of the LSI 10 via an input/output buffer 154A. PIOFR_A has a data width of one bit. When its value is zero, the value set in PIOWRA is outputted to the external signal line lSOA.
When the value of PIOFRA is one, the signal level of the external signal line 150A is inputted to PIORRA.
[0030] Figure 12 is an illustration for explaining the layout of the logic circuit and the arrangement of the input/output pad in the LSI chip 100 according to this embodiment. It is desirable that the processing devices of two lines are disposed away from each other in the chip to avoid some defect to cause errors to both lines.
Accordingly, in the logic circuit according to this embodiment, the processing device of the A line is arranged at the left side of the chip and the processing device of the B line is arranged at the right side of the chip in the drawing. The comparison device (corresponding to the comparison device 20 in Figure 3) and the common line external I/F (corresponding to the network I/F circuit 23 and the system bus I/F circuit 22 in Figure 3) are arranged at the central portion between the processing devices, so that the logic circuits of A and B lines are separated from each other. Moreover, the layout inside the processing device of the B line is provided such that top and bottom are reversed as compared to the layout inside the processing device of the A line, so that the distance between the identical logic circuits of A and B lines is maximized. (It is desirable that the distance is maximized, but the distance does not need to be always maximized in a precise sense.) The layout of the input/output pad (corresponding to the input/output pad region 106 in Figure 2C) is closely related to the layout of the logic circuit. In this embodiment, an input/output pad of a signal relating to the memory I/F of the A line (corresponding to the high-speed memory I/F circuit 13A in Figure 3) is arranged at the left side of the chip; an input/output pad of a signal relating to the memory I/F of the B line (corresponding to the high-speed memory I/F circuit 138 in Figure 3) is arranged at the right side of the chip; an input/output pad of a signal relating to the other external I/F of the A line (corresponding to the external bus I/F circuit 14A in Figure 3) is arranged at the lower left side of the chip; and an input/output pad of a signal relating to the other external I/F of the B line (corresponding to the external bus I/F circuit 148 in Figure 3) is arranged at the upper right side of the chip. In short, the signals of A line and the signals of B line are provided on the opposing corners (approximately opposing corners) on the outer periphery of the chip. In addition, input/output pads of signals relating to the common line external I/F (corresponding to the external I/F circuit 22 in Figure 3) are arranged at the upper side and the lower side of the chip to separate the signals of the A line from the signals of the B line. In the present invention, the layout of the I/F is important. Specifically, it is essential that the I/F signals of the A line and the I/F signals of the B line are provided on the opposing corners or approximately opposing corners, and the signals of the common line are provided to separate the I/F signals of the A line from the I/F signals of the B line. The specific number of signals in each I/F, the specific position of each I/F, and the specific arrangement of signals inside each I/F are not described here.
Incidentally, the direction of the layout such as the right, left, upper, or lower side of the chip is a relative direction, and the present invention is not limited thereto.
(0031] When the input/output pad is actually disposed( a power source, a reserve pad for diagnostic function and the like become a constraint on the design of the input/output pad. When there are some constraints on the layout of the input/output pad, it is difficult in reality to provide all signals on the input/output pads positioned at opposing corners across the center point of the chip. In the present invention, it is not required that the signals be arranged on the input/output pads at the opposing corners in a precise sense. It is only required that the signals of two lines be arranged at approximately opposing corners. For example, the arrangement of signals can be changed within each I/F as long as each I/F has an opposing corners arrangement.
[0032] Figures 13A and 13B are illustrations for explaining the arrangement of the external pins of the LSI 10 according to this embodiment. Figure 13A shows the arrangement of the pins from directly above of the LSI 10 as viewed from an observing point outside the LSI 10 shown in Figure l3B. In this embodiment, no signal pins are provided at the central portion of the package, and a space region is provided at the central portion of the package. The arrangement of the external pins is similar to the layout of the logic circuit and the arrangement of the input/output pad in the LSI chip shown in Figure 12.
An input/output pin of a signal relating to the memory I/F of the A line is arranged at the left side of the package (at the position opposite to the memory I/F signal of the A line in Figure 12); an input/output signal pin of a signal relating to the memory I/F of the B line is arranged at the right side of the package (at the position opposite to the memory I/F signal of the B line in Figure 12); an input/output signal pin of a signal relating to the other external I/F of the A line is arranged at the lower left side of the package (at the position opposite to the external I/F signal of the A line in Figure 12); and an input/output signal pin of a signal relating to the other external I/F of the B line is arranged at the upper right side of the package (at the position opposite to the external I/F signal of the B line in Figure 12). In short, the signals of the A line and the signal pins of the B line are provided on the opposing corners on the outer periphery of the package.
In addition, input/output pins of signals relating to the common line external I/F are arranged at the upper side and lower side of the package (at the positions opposite to the common line external I/F signals in Figure 12) to separate the signal pins of the A line from the signal pins of the B line. In the present invention, the layout of the I/F is important. Specifically, it is essential that the I/F signal pins of the A line and the I/F signal pins of the B line are provided on the opposing corners across the central point of the package, and the common line signal pins are provided to separate the I/F signal pins of the A line from the I/F signal pins of the B line.
The specific number of signal pins in each I/F, the specific position of each I/F, and the specific layout of signal pins inside each I/F are not described here.
Incidentally, the direction of the layout such as the right, left, upper, or lower side of the package is a relative direction, and the present invention is not limited thereto.
[0033] When the signal pins are actually disposed, a power source pin, a reserve pin for diagnostic function and the like become a constraint on the design of the package.
When there are some constraints on the arrangement of the pins, it is difficult in reality to provide all signal pins on opposing corners across the center point of the package. In the present invention, it is not required that the pins be arranged on the opposing corners in a precise sense. It is only required that the pins of two lines be arranged on approximately opposing corners. For example, the arrangement of signal pins can be changed within each I/F as long as each I/F has an opposing corners arrangement.
[0034] Figure 14 shows the arrangement of parts on an electronic circuit board 30 including the LSI 10 and the external devices according to this embodiment. The high-speed memory I/F circuits 13A and 133 (see Figure 3) provided in the memory I/F signal pin regions of the A and B lines of the fail-safe LSI 10 are connected to RAM-Al (1311A), RAM-A2 (1312A), RAM-Bi (13113), and RAM-B2 (13123), and the external bus I/F circuits 14A and 143 (see Figure 3) are connected to RON-A (141A) and RON-B (1413) . The system bus I/F circuit 22 (see Figure 3) of the fail-safe LSI 10 is connected to a system bus bridge LSI 221, and the network I/F circuit 23 (see Figure 3) is connected to a network physical layer LSI 231. The black circles shown at the corners of the squares indicating the external devices are index marks of semiconductor parts, which indicate the direction where the parts are mounted. Similarly to the arrangement of the signal pins, the arrangement of the devices connected to the A line is provided such that top and bottom are reversed as compared to the arrangement of the devices connected to the B line. The normal/abnormal discrimination signal outputted from the comparison device 20 (see Figure 3) is connected to a state notifying connector 2000 to notify the state to the outside of the electronic circuit board 30. A signal outputted from the system bus bridge LSI 221 is connected to a system bus connector 2210 to deal with a bus signal on a board that is different from the electronic circuit board 30. A signal outputted from the network physical layer LSI 231 is connected tb a network connector 2310 to deal with a network signal on a board that is different from the electronic circuit board 30. The signal pin relating to the network I/F circuit 23 is arranged at the upper side of the LSI 10, and the signal pin relating to the system bus I/F circuit 22 is arranged at the lower side of the LSI 10 according to this embodiment. Accordingly, the wiring can be distributed to each external circuit from each I/F on the board without going the long way around and without congestion. Thus, the design cost for the board and the performance can be favorable.
[0035) A region 300A (a hatched region in the drawing) including a signal pin region relating to the high-speed memory I/F circuit l3A of the LSI 10, RAM-Al (1311A), and RAM-A2 (l3l2A); and a region 300B (a hatched region in the drawing) including a signal pin region relating to the high-speed memory I(F circuit l3B of the LSI 10, RAM-BI (l3llB), and RAM-B2 (1312B) have a power-supply voltage that is different from that of other regions in the electronic circuit board 30 in Figure 14.
Specifically, the power-supply voltage of the high-speed memory I/F (see the numeral numbers 13A and 13B in Figure 3) is 2.5 V, and the power-supply voltage of other I/F is 3.3 V. In this embodiment, the regions having different voltages can be separated into right and left.
Accordingly, the operation of the high-speed RAM is minimally affected by the noise caused by the operation of the high-speed RAM of the opposite line. By arranging the I/F having the same function of two lines at opposing corners, the mutual interference can be minimized irrespective of the power-supply voltage of the I/F or the types of the regions having different voltages. An electronic device including the electronic circuit board mounting the LSI 10 and the external devices can be used as an electronic device for railways. At this time, the LSI 10 serves as a fail-safe LSI for railways.
[0036] A second embodiment of the present invention will be explained below with reference to Figures 15 to 18. When a pin multiplex is set in the fail-safe LSI, the pin multiplex between signals relating to the processing devices of two lines or between signals of the common line is a matter to be dealt with by the arrangement of the external I/F as described in the first embodiment.
It is only required that signals relating to the processing devices of two lines be provided at opposing corners across the LSI. However, with regard to the pin multiplex between the signals relating to the processing devices of two lines and the signals of the common line, the arrangement as described below in this second embodiment is preferable.
[0037] Figure 15 shows the internal arrangement of the fail-safe LSI and the external devices according to the second embodiment. The arrangement shown in Figure 15 is different from the arrangement shown in Figure 3 according to the first embodiment in that general-purpose input/output circuits 24A and 243 and pin function selectors 254k and 253 are provided; signals relating to the general-purpose input/output circuits 15A and 156 are not directly connected to the outside of the LSI 10; and signals relating to the general-purpose input/output circuits 24A and 246 of the common line are selectively connected to the outside by the pin function selectors 25A and 258, (i.e., pin multiplexed). In other words, the general-purpose input/output circuits 2471 and 248, and pin function selectors 25A and 258 connected to two general-purpose input/output circuits ISA and 24A or two general-purpose input/output circuits 158 and 248 for selection are added to the arrangement according to the embodiment shown in Figure 3.
[0038] Figure 16 shows the internal arrangement of the general-purpose input/output circuit 1571, the general-purpose input/output circuit 24A, and the pin function selector 2571 according to the second embodiment. The general-purpose input/output circuit 158, the general-purpose input/output circuit 248, and the pin function selector 258 have the same arrangement. Similarly to the first embodiment, the general--purpose input/output circuit ISA includes a general-purpose 10 read data register (PIORRA) 15171, general-purpose 10 write data register (PIOWRA) 152A, general-purpose 10 function setting register (PIOFRA) 15371. These registers read and write values with use of the processor 1171 (see Figure 15) via the internal bus 1271. The general-purpose input/output circuit 2471 includes a general-purpose 10 read data register (PIORRO1) 24171, general-purpose 10 write data register (PIOWRC1) 24271, general-purpose 10 function setting register (PIOFRO1) 243A. These registers read and write values by simultaneous access from the processors hA and uS via the common line internal bus l2A.
[0039} The pin function selector 25A is composed of a general-purpose 10 selection register (PIOSRA) 251A and a selection circuit 252A. A circuit (not shown) for register access of PIOSRA is provided in the general-purpose input/output circuit iSA to read and write values by the processor hA via the internal bus 12A. PIORRA and PIOWRA have a data width of eight bits and PIOFRA has a data width of one bit, which are connected to the selection circuit 252A. PIORRC1 and PIOWRC1 have a data width of eight bits and PIOFRC1 has a data width of one bit, which are connected to the selection circuit 252A. PIOSRA has a data width of one bit. The function of the general-purpose input/output circuit 24A is selected when the value is zero, and the function of the general-purpose input/output circuit l5A is selected when the value is one. When the function of the general-purpose input/output circuit 24A is selected, PIORRC1 and PIOWRC1 are connected to an external signal line 230A of the LSI 10 via the input/output buffer 252A. The direction of input/output is determined in accordance with the value of PIOFRC1. When the function of the general-purpose input/output circuit iSA is selected, PIORRA and PIOWRA are connected to the external signal line 250A of the LSI 10 via the input/output buffer 252A.
The direction of input/output is determined in accordance with the value of PIOFRA.
[0040] Figure 17 is an illustration for explaining the layout of the logic circuit and the arrangement of the input/output pad in the LSI chip 100 according to the second embodiment. The arrangement shown in Figure 17 is different from the arrangement shown in Figure 12 in that a pin function selector for switching an external I/F of the A line and an external I/F of the common line is provided at the lower left side of the chip; a pin function selector for switching an external I/F of the B line and an external I/if' of the common line is provided at the upper right side of the chip; an input/output pad relating to a signal for switching by the pin function selector between an input/output pad of a signal relating to the external I/F of A line and an input/output pad of a signal relating to the external I/F of common system at the lower left side is provided (i.e., A line/common line mixed region); and an input/output pad relating to a signal for switching by the pin function selector between an input/output pad of a signal relating to the external I/F of B line and an input/output pad of a signal relating to the external I/F of common system at the upper right side is provided (i.e., B line/common line mixed region).
[0041] Figure iSA is an illustration for explaining the arrangement of the external pins of the LSI 10 according to the second embodiment. The arrangement shown in Figure iSA is different from the arrangement shown in Figure 13A in that an input/output pin relating to a signal for switching by the pin function selector between an input/output pin of a signal relating to the external I/F of A line and an input/output pin of a signal relating to the external I/F of common system at the lower left side is provided (i.e., A line/common line mixed region); and an input/output pin relating to a signal for switching by the pin function selector between an input/output pin of a signal relating to the external I/F of B line and an input/output pin of a signal relating to the external I/F of common system at the upper right side js provided (i.e., B line/common line mixed region). When the pin multiplex of the signals relating to the processing devices of two lines and the signals of common line is performed, the symmetry of the signals of A and B lines can be maintained due to the pin arrangement according to the second embodiment.
[0042] Figures 19A, 19B, and 19C show the outline of the fail-safe LSI having a physical structure different from that according to the first embodiment. Figure 19A shows the cross-section of the fail-safe LSI. An external I/F signal of an LSI chip and a power source are connected to a package board via chip bumps 107. Figure l9B is an overhead view of the fail-safe LSI from which a sealing member is removed. The LSI chip 100 is arranged on the package board so that its circuit surface faces downwardly, and is connected to the package board via the chip bumps 107. Figure 19C shows the circuit surface of the LSI chip. The processing device of the B line is arranged at the left side of the LSI chip, the processing device of the A line is arranged at the right side, and the circuit of the common line is arranged at the center.
With regard to the external pins of the LSI package, the signal pins of the A line are arranged at the left side, the signal pins of the B line are arranged at the right side, and the signal pins of the common line are arranged vertically, similarly to the first embodiment. When the chip is mounted on the rear face shown in the drawing, the signal arrangement of the LSI chip is provided by left-right reversal of the signal arrangement of LSI package.
[0043) Figures 20A, 20B, and 20C are illustrations for explaining the arrangement of the external pins in the fail-safe LSI having the external pin structure different from that according to the first embodiment. Figure 20A shows the arrangement when the external pins are not provided at the center of the package as compared to the first erabodiment. The signal pins of the A line is arranged at the left side of the LSI, the signal pins of the B line are arranged at the right side, and the signal pins of the common line are arranged at the upper and lower sides. In this drawing, power-supply pins (including ground pins), which are not I/F signals, are indicated by black circles. Incidentally, the number of entire pins and the arrangement and number of power-supply pins are varied depending on the design of the package. Figure 20A merely shows the positional relationship between the signal pins of A line, B line, and common line. In Figure 20B, the external pins are provided at the center of the package. All external pins provided at the center are power-supply pins. The signal pins of the A line is arranged at the left side of the LSI, the signal pins of the B line are arranged at the right side, and the signal pins of the common line are arranged at the upper and lower sides. Since there are no signal pins at the center, the signal pins of A and B lines are separated by the signal pins of the common line similarly to the arrangement shown in Figure 20A. In Figure 20C, the external pins including signal pins are provided at the center of the package. The signal pins of the A line is arranged at the left side of the LSI, the signal pins of the B line are arranged at the right side, and the signal pins of the common line are arranged at the upper and lower sides. By arranging the signal pins of the common line at the center, the signal pins of A and B lines are separated by the signal pins of the common line similarly to the other arrangements.
Reference Signs List [0044) fail-safe LSI ilA, 118 processor l2A, 12B line internal bus 13A, 138 high-speed memory interface circuit 14A, 148 external bus interface circuit lSA, 158 general-purpose input/output circuit comparison device 21 common line internal bus 22 system bus intert ace circuit 23 network interface circuit 25A, 258 pin function selector electronic circuit board fail-safe LSI chip normal/abnormal discrimination signal 201 alternating signal generator 202 bus comparator 203 duplex control circuit 204 comparison discrepancy signal
GB1211339.5A 2009-12-28 2010-12-21 LSI, fail-safe LSI for railways, electronic device, and electronic device for railways Withdrawn GB2489353A (en)

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JP2009296659A JP5386342B2 (en) 2009-12-28 2009-12-28 LSI, Fail-safe LSI for railway, Electronic equipment, Electronic equipment for railway
PCT/JP2010/072953 WO2011081052A1 (en) 2009-12-28 2010-12-21 Lsi, fail-safe lsi for railways, electronic device, and electronic device for railways

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JPH07295844A (en) * 1994-04-28 1995-11-10 Hitachi Ltd Fail-safe controller and train controller
JP2001249701A (en) * 2000-03-08 2001-09-14 Nippon Signal Co Ltd:The Duplex information processor
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JP2005049967A (en) * 2003-07-30 2005-02-24 Toshiba Corp Failsafe processor and protection control unit for railroad
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JP2006031727A (en) * 2005-08-17 2006-02-02 Hitachi Ltd Fail-safe controller

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JP4521602B2 (en) * 2005-06-06 2010-08-11 ルネサスエレクトロニクス株式会社 Multimode high frequency circuit
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JPS63271540A (en) * 1987-04-28 1988-11-09 Railway Technical Res Inst Fail-safe type computer device
JPH07295844A (en) * 1994-04-28 1995-11-10 Hitachi Ltd Fail-safe controller and train controller
JP2001249701A (en) * 2000-03-08 2001-09-14 Nippon Signal Co Ltd:The Duplex information processor
JP2002135963A (en) * 2000-10-19 2002-05-10 Nissin Electric Co Ltd Protective relay
JP2005049967A (en) * 2003-07-30 2005-02-24 Toshiba Corp Failsafe processor and protection control unit for railroad
JP2005123591A (en) * 2003-09-25 2005-05-12 Rohm Co Ltd Semiconductor device and electronic apparatus packaging the same
JP2006031727A (en) * 2005-08-17 2006-02-02 Hitachi Ltd Fail-safe controller

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CN102110033B (en) 2015-04-15
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CN102110033A (en) 2011-06-29
WO2011081052A1 (en) 2011-07-07
GB201211339D0 (en) 2012-08-08

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