CN102110033B - LSI, fail-safe LSI for railways, electronic device, and electronic device for railways - Google Patents

LSI, fail-safe LSI for railways, electronic device, and electronic device for railways Download PDF

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Publication number
CN102110033B
CN102110033B CN201010621634.0A CN201010621634A CN102110033B CN 102110033 B CN102110033 B CN 102110033B CN 201010621634 A CN201010621634 A CN 201010621634A CN 102110033 B CN102110033 B CN 102110033B
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China
Prior art keywords
external interface
interface circuit
input
lsi
systems
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CN201010621634.0A
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Chinese (zh)
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CN102110033A (en
Inventor
中三川哲明
岛村光太郎
作山秀夫
竹原刚
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Hitachi Ltd
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Hitachi Ltd
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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B61—RAILWAYS
    • B61L—GUIDING RAILWAY TRAFFIC; ENSURING THE SAFETY OF RAILWAY TRAFFIC
    • B61L27/00—Central railway traffic control systems; Trackside control; Communication systems specially adapted therefor
    • B61L27/50—Trackside diagnosis or maintenance, e.g. software upgrades
    • B61L27/57—Trackside diagnosis or maintenance, e.g. software upgrades for vehicles or trains, e.g. trackside supervision of train conditions
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B9/00—Safety arrangements
    • G05B9/02—Safety arrangements electric
    • G05B9/03—Safety arrangements electric with multiple-channel loop, i.e. redundant control systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11898—Input and output buffer/driver structures
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/007—Fail-safe circuits
    • H03K19/0075—Fail-safe circuits by using two redundant chains
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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    • H01L2027/11874—Layout specification, i.e. inner core region
    • H01L2027/11879—Data lines (buses)
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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Abstract

The present invention provides an LSI, a fail-safe LSI for railways, an electronic device, and an electronic device for railways. Conventional fail-safe LSIs have been used for the placement of processors and comparators in chips, but have not been used for the placement of package signal pins. The adaptability of fail-safe LSIs to various peripheral circuits and high speed memory has also not been considered. The technical scheme of the present invention is characterized in that: outputs from two processors are matched, an integrated internal interface is connected to a common line internal bus, and a plurality of external interface circuits are connected to the common line internal bus. Furthermore, signal pins corresponding to two systems are disposed at opposite corners of a package, and signal pins corresponding to a common line are disposed therebetween.

Description

LSI, railway fail safe LSI, electronic installation, the sub-device of railway power supply
Technical field
The semi-conductor chip that the present invention relates to microprocessor built-in, the signal system particularly in railway needs the semi-conductor chip used in the control system of high security like that.
Background technology
Signal system in railway needs in the control system of high security like that; thought according to " fail safe (Off エ mono-Le セ mono-Off; fail safe) " carrys out designing apparatus; even if make when intrasystem equipment there occurs abnormal; also can not make the state that system is in jeopardy, and can stop under the state of safety.Although reliably the exception of checkout equipment is required in the realization of fail safe, employing in microprocessor-based control system, mutually monitoring the exception in measurement processor portion by carrying out multiplexed (multiplex) to processor.
In recent years, highly integrated along with semiconductor, built-in two processors in a LSI chip, thus make it possible to carry out action and compare.Patent documentation 1 etc. describes this manner of comparison.Non-patent literature 1 describes the example being in fact made 1 chip failure protection LSI.
Patent documentation 1: Japanese Unexamined Patent Publication 6-161798 publication
Non-patent literature 1:K.Shimamura etc.: " A Single-Chip Fail-SafeMicroprocessor with Memory Data Comparison Feature ", IEEE 12 thpacificRim International Symposium on Dependable Computing (PRDC ' 06) (18-20 day in Dec, 2006).
Recently, the highly integrated progress more of semiconductor, so far, can be built in by the peripheral circuit in addition in chip in chip.In order to effectively utilize the performance of the processor of high speed motion, need at high speeds jumbo storer in addition.
In order to make multiple peripheral circuit and high speed outer storer etc. can be connected on chip, need the signal pin number of the encapsulation increasing chip and built-in chip.Due to the operating frequency also high speed of peripheral circuit, the difference of wire delay and electrical specification when just needing to consider signal pin configuration.
On the other hand, in the prior art, from the viewpoint guaranteeing reliability, the configuration of processor in chip and comparator circuit has been mentioned, but, the signal pin configuration of encapsulation and the parts of device substrate are configured, does not mention.And the peripheral circuit that the outside of chip connects also only exists a kind of general bus, there is no the correspondence considered multiple peripheral circuit and high speed outer storer.
Usually, the built-in LSI of processor, in order to keep versatility in purposes, an external signal pin keeping multiple function, carrys out handoff functionality as required, the situation with the signal pin setting so-called pin multiplexing is also a lot.Thus, although can the limited signal pin of usage quantity effectively, for the pin multiplexing in fail safe LSI in the prior art, but do not consider.
Summary of the invention
The object of the invention is to comprise the peripheral circuit of LSI chip and make security and high performance and deposit.
Make security and high performance to comprise peripheral circuit and deposit, the position that the diagonal angle signal pin relevant to 2 systems comprising processor being configured in encapsulation namely mutually leaves most, and the signal pin that configuration is relevant to common system between the signal pin that 2 systems are relevant.When the peripheral circuit of common system has 2, the signal pin that configuration is relevant to the peripheral circuit of every 1 on the region between the signal that 2 systems with 2 positions are relevant.
Invention effect
Due to by the signal pin relevant to common system of configuration between the signal pin that 2 systems are relevant, the distance of the signal pin relevant to 2 systems can be made to become maximum, therefore, it is possible to make to cause the possibility of 2 systems malfunction simultaneously to become less by single main causes such as electromagnetic noises.
Accompanying drawing explanation
Fig. 1 is synoptic diagram of the present invention.
Fig. 2 is the physical structure of fail safe LSI.
Fig. 3 is the internal structure figure of fail safe LSI.
Fig. 4 is the synoptic diagram of the distribution that common system internal bus connects.
Fig. 5 is the internal structure figure of common system internal bus.
Fig. 6 is the sequential chart of the action for illustration of internal bus.
Fig. 7 is the internal structure figure of comparison means.
Fig. 8 is the action diagram of alternating signal generator.
Fig. 9 is the internal structure figure of bus comparer.
Figure 10 is the internal structure figure of two-way multiplexing control circuit.
Figure 11 is the internal structure figure of universal input output circuit.
Figure 12 is the schematic diagram configured for illustration of the logic circuit arrangements in LSI chip and input/output pads (パ Star De).
Figure 13 is the schematic diagram configured for illustration of the external terminal of LSI.
Figure 14 is the parts arrangement plan on electronic circuit board.
Figure 15 is the internal structure figure of the fail safe LSI of the second embodiment.
Figure 16 is the universal input output circuit of the second embodiment and the internal structure figure of pin function selector switch.
Figure 17 is the schematic diagram for illustration of the logic circuit arrangements in the LSI chip of the second embodiment and input/output pads configuration.
Figure 18 is the schematic diagram configured for illustration of the external terminal of the LSI of the second embodiment.
Figure 19 is the synoptic diagram of the fail safe LSI with different physical arrangements.
Figure 20 is the schematic diagram configured for illustration of the external terminal of the fail safe LSI with different external terminal structures.
Reference numeral explanation
10 fail safe LSI
11A, 11B processor
Internal bus in 12A, 12B system
13A, 13B high-speed memory interface circuit
14A, 14B external bus interface circuitry
15A, 15B universal input output circuit
20 comparison means
21 common system internal buss
22 system bus interface circuits
23 network interface circuits
25A, 25B pin function selector switch
30 electronic circuit boards
100 fail safe LSI chips
200 normal abnormality discrimination signal
201 alternating signal generators
202 bus comparers
203 two-way multiplexing control circuits
204 more inconsistent signals
Embodiment
According to Fig. 1 to Figure 14, the first embodiment of the present invention is described.Fig. 1 is the schematic diagram that summary of the present invention is described.In a LSI 10,2 systems have carried the treating apparatus of the identical formation comprising processor and external interface (being I/F below) circuit.In the present embodiment, 2 systems are called A system and B system.Respective treating apparatus has more than one processor and more than one exterior I/F circuit, and they are all connected to the internal bus in each system etc.Because the result of the processor in each system etc. appears on internal bus, if the signal of comparison means to both buses be therefore connected with B internal system bus by A internal system bus is compared, then can know that the treating apparatus of 2 systems has carried out identical action.By normal abnormality discrimination signal 200 by represent when both have carried out same action for normal, when both have carried out different action for abnormal signal outputs to the outside of fail safe LSI chip 100.Under normal conditions, namely when the internal bus of 2 systems outputs identical signal, comparison means outputs to common system internal bus by selecting one individual.For from common system internal bus to the output for the treatment of apparatus, comparison means outputs on both of the internal bus of 2 systems.By such bus single line, action timing (timing) of 2 systems can not be staggered, thus same treatment is continued.Common system external interface circuit is connected on common system internal bus by multiple.On the exterior I/F that respective external device (ED) can be connected to the identical formation of 2 systems and common system exterior I/F.Like this, by the output of contrast from 2 processors, the outside of chip will need not be directly outputted to as prior art by the internal interface of single line, by making just multiple external interface circuit to be connected to this common system internal bus once be connected with common system internal bus, thus multiple peripheral circuit can be connected, the performance that can obtain LSI improves.
In other words, owing to making it possible to built-in multiple external interface by arranging common system internal bus, therefore make it possible to multiple external device (ED) to be directly connected on chip.
Fig. 2 is the schematic diagram of the summary of the physical arrangement of the fail safe LSI representing the present embodiment.Fig. 2 (a) is the schematic diagram in the cross section representing fail safe LSI 10; exterior I/F the signal of LSI chip 100 and power supply are connected to base plate for packaging 101 by bonding wire (ボ Application デ イ Application グ ワ イ ヤ) 103, and the solder ball 104 of installing via the bottom at base plate for packaging 100 is connected with outside.The top of LSI chip 100 is protected by encapsulant 102.Fig. 2 (b) is the vertical view of the state remove encapsulant 102 from fail safe LSI 10 after; it represents that LSI chip 100 is by being configured in circuit face towards top on base plate for packaging 101, and is connected on base plate for packaging 101 by bonding wire 103.Fig. 2 (c) is the schematic diagram of the circuit face representing LSI chip 100, and it represents that LSI chip 100 is by defining the logical circuit installation region 105 of the logical circuits such as the treating apparatus of 2 systems and comparison means and forming for the input/output pads region 106 of connection signal and power supply.In the present embodiment, be configured with the treating apparatus of A system in the left side of LSI chip 100, be configured with the treating apparatus of B system on right side, be configured with the circuit of common system in central authorities.Configure about in chip, aftermentioned.
Fig. 3 is the Inner Constitution of fail safe LSI and the schematic diagram of external unit that represent the present embodiment.Fail safe LSI has processor 11A and 11B of 2 systems, internal bus 12A and 12B of 2 systems; as 2 its exterior I/F, there is high-speed memory I/F circuit 13A and 13B, external bus I/F circuit 14A and 14B, universal input output circuit 15A and 15B.As respective external device (ED), high-speed memory I/F circuit 13A and 13B is connected to external RAM 131A and 131B, external bus I/F circuit 14A and 14B is connected to external ROM 141A and 141B.In addition, fail safe LSI 10 has comparison means 20 and common system internal bus 21, as common system exterior I/F, has system bus I/F circuit 22 and network I/F circuit 23.As respective external device (ED), system bus I/F circuit 22 is connected to system bus bridge 221, network I/F circuit 23 is connected to networked physics layer 231.Normal abnormality discrimination signal 200 is exported from comparison means 20.
Fig. 4 is the schematic diagram of the summary representing the distribution that the common system internal bus 21 of the present embodiment connects.Common system internal bus 21 is connected to the I/F signal 232 between I/F signal 222 between I/F signal 205 between comparison means 20 and system bus I/F circuit 22 and network I/F circuit 23.I/F signal 205,222,232 are separated into for read/write is required to be supplied to the master port 205M of internal bus respectively, 222M, 232M and for accepting the auxiliary port 205S required from the read/write of internal bus, 222S, 232S.In the present embodiment, although 3 modules that common system internal bus 21 connects all have master port and auxiliary port, usually, only there is any one port and be also fine.The number of modules that internal bus 12A with 12B of 2 systems is only be connected is different, owing to having the Structure and function same with common system internal bus 21, because omitted herein detailed description, but the I/F such as and between high-speed memory I/F circuit 13A and 13B only has auxiliary port.
Fig. 5 is the Inner Constitution of the common system internal bus 21 representing the present embodiment and the schematic diagram of the details of distribution that connects.In Figure 5, in order to make the flow direction of signal easily separate, master port and auxiliary port is separately shown.Common system internal bus 21 is formed by bus control circuit 211 with to the distribution of each port.Bus control circuit 211 is made up of request control circuit 212 and response limiting circuit 213.Each master port by address (output), write data (output), order (outputs), authorize (グ ラ Application ト) (input), read data (input), effective (バ リ Star De) (input) these 6 kinds of signals form.Each auxiliary port by address (input), write data (input), order (input), the line is busy (PVC ジ mono-) (output), port sequence number (output), read data (output), effective (output) these 7 kinds of signals are formed.The direction of input and output is facing to bus control circuit 211 from each port.Request control circuit 212 mediates the transmission requirement from each master port, is decoded address, selects the auxiliary port exporting destination.Bus reconciliation and geocoding are known technology, and detailed description is omitted.The read data that response limiting circuit 213 mediates from each auxiliary port returns requirement, and outputs to the master port requiring source.Response limiting circuit 213 has the impact damper (buffer) (not diagram) of the read data for temporarily keeping each auxiliary port, returning requirement and need not wait for from each auxiliary port.
Fig. 6 is the sequential chart of the action for illustration of common system internal bus 21.In figure 6, the action of the write and read of the data between master port 205M and auxiliary port 222S is represented.Common system internal bus 21 and the clock signal synchronization shown in top of figure, transmit data in every 1 clock period.When clock period i from comparison means 20 using represent the address of the register of system bus I/F circuit 22 inside as address 2051M, represent 4 bytes are write (バ イ ト ラ イ ト) coding as writing data 2052M, order 2053M grant bus control circuit 211 time, request control circuit 212 judges the engaged condition not from the request of other master ports and the auxiliary port of request distribution destination, (ア サ mono-ト is in effectively by making mandate 2054M, assert), notice request source receives requirement.Meanwhile, request control circuit 212 by address 2221S, write data 2222S, order 2223S output to request distribution destination auxiliary port 222S.The system bus I/F circuit 22 that auxiliary port 222S connects, according to accepted address, is written to the register in module by writing data.
When clock period j using represent the address of the register of system bus bridge 221 inside that system bus I/F circuit 22 connects as address 2051M, represent that the coding that 4 bytes are write grants bus control circuit 211 as order 2053M time, request control circuit 212 judges the state of bus, by making mandate 2054M be in effectively (assert), notice request source accepts requirement.Meanwhile, address 2221S, order 2223S are outputted to the auxiliary port 222S of request distribution destination by request control circuit 212.The system bus I/F circuit 22 that auxiliary port 222S connects, according to accepted address, will be read requirement and be supplied to system bus bridge 221.At clock period j+1, system bus I/F circuit 22 makes that the line is busy, and 2227S is in effectively (assert), will not accept the situation notice request control circuit 212 of other request.When clock period J+2 ready return from system bus bridge 221 read data, the expression request as port sequence number 2228S is required that the coding of the port 205M in source and read data 2225S output to response limiting circuit 213 together with effective 2226S by system bus I/F circuit 22.Response limiting circuit 213, to the port 205M represented by port sequence number 2228S, exports read data 2055M and effective 2056M.
Like this, use common system internal bus 21, carry out transmitting in the data of connected intermodule.Especially, according to this bus, by Request Control is separated with response limiting, even if from a module read require in, the data of other intermodules also can not be hindered to transmit, realize so-called separate type issued transaction (ス プ リ Star ト ト ラ Application ザ Network シ ヨ Application), therefore, even if there is the module of carrying out a large amount of DMA data transmission as network I/F and system bus I/F simultaneously, also can not occupy bus, thus avoid bus throughput to reduce.Because the distribution between each port and bus control circuit can become 1 to 1, even if therefore module is placed in physically separated position, the impact of the wire delay that the responsiveness of bus entirety applies also can be made to become minimum.
Fig. 7 is the schematic diagram of the Inner Constitution of the comparison means 20 representing the present embodiment.Comparison means 20 is made up of alternating signal generator 201, bus comparer 202, two-way multiplexing control circuit 203, and is connected with A internal system bus 121A, B internal system bus 121B, common system internal bus 21.
Fig. 8 is the schematic diagram of the action of the alternating signal generator 201 representing the present embodiment.The more inconsistent signal 204 that alternating signal generator 201 exports according to bus comparer 202, exports normal abnormality discrimination signal 200.When normal or abnormal and so on state is outputted to outside by the level signal of 1; the fault mode of ON (connection) or OFF (disconnection) is fixed on owing to not avoiding signal level; therefore in railway signaling system etc.; according to prior art, use and the situation repeating ON, OFF with certain frequency is set to normally, state is in addition set to abnormal " alternating signal ".In the present embodiment, alternating signal generator 201 at more inconsistent signal 204 for unanimously namely representing output frequency signal in normal situation, when inconsistent namely represent abnormal outputs level signals.Formation logic due to alternating signal is known, and therefore detailed description is omitted.
Fig. 9 is the schematic diagram of the Inner Constitution of the bus comparer 202 representing the present embodiment.The signal that the signal exported from A internal system bus 121A and B internal system bus 121B export compares by bus comparer 202 all the time, when detecting inconsistent, connects (ON) more inconsistent signal 204.The data compared are address 1211MA and 1211MB, write data 1212MA and 1212MB, order 1213MA and 1213MB, the line is busy 1217SA and 1217SB, port sequence number 1218SA and 1218SB, read data 1215SA and 1215SB, effectively 1216SA and 1216SB, even if when detecting inconsistent at the same time, the trigger of bus comparer 202 inside is also set, and more inconsistent signal 204 becomes ON (conducting) former state.And, although known the misoperation in order to bus comparer self be detected, technology comparer is multiplexed, intentionally produce again mistake on each certain hour, in the present embodiment, the logic of the comparer of high reliability is as known, and detailed description is omitted.
Figure 10 is the schematic diagram of the Inner Constitution of the two-way multiplexing control circuit 203 representing the present embodiment.As long as two-way multiplexing control circuit 203 bus comparer 202 does not detect more inconsistent, just the signal exported from A internal system bus 121A is outputted to common system internal bus 21.That is, using address 1211MA, write data 1212MA, order 1213MA, the line is busy 1217SA, port sequence number 1218SA, read data 1215SA, effectively 1216SA as address 2051M, write data 2052M, order 2053M, the line is busy 2057S, port sequence number 2058S, read data 2055S, effectively 2056S export.When detecting more inconsistent, the output of order 1213MA and effective 1216SA is suppressed by more inconsistent signal 204, and common system internal bus 21 can not detect the distribution of request and response, therefore, prevents and outputs to common system internal bus 21 by becoming inconsistent data.
The signal exported from common system internal bus 21 is simultaneously sent to A internal system bus 121A and B internal system bus 121B.That is, authorize 2054M, read data 2055M, effectively 2056M, address 2051S, write data 2052S, order 2053S to be delivered to mandate 1214MA and 1214MB, read data 1215MA and 1215MB, effectively 1216MA and 1216MB, address 1211SA and 1211SB respectively, write data 1212SA and 1212SB, order 1213SA and 1213SB.Like this, by two-way multiplexing control circuit 203, from common system internal bus 21, see that A internal system bus 121A and B internal system bus 121B is as 1 bus (port 205), the action timing of A internal system bus 121A and B internal system bus 121B is not also staggered, and the process in the treating apparatus of therefore 2 systems is not also staggered.
Processor 11A and 11B is assumed to general microprocessor, as known technology, omission is described.High-speed memory I/F circuit 13A and 13B is assumed to the universal high speed storer of DDR-SDRAM (Double DataRate-Synchronous DRAM) etc., as known technology, omission is described, but, in order to high speed, there is the tendency making external bus that I/F voltage ratio is general lower.Particularly, the I/F voltage of general external bus is the I/F voltage of 3.3V, DDR-SDRAM is 2.5V, needs LSI corresponding with multiple I/F voltage.External bus I/F circuit 14A and 14B is assumed to the external bus of the general microprocessor be made up of chip selection, address, data, read/write gating etc., as known technology, omission is described.
Figure 11 is the schematic diagram of the Inner Constitution of the universal input output circuit 15A representing the present embodiment.Universal input output circuit 15B is also same formation.Universal input output circuit 15A has general purpose I/O read data register (PIORR_A) 151A, general purpose I/O write data register (PIOWR_A) 152A, general purpose I/O function setting register (PIOFR_A) 153A, and these registers are carried out the reading and writing be worth by processor 11A via internal bus 12A.PIORR_A and PIOWR_A has the data width of 8, via inputoutput buffer 154A, is connected with the external signal line 150A of LSI 10.PIOFR_A has the data width of 1, and become data when its value is 0 and export, the value of the upper setting of PIOWR_A is output to external signal line 150A.Become data input when the value of PIOFR_A is 1, the signal level of external signal line 150A is imported into PIORR_A.
Figure 12 is the schematic diagram for illustration of the logic circuit arrangements in the LSI chip 100 of the present embodiment and input/output pads configuration.The treating apparatus of 2 systems, in order to avoid single main cause causes identical mistake in both systems, ites is desirable to leave distance as much as possible in chip and is configured.For this reason, the logic circuit arrangements of the present embodiment, by the treating apparatus in the left side of chip configuration A system, at the treating apparatus of the right side of chip configuration B system, namely central portion configures the exterior I/F of comparison means and common system between, is separated by the logical circuit of A system with B system.And, by the layout in the treating apparatus of B system being set to the transposition up and down of A system, make the distance between the identity logic circuit of A system and B system become maximum.Although the configuration of input/output pads becomes adjacent relation with logic circuit arrangements, but in the present embodiment, configuration makes the left side input/output pads of signal relevant for the memory I/F to A system being in chip, the input/output pads of the signal relevant to the memory I/F of B system is on the right of chip, the input/output pads of the signal relevant to the exterior I/F except A system is in the left lower side of chip, the input/output pads of the signal relevant to the exterior I/F except B system is in the top right-hand side of chip, thus the signal of the signal of A system and B system is configured to the position at diagonal angle in chip periphery.The input/output pads of the signal relevant to common system exterior I/F is configured in the bottom and upper segment of chip, makes the Signal separator by A system and B system.And, in the present invention, arrangement side i.e. each I/F signal of A system and B system of each I/F is configured to diagonal angle respectively, and it is important for being carried out being separated by the signal therebetween with common system, for the details of the concrete signal arrangement in the boundary position of the concrete signal radical of each I/F, the concrete of each I/F, each I/F, do not mention.The left and right of chip, upper and lower and so on direction are also relative, are not limited to the direction shown by the present embodiment.
And in the input/output pads configuration of reality, the reservation pad etc. of such as power supply and diagnostic function, the situation that input/output pads design exists constraint is frequent.When there is constraint in input/output pads configuration, whole signals is configured at the input/output pads of diagonal position relative to the central point of chip, be difficult in reality.Imprecision of the present invention requires the signal configures to the input/output pads of diagonal position, as long as roughly that the signal configures of 2 systems is just passable in the position at diagonal angle.Such as, if putting in order of each I/F unit becomes diagonal angle, also do not hinder even if change configuration between the signal belonging to each I/F.
Figure 13 is the schematic diagram configured for illustration of the external terminal of the LSI 10 of the present embodiment.Figure 13 (a) is that the viewpoint indicated by outward appearance of LSI 10 in Figure 13 (b) is namely from the schematic diagram of the positive upper perspective pin configuration of LSI 10.In the present embodiment, there is no configures signal pins at the central portion of encapsulation, become clear area.External terminal configuration configures same with the logic circuit arrangements in the LSI chip 100 shown in Figure 12 and input/output pads, configuration makes the left side input and output pin of signal relevant for the memory I/F to A system being in encapsulation, the input and output pin of the signal relevant to the memory I/F of B system is in and encapsulates the right, the input and output pin of the signal relevant to the exterior I/F except A system is in the left lower side of encapsulation, the input/output signal of the signal relevant to the exterior I/F except B system is in the top right-hand side of encapsulation, thus the signal pin of the signal of A system and B system is configured to the position at diagonal angle in encapsulation periphery.The input and output pin of the signal relevant to common system exterior I/F is configured in the bottom and upper segment of encapsulation, makes the signal pin of A system with B system be separated.And, in the present invention, arrangement side i.e. each I/F signal pin of A system and B system of each I/F is configured to diagonal angle relative to the central point of encapsulation respectively, and it is important for being carried out being separated by the signal pin therebetween with common system, for the details of the concrete signal pin arrangement in the boundary position of the concrete signal pin number of each I/F, the concrete of each I/F, each I/F, do not mention.Left and right, upper and lower and so on the direction of encapsulation are also relative, are not limited to the direction shown by the present embodiment.
And in the signal pin configuration of reality, the reservation pin etc. of such as power pin and diagnostic function, the situation that package design exists constraint is frequent.When there is constraint in pin configuration, whole signal pins is configured at diagonal position relative to the central point of encapsulation, is difficult in reality.Imprecision of the present invention requires the pin configuration to diagonal position, as long as the position roughly signal pin of 2 systems being configured in diagonal angle is just passable.Such as, if putting in order of each I/F unit becomes diagonal angle, also do not hinder even if then change configuration between the signal pin belonging to each I/F.
Figure 14 is the schematic diagram of the parts configuration represented on the electronic circuit board 30 having carried LSI 10 and external device (ED) of the present embodiment.High-speed memory I/F circuit 13A and 13B of fail safe LSI 10 is connected to RAM-A1 (1311A), RAM-A2 (1312A), RAM-B1 (1311B) and RAM-B2 (1312B), external bus I/F circuit 14A and 14B is connected to ROM-A (141A) and ROM-B (141B).Connected system bus bridge LSI221 on the system bus I/F circuit 22 of fail safe LSI 10, interconnection network Physical layer LSI 231 on network I/F circuit 23.Represent that the stain at the angle of the figure of these external device (ED)s is mark (イ Application デ Star Network ス マ mono-Network) the i.e. symbols in the lift-launch direction of parts differentiating semiconductor device.In the device that the device connected in A system is connected with B system, same with the configuration of signal pin, become up and down and put upside down.The normal abnormality discrimination signal 200 exported from comparison means 20 is connected to state notifying connector 2000, and by the outside of state notifying electronic circuit board 30.The signal exported from system bus bridge LSI 221 is connected to system bus connector 2210, and exchanges bus signals on the substrate separated with electronic circuit board 30.The signal exported from networked physics layer LSI 231 is connected to network connector 2310, and on the substrate separated with electronic circuit board 30 exchange network signal.As in this embodiment, by configuring the signal pin relevant to network I/F circuit 23 in the top of LSI 10, at the signal pin that configuration is below relevant to system bus I/F circuit 22, can on substrate not roundabout and chaotic distribution from each I/F to each external circuit and drawing, therefore, the design cost of substrate and performance all become favourable.
In the electronic circuit board 30 of Figure 14, the region 300B (in figure hatched region) that RAM-B1 (1311B) and RAM-B2 (1312B) have been installed in the region 300A (in figure hatched region) of RAM-A1 (1311A) and RAM-A2 (1312A) and the signal pin region relevant with the high-speed memory I/F circuit 13B of LSI 10 has namely been installed in the signal pin region relevant to the high-speed memory I/F circuit 13A of LSI 10 namely, is the supply voltage region different from region in addition.Particularly, high-speed memory I/F is the supply voltage of 2.5V, and I/F is in addition 3.3V.Like this, different voltage regime can be divided right and left in the present embodiment, therefore, for the noise of the action with high-speed RAM, the impact that the action of the high-speed RAM of the system on opposition side can be made to apply diminishes.And essence of the present invention is, is what kind of supply voltage by whichever I/F or there is several different voltage regime, all the identical function I/F of 2 systems is configured in the position at diagonal angle, thus mutual interference can be made to be minimum.
According to Figure 15 to Figure 18, the second embodiment of the present invention is described.When setting pin multiplexing in as the fail safe LSI of object of the present invention; relate to the pin multiplexing between the signal relevant to the treating apparatus of 2 systems or between the signal of common system; the problem that should solve in the configuration of the exterior I/F addressed in the first embodiment, also can by the diagonal angle of the signal configures relevant to the treating apparatus of 2 systems at LSI.But, relate to the pin multiplexing of the signal of the signal relevant to the treating apparatus of 2 systems and common system, also can be configured as the second embodiment addressed accordingly.
Figure 15 is the Inner Constitution of fail safe LSI and the schematic diagram of external unit that represent the second embodiment.With the difference of Fig. 3 of the first embodiment be: there is universal input output circuit 24A and 24B and pin function selector switch 25A and 25B, the signal relevant to universal input output circuit 15A and 15B is not directly connected to the outside of LSI 10, and by pin function selector switch 25A and 25B, and together with the signal relevant to universal input output circuit 24A with 24B of common system, selectively be connected to outside, namely by pin multiplexing.
Figure 16 is the schematic diagram representing universal input output circuit 15A, the universal input output circuit 24A of the second embodiment and the Inner Constitution of pin function selector switch 25A.Universal input output circuit 15B, universal input output circuit 24B and pin function selector switch 25B are also same formations.Universal input output circuit 15A is identical with the first embodiment, have general purpose I/O read data register (PIORR_A) 151A, general purpose I/O write data register (PIOWR_A) 152A, general purpose I/O function setting register (PIOFR_A) 153A, these registers are carried out the reading and writing be worth by processor 11A via internal bus 12A.Universal input output circuit 24A has general purpose I/O read data register (PIORR_C1) 241A, general purpose I/O write data register (PIOWR_C1) 242A, general purpose I/O function setting register (PIOFR_C1) 243A, and these registers carry out the reading and writing be worth by access while carrying out self processor 11A and 11B via common system internal bus 21.
Pin function selector switch 25A is made up of general purpose I/O mask register (PIOSR_A) 251A and selection circuit 252A.The circuit (not diagram) of the register access of PIOSR_A is positioned at universal input output circuit 15A, is carried out the reading and writing be worth via internal bus 12A by processor 11A.PIORR_A and PIOWR_A has the data width of 8, and PIOFR_A has the data width of 1, is connected to selection circuit 252A.PIORR_C1 and PIOWR_C1 has the data width of 8, and PIOFR_C1 has the data width of 1, is connected to selection circuit 252A.PIOSR_A has the data width of 1, when its value is 0, selects the function of universal input output circuit 24A, when its value is 1, selects the function of universal input output circuit 15A.That is, when have selected the function of universal input output circuit 24A, PIORR_C1 with PIOWR_C1 is connected via the external signal line 250A of inputoutput buffer 252A and LSI 10, and decides the direction of input and output according to the value of PIOFR_C1.When have selected the function of universal input output circuit 15A, PIORR_A with PIOWR_A is connected via the external signal line 250A of inputoutput buffer 252A and LSI 10, and decides the direction of input and output according to the value of PIOFR_A.
Figure 17 is the schematic diagram for illustration of the logic circuit arrangements in the LSI chip 100 of the second embodiment and input/output pads configuration.With the difference of Figure 12 be: be configured with the pin function selector switch for switching A its exterior I/F and common system exterior I/F at the lower left quarter of chip, the pin function selector switch for switching B its exterior I/F and common system exterior I/F is configured with at the upper right quarter of chip, the signal relevant to A its exterior I/F of lower left quarter input/output pads and and common system exterior I/F input/output pads of signal of being correlated with between be configured with and the input/output pads of the signal correction switched by pin function selector switch and A system/common system Mixed Zone, the signal relevant to B its exterior I/F of upper right quarter input/output pads and and common system exterior I/F input/output pads of signal of being correlated with between be configured with and the input/output pads of the signal correction switched by pin function selector switch and B system/common system Mixed Zone.
Figure 18 is the schematic diagram configured for illustration of the external terminal of the LSI 10 of the second embodiment.With the difference of Figure 13 be: same with Figure 17, the signal relevant to A its exterior I/F of lower left quarter input and output pin and and common system exterior I/F input and output pin of signal of being correlated with between be configured with and the input and output pin of the signal correction switched by pin function selector switch and A system/common system Mixed Zone, the signal relevant to B its exterior I/F of upper right quarter input and output pin and and common system exterior I/F input and output pin of signal of being correlated with between be configured with and the input and output pin of the signal correction switched by pin function selector switch and B system/common system Mixed Zone.When carrying out the pin multiplexing of signal of the signal relevant to 2 system treating apparatus and common system, by becoming the such pin configuration of this second embodiment, the symmetry of the signal destroying A system and B system can be prevented.
Figure 19 is the schematic diagram of the summary representing the fail safe LSI with the physical arrangement different from the first embodiment.Figure 19 (a) is the schematic diagram in the cross section representing fail safe LSI, and the exterior I/F signal of LSI chip and power supply are connected to base plate for packaging by chip projection (バ Application プ) 107.Figure 19 (b) is the vertical view removing the state after seal member from fail safe LSI, and it represents that LSI chip 100 is by being configured in circuit face on base plate for packaging towards bottom, and is connected on base plate for packaging by chip projection 107.Figure 19 (c) is the schematic diagram of the circuit face representing LSI chip, is configured with the treating apparatus of B system in the left side of LSI chip, is configured with the treating apparatus of A system on right side, is configured with the circuit of common system in central authorities.But the external terminal of LSI encapsulation is identical with the first embodiment, is configured with the signal pin of A system, is configured with the signal pin of B system on right side, be configured with the signal pin of common system up and down in the left side of LSI.That is, as this figure, overleaf during chip, the signal configures of LSI chip and LSI encapsulation becomes reversed left to right.
Figure 20 is the schematic diagram configured for illustration of the external terminal of the fail safe LSI with the external terminal structure different from the first embodiment.Figure 20 (a) is the situation of the first embodiment, it is the situation not having external terminal at the central portion of encapsulation, be configured with the signal pin of A system in the left side of LSI, be configured with the signal pin of B system on right side, be configured with the signal pin of common system up and down.But, in the figure, represent it is not the power pin (also comprising ground pin) of I/F signal with stain.And the configuration of whole number of pin, power pin and quantity depend on the design of encapsulation and change, and what kind of position relationship the signal pin that the figure shows A system, B system and common system is installed into.Figure 20 (b) also has external terminal at the central portion of encapsulation, but central portion is all the situation of power pin, is configured with the signal pin of A system in the left side of LSI, be configured with the signal pin of B system on right side, be configured with the signal pin of common system up and down.Owing to not having signal pin at central portion, therefore same with Figure 20 (a), A system is separated by the signal pin of common system with the signal pin of B system.Figure 20 (c) also has external terminal at the central portion of encapsulation, it is the situation that central portion also becomes signal pin, be configured with the signal pin of A system in the left side of LSI, be configured with the signal pin of B system on right side, be configured with the signal pin of common system in upper and lower and central authorities.Like this, by the signal pin at central portion configuration common system, same with other examples, A system is separated by the signal pin of common system with the signal pin of B system.

Claims (20)

1. a LSI, is characterized in that, has in same chip:
The treating apparatus of the first system, comprises processor and external interface circuit;
The treating apparatus of second system, comprises the processor identical with the treating apparatus of described the first system and external interface circuit;
The comparison means of common system, the result of the treating apparatus of more described 2 systems, described common system does not belong to described 2 systems; With
Do not belong to the external interface circuit of the common system of described 2 systems,
Described comparison means has bus comparer, and the output of this bus comparer represents normal, represents abnormal judgment signal when the treating apparatus of described 2 systems carries out different actions when the treating apparatus of described 2 systems carries out identical action,
Between the input/output signal pin of the external interface circuit of described 2 systems, configure the input/output signal pin of the external interface circuit of described common system, make the input/output signal pin of the external interface circuit of described 2 systems non-conterminous.
2. LSI according to claim 1, is characterized in that,
The input/output signal pin of the external interface circuit of the input/output signal pin of the external interface circuit of described the first system and corresponding described second system, is configured in the position at the central point roughly diagonal angle relative to LSI encapsulation respectively.
3. LSI according to claim 2, is characterized in that,
Described common system has more than 2 external interface circuits, the input/output signal pin of the external interface circuit of more than 2 of described common system, is configured in the position relative to the roughly diagonal angle of the central point in LSI encapsulation respectively.
4. an electronic installation, has the electronic circuit board having carried LSI according to claim 3, and the feature of this electronic installation is,
The centre of the external device (ED) of the described common system of more than 2 connected at the external interface circuit of more than 2 of described common system, is configured with described LSI.
5. LSI according to claim 1, is characterized in that,
Described comparison means has two-way multiplexing control circuit, this two-way multiplexing control circuit is when the signal exported respectively from the treating apparatus of described 2 systems is consistent, export the consistent signal from described treating apparatus, in the case of inconsistencies, do not export the signal from described treating apparatus
There is common system internal bus control circuit, this common system internal bus control circuit is when the signal exported respectively from the treating apparatus of described 2 systems is consistent, receive the consistent signal from described treating apparatus from described two-way multiplexing control circuit, this signal is outputted to multiple external interface circuits of described common system.
6. LSI according to claim 5, is characterized in that,
Described two-way multiplexing control circuit comprises transport sector, and the signal from described common system internal bus control circuit is outputted to the treating apparatus of described 2 systems by this transport sector.
7. LSI according to claim 1, is characterized in that, has:
First pin function selection circuit, selects a part for the input/output signal of the external interface circuit of a part for the input/output signal of the external interface circuit of described the first system and described common system, is shared by identical input/output signal pin; With
Second pin function selection circuit, it selects a part for the input/output signal of the external interface circuit of a part for the input/output signal of the external interface circuit of described second system and described common system, is shared by identical input/output signal pin.
8. LSI according to claim 1, is characterized in that,
Between the input/output signal pin of the external interface circuit of described the first system and the input/output signal pin of the external interface circuit of described common system, be configured with an input/output signal pin part for the input/output signal of the external interface circuit of a part for the input/output signal of the external interface circuit of described the first system and described common system shared
Between the input/output signal pin of the external interface circuit of described second system and the input/output signal pin of the external interface circuit of described common system, be configured with an input/output signal pin part for the input/output signal of the external interface circuit of a part for the input/output signal of the external interface circuit of described second system and described common system shared.
9. LSI according to claim 1, is characterized in that,
The input/output pads of the external interface circuit of described 2 systems that LSI chip carries, is configured in the position at the central point roughly diagonal angle relative to the LSI chip in encapsulation respectively,
The input/output pads of the external interface circuit of the described common system that LSI chip carries, between the input/output pads being configured in the external interface circuit of described 2 systems, the input/output pads of the external interface circuit of described 2 systems is made to be spaced from each other and to configure
In logical circuit installation region in LSI chip, the processor of described the first system and the region of external interface circuit are being installed and between the processor having installed described second system and the region of external interface circuit, the region of the interface circuit of described comparison means and described common system has been installed in configuration, makes the region of the region of described the first system and described second system non-conterminous.
10. LSI according to claim 1, is characterized in that,
Possess the external device (ED) be connected with the external interface circuit of described second system,
External memory storage is comprised at described external device (ED).
11. LSI according to claim 10, is characterized in that,
The signal voltage of the described external memory storage be connected with the external interface circuit of described 2 systems, at least different in a part from the signal voltage of the external interface circuit of described common system.
12. 1 kinds of electronic installations, be the sub-device of railway power supply having carried LSI according to claim 10, the feature of this electronic installation is,
The configuration of the configuration of the external memory storage of described the first system and the external memory storage of described second system, on the electronic circuit board carrying LSI, is set to center by this LSI, becomes the position at roughly diagonal angle.
13. 1 kinds of railway fail safe LSI, is characterized in that,
The treating apparatus comprising processor and the first system of external interface circuit is set in a LSI chip and comprises the treating apparatus of second system of the processor identical with the treating apparatus of described the first system and external interface circuit,
Have: the comparison means of common system, the result of more described 2 systems, described common system does not belong to described 2 systems; Do not belong to the external interface circuit of the common system of described 2 systems,
Described comparison means has bus comparer, and the output of this bus comparer represents normal, represents abnormal judgment signal when the treating apparatus of described 2 systems carries out different actions when the treating apparatus of described 2 systems carries out identical action,
Between the input/output signal pin of the external interface circuit of described the first system and the input/output signal pin of the external interface circuit of described second system, configure the input/output signal pin of the external interface circuit of described common system, the configuring area of the input/output signal pin of the configuring area of the input/output signal pin of the external interface circuit of described the first system and the external interface circuit of described second system is spaced configuration.
14. railway fail safe LSI according to claim 13, is characterized in that,
The configuring area of the input/output signal pin of the external interface circuit of the configuring area of the input/output signal pin of the external interface circuit of described the first system and corresponding described second system, is configured in the position at the central point roughly diagonal angle relative to LSI encapsulation respectively.
15. railway fail safe LSI according to claim 14, is characterized in that,
Described common system has more than 2 external interface circuits, the input/output signal pin of the external interface circuit of more than 2 of described common system, is configured in the position relative to the roughly diagonal angle of the central point in LSI encapsulation respectively.
16. railway fail safe LSI according to claim 15, is characterized in that,
The input/output pads of the external interface circuit of described 2 systems that LSI chip carries, is configured in the position at the central point roughly diagonal angle relative to the LSI chip in encapsulation respectively,
The input/output pads of the external interface circuit of the described common system that LSI chip carries, between the input/output pads being configured in the external interface circuit of described 2 systems, the input/output pads of the external interface circuit of described 2 systems is made to be spaced from each other and to configure
In logical circuit installation region in LSI chip, the processor of described the first system and the region of external interface circuit are being installed and between the processor having installed described second system and the region of external interface circuit, the region of the interface circuit of described comparison means and described common system has been installed in configuration, makes the region of the region of described the first system and described second system non-conterminous.
17. railway fail safe LSI according to claim 16, is characterized in that,
External memory storage is comprised at the external device (ED) be connected with the external interface circuit of described 2 systems,
The signal voltage of the described external memory storage be connected with the external interface circuit of described 2 systems, at least different in a part from the signal voltage of the external interface circuit of described common system.
18. 1 kinds of sub-devices of railway power supply, be the sub-device of railway power supply having carried railway fail safe LSI according to claim 17, the feature of the sub-device of this railway power supply is,
The configuration of the configuration of the external memory storage of described the first system and the external memory storage of described second system, on the electronic circuit board carrying LSI, is set to center by this LSI, becomes the position at roughly diagonal angle.
19. railway fail safe LSI according to claim 17, is characterized in that,
Described comparison means has two-way multiplexing control circuit, this two-way multiplexing control circuit is when the signal exported respectively from the treating apparatus of described 2 systems is consistent, export the consistent signal from described treating apparatus, in the case of inconsistencies, do not export the signal from described treating apparatus
There is common system internal bus control circuit, this common system internal bus control circuit is when the signal exported respectively from the treating apparatus of described 2 systems is consistent, receive the consistent signal from described treating apparatus from described two-way multiplexing control circuit, this signal is outputted to multiple external interface circuits of described common system.
20. railway fail safe LSI according to claim 19, is characterized in that,
Described two-way multiplexing control circuit comprises transport sector, and the signal from described common system internal bus control circuit is outputted to the treating apparatus of described 2 systems by this transport sector.
CN201010621634.0A 2009-12-28 2010-12-28 LSI, fail-safe LSI for railways, electronic device, and electronic device for railways Expired - Fee Related CN102110033B (en)

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