GB2484908A - Layered structures comprising controlled height structures - Google Patents

Layered structures comprising controlled height structures Download PDF

Info

Publication number
GB2484908A
GB2484908A GB1017755.8A GB201017755A GB2484908A GB 2484908 A GB2484908 A GB 2484908A GB 201017755 A GB201017755 A GB 201017755A GB 2484908 A GB2484908 A GB 2484908A
Authority
GB
United Kingdom
Prior art keywords
solder
layer
capture pads
structures
controlled height
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB1017755.8A
Other versions
GB201017755D0 (en
Inventor
David Japp
Brian Minnis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bluwireless Technology Ltd
Original Assignee
Bluwireless Technology Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bluwireless Technology Ltd filed Critical Bluwireless Technology Ltd
Priority to GB1017755.8A priority Critical patent/GB2484908A/en
Publication of GB201017755D0 publication Critical patent/GB201017755D0/en
Publication of GB2484908A publication Critical patent/GB2484908A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q9/00—Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
    • H01Q9/04—Resonant antennas
    • H01Q9/0407—Substantially flat resonant element parallel to ground plane, e.g. patch antenna
    • H01Q9/045—Substantially flat resonant element parallel to ground plane, e.g. patch antenna with particular feeding means
    • H01Q9/0457—Substantially flat resonant element parallel to ground plane, e.g. patch antenna with particular feeding means electromagnetically coupled to the feed line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
    • H01Q1/38—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q9/00—Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
    • H01Q9/04—Resonant antennas
    • H01Q9/0407—Substantially flat resonant element parallel to ground plane, e.g. patch antenna
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

A layered structure e.g. planar patch antenna or a method of fabricating a layered structure comprising a plurality of controlled height structures 622 located between first and second planar surfaces wherein a void e.g. air gap is defined between the first and second surfaces and wherein each controlled height structure 622 includes first and second capture pads (623, 624, fig. 9) located on the first and second surfaces and a solder ball (625, fig. 9) with a core of a base material (625a, fig. 9) surrounded by a solder material (625b, fig. 9). The base material (625a, fig. 9) has a melting temperature higher than that of the solder material (625b, fig. 9) and the solder balls (625, fig. 9) are affixed to the capture pads (623, 624, fig. 9) without melting the base material (625a, fig. 9). The first and second planar surfaces may be formed by dielectric layers 608, 614 on which patch antenna 616 and ground plane 610, which face one another across the air gap, are located. A sealing material 626 can be located around the outside of the height controlled structures 622 to prevent ingress of dust.

Description

LAYERED STRUCTURES
The present invention relates to layered structures.
BACKGROUND OF THE INVENTION
Layered structures are well known in the field of semiconductor device manufacture, and are used in many different applications. One such application is the construction of planar antenna for wireless communication devices. In order to provide enhanced performance of such devices, it is desirable to provide an air gap between a ground plane and the patch antenna itself, as illustrated by a previously considered structure shown in Figure 1 of the accompanying drawings.
The structure shown in Figure 1 has a first dielectric layer 404, which has first and second substantially planar surfaces, and a conductive ground plane layer 402 which is located on the first surface of the first dielectric layer 404. A conductive feed line layer 406 is located on the second surface of the first dielectric layer 404, and a second dielectric layer 408 is located on the feed line layer 406. A conductive ground plane layer 410 is located on an upper surface of the second dielectric layer 408, and defines a slot or void 411. The slot 411 is surrounded by the ground plane layer 410, as before.
In the example shown in Figure 1, a spacing dielectric layer 412 is provided on the upper surface of the second dielectric layer 408, outside of the ground plane layer 410. It will be readily appreciated that the spacing dielectric layer could be located on the ground plane layer 410. A third dielectric layer 414 is located on an upper surface or surfaces of the spacing layer 412, sO as to define a void 413 between the second layer 408, the spacing layer 412, and the third layer 414. The third layer 414 has a surface 415 that bounds the void 413. The ground plane layer 410 bounds at least partially the void 413, on the upper surface of the second dielectric layer 410.
A planar patch antenna 416 is provided on the surface 415 of the third layer 414, such that the patch antenna 416 is opposite the ground plane layer 410 and slot 411 across the void 413. The patch antenna 316 is arranged to be substantially coaxial with the slot 411.
Such a structure overcomes the problems regarding the permittivity of the material between the patch antenna 416 and the slot 411, but has some disadvantages. In particular, the width of the spacing layer 412 is relatively large in order to maintain the integrity of the device, and to allow the device to be produced in a standard process such as a LTCC process. This width is necessary to enable the spacing layer 412 to be successfully and reliably bonded to the second and third layers 410 and 414, leads to the overall package being undesirably large.
A second previously considered patch antenna structure is illustrated in Figure 2 of the accompanying drawings, and is similar in basic construction to the structure of Figure 1.
A first dielectric layer 504 has first and second substantially planar surfaces, and a conductive ground plane layer 502 is located on the first surface of the first dielectric layer 504. A conductive feed line layer 506 is located on the second surface of the first dielectric layer 504, and a second dielectric layer 508 is located on the feed line layer 506. A conductive ground plane layer 510 is located on an upper surface of the second dielectric layer 508, and defines a slot or void 511. The slot 511 is surrounded by the ground plane layer 510, as before.
As in the example shown in Figure 1, a spacing dielectric layer 512 is provided on the upper surface of the second dielectric layer 508, outside of the ground plane layer 510. It will be readily appreciated that the spacing dielectric layer could be located on the ground plane layer 510. A third dielectric layer 514 is located on an upper surface or surfaces of the spacing layer 512, sO as to define a void 513 between the second layer 508, the spacing layer 512, and the third layer 514. The third layer 514 has a surface 515 that bounds the void 513. The ground plane layer 510 bounds at least partially the void 513, on the upper surface of the second dielectric layer 510.
A planar patch antenna 516 is provided on the surface 515 of the third layer 514, such that the patch antenna 516 is opposite the ground plane layer 510 and slot 511 across the void 513. The patch antenna 516 is arranged to be substantially aligned with the slot 511.
In the example of Figure 2, the third layer 514 is attached to the spacing layer 512 by way of attachment pads 518, 519. These attachment pads may be of a metallic material, such that they can be brazed or soldered to one another in order to hold the third layer 514 in place on the spacing layer 512. Alternatively, the attachment pads 518, 519 may be glued to one another using a suitable adhesive material.
Such a structure has the advantage that a void can be formed in a device even if the process used to fabricate the rest of the structure does not allow voids. However, the example of Figure 2 does have the significant disadvantage that an extra processing step and technique is required in order to attach the antenna-carrying third layer. In addition, the third layer must be very accurately positioned and aligned.
These patch antenna structures are examples of layered structures that require voids or air gaps to be provided.
It is desirable to provide a layered structure which can be manufactured using existing manufacturing techniques, whilst providing a suitable air gap and accurate alignment and spacing of the components.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, there is provided a layered structure having a void defined therein, the structure comprising a first component defining a first substantially planar surface, a plurality of controlled height structures located on the first surface, a second component defining a second substantially planar surface, and being located on the controlled height structures such that the second surface faces the first surface across a void defined between the first and second surfaces and the controlled height structures, the second surface being separated from the first surface by a distance determined by the controlled height structures, wherein each controlled height structure includes first and second capture pads located on the first and second surfaces respectively, a solder ball located between, and attached to, such first and second capture pads, each solder ball having a core of a base material surrounded by a solder material, the base material having a melting temperature higher than that of the solder material.
According to a second aspect of the present invention there is provided a method of fabricating a layered structure having a void defined therein, the method comprising the steps of providing a first component defining a first substantially planar surface, depositing a plurality of first capture pads onto the first surface, locating a plurality of solder balls onto respective first capture pads, each solder ball having a core of a base material surrounded by a solder material, the base material having a melting temperature higher than that of the solder material, providing a second component defining a second substantially planar surface, depositing a plurality of second capture pads onto the second surface, locating the second capture pads on respective ones of the solder balls, such that the second surface faces the first surface across a void defined between the first and second surfaces, the second surface being separated from the first surface by a distance determined by the solder balls, melting the solder material of the solder balls, without melting the base material of the solder balls, and, cooling the solder material of the solder balls, such that the first and second capture pads are affixed to the solder ball, so as to align the second capture pads with respect to the first capture pads.
BRIEF DESCRIPTION OF THE DRAWINGS
Figures 1 and 2 illustrate respective previously considered layered structures; Figure 3 illustrates a layered structure embodying one aspect of the present invention; Figure 4 illustrates the structure of Figure 3 in plan view; Figure 5 illustrates parts of the structure of Figure 3 in more detail; Figure 6 is a flow chart illustrating steps in a method embodying another aspect of the present invention; and Figure 7 illustrates fabrication of the structure of Figure 3, according to the method of Figure 6.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Aspects of the present invention will be described with reference to manufacture of a planar antenna structure. However, it will readily appreciated that the techniques embodying various aspect of the present invention are applicable to any layered structure in which a void or air gap is required or desirable.
Figure 3 of the accompanying drawings illustrates a first embodiment of one aspect of the present invention. A first dielectric layer 604 has first and second substantially planar surfaces, and a conductive ground plane layer 602 is located on the first surface of the first dielectric layer 604. A conductive feed line layer 606 is located on the second surface of the first dielectric layer 604, and a second dielectric layer 608 is located on the feed line layer 606.
A semiconductor device 607 is mounted on the feed line layer 606 adjacent the second dielectric layer 608, but will not be described in detail here. A conductive ground plane layer 610 is located on an upper surface of the second dielectric layer 608, and defines a slot or void 611. The slot 611 is surrounded by the ground plane layer 610.
A plurality of controlled height structures 622 are provided on the upper surface of the second dielectric layer, and carry a third dielectric layer 614 thereon. The controlled height structures space the third layer 614 away from the second layer 610 by a predetermined amount. One of the controlled height structures is shown in more detail in Figure 8, and will be described in more detail below. The controlled height structures 622 serve to provide an air gap 613 between the second and third layers 610 and 614. The third layer 614 carries a patch antenna 616 on a surface 616 thereof, such that the patch antenna 616 and ground plane 610/slot 611 face one another across the air gap 613. A high viscosity epoxy seal 626 is located around the edge of the third layer 614, and serves to seal the air gap 613 between the third layer 614 and the second layer 608, in order to prevent ingress of contaminants, such as dust. The seal can be of any suitable material.
Figure 4 illustrates the structure of Figure 3 in partial plan view. The plan view is taken through the air gap 613, and the patch antenna is shown in dotted lines to illustrate its positioning relative to the other components. The ground plane layer 610 defines the slot 611, through which the second dielectric layer can be seen. The plurality of controlled height structures 622 are arranged on the second layer 608, around the ground plane layer 610.
The patch antenna 616, shown in dotted lines, is aligned substantially coaxially with the slot 611.
It will be readily appreciated that the shapes of the component shown in Figure 4 are merely exemplary, and that the ground plane 610, slot 611, and patch antenna 616 could be of any shape as required by a particular application. For example, the slot 611 and patch antenna 616 could be square, rectangular, circular, elliptical, irregular in shape, or patterned, in plan view. It will also be appreciated that there can be provided any suitable number of controlled height structures.
Figure 5 illustrates one of the controlled height structures 622 of the embodiment of Figure 3.
The controlled height structure 622 comprises a first capture pad 623 attached to the second dielectric layer 608, and a second capture pad 624 attached to the third dielectric layer 614.
A non-collapsible solder alloy ball 625 is provided between the capture pads 620 and 624, and comprises a core 622a, surrounded by a solder alloy material 622b. As will be described in more detail below, the solder alloy ball 622 is subjected to heating, such that the solder alloy material 622b melts, and thereby bonds with the capture pads 620 and 624.
As the solder alloy material 622b melts, surface tension of the resulting liquid causes the capture pads 620 and 624 (and hence the second and third layers 608 and 614) to align.
The core 622a is of a material that has a higher melting point than that of the solder alloy material 622b, so that the height of the controlled height structure is accurately controlled.
When the molten solder alloy material 622b cools, the first and second capture pads 620 and 624 are joined together by the solder alloy material 622b, at a spacing controlled by the core 622a and the solder alloy material 622b.
Figure 6 is a flowchart showing steps in a method of fabricating a structure a shown in Figures 3 to 5, and Figure 7 illustrates these steps. Figures 6 and 7 will be described together. At step A, the first dielectric layer 604 is provided and the ground plane layer 602 deposited onto a first (lower) surface thereof. At step B the feed line layer 606 is deposited onto a second (upper) surface of the first dielectric layer 604. At step C, the second dielectric layer 408 is attached to the feed line layer 606.
The ground plane layer 610, and a plurality of first capture pads 623 are then deposited onto an upper surface of the second dielectric layer 608 (step D). Respective solder alloy balls 625 are located on the first capture pads 623 (Step E). At Step F, the third dielectric layer 614 is prepared by depositing the patch antenna 616 and a plurality of second capture pads 624 on the same surface thereof.
The third dielectric layer 614 is then positioned over the second dielectric layer 608 such that the second capture pads 624 come into contact with respective solder alloy balls 625 located on the first capture pads 623 (Step C). The assembly is heated such that the solder alloy material 625b melts, thereby bonding the first capture pads 623 to respective second capture pads 624W Surface tension of the molten solder alloy material 625b causes the capture pads, and hence the second and third dielectric layers, to align with one another.
The central core material 625a of the solder alloy balls 625 does not melt, and so controls the height of the gap 613.
A sealing material 626 can then be located around the outside of the controlled height structures in order to prevent ingress of dust or foreign matter into the air gap 613.
Such a fabrication technique allows an air gap to be provided between the ground plane and the patch antenna, whilst making use of existing substrate or laminate fabrication techniques.

Claims (4)

  1. CLAIMS: 1. A layered structure having a void defined therein, the structure comprising: a first component defining a first substantially planar surface; a plurality of controlled height structures located on the first surface; a second component defining a second substantially planar surface, and being located on the controlled height structures such that the second surface faces the first surface across a void defined between the first and second surfaces and the controlled height structures, the second surface being separated from the first surface by a distance determined by the controlled height structures; wherein each controlled height structure includes first and second capture pads located on the first and second surfaces respectively, a solder ball located between, and attached to, such first and second capture pads, each solder ball having a core of a base material surrounded by a solder material, the base material having a melting temperature higher than that of the solder material.
  2. 2. A method of fabricating a layered structure having a void defined therein, the method comprising the steps of: providing a first component defining a first substantially planar surface; depositing a plurality of first capture pads onto the first surface; locating a plurality of solder balls onto respective first capture pads, each solder ball having a core of a base material surrounded by a solder material, the base material having a melting temperature higher than that of the solder material; providing a second component defining a second substantially planar surface, depositing a plurality of second capture pads onto the second surface; locating the second capture pads on respective ones of the solder balls, such that the second surface faces the first surface across a void defined between the first andSsecond surfaces, the second surface being separated from the first surface by a distance determined by the solder balls; melting the solder material of the solder balls, without melting the base material of the solder balls; and cooling the solder material of the solder balls, such that the first and second capture pads are affixed to the solder ball, so as to align the second capture pads with respect to the first capture pads.
  3. 3. A device substantially as hereinbefore described with reference to, and as shown in, Figures 3 to 5 of the accompanying drawings.
  4. 4. A method substantially as herein before described with reference to Figures 6 and 7 of the accompanying drawings.
GB1017755.8A 2010-10-21 2010-10-21 Layered structures comprising controlled height structures Withdrawn GB2484908A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB1017755.8A GB2484908A (en) 2010-10-21 2010-10-21 Layered structures comprising controlled height structures

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB1017755.8A GB2484908A (en) 2010-10-21 2010-10-21 Layered structures comprising controlled height structures

Publications (2)

Publication Number Publication Date
GB201017755D0 GB201017755D0 (en) 2010-12-01
GB2484908A true GB2484908A (en) 2012-05-02

Family

ID=43334141

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1017755.8A Withdrawn GB2484908A (en) 2010-10-21 2010-10-21 Layered structures comprising controlled height structures

Country Status (1)

Country Link
GB (1) GB2484908A (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5736074A (en) * 1995-06-30 1998-04-07 Micro Fab Technologies, Inc. Manufacture of coated spheres
US6350669B1 (en) * 2000-10-30 2002-02-26 Siliconware Precision Industries Co., Ltd. Method of bonding ball grid array package to circuit board without causing package collapse
JP2004165511A (en) * 2002-11-14 2004-06-10 Nec Corp Csp connection method
EP1834377A1 (en) * 2004-12-30 2007-09-19 Robert Bosch Gmbh Antenna array for a radar transceiver
EP2040296A2 (en) * 2007-09-24 2009-03-25 Delphi Technologies, Inc. Method for forming BGA package with increased standoff height
US20090168367A1 (en) * 2007-12-27 2009-07-02 Shinko Electric Industries Co., Ltd. Electronic apparatus
WO2010058337A1 (en) * 2008-11-19 2010-05-27 Nxp B.V. Millimetre-wave radio antenna module

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5736074A (en) * 1995-06-30 1998-04-07 Micro Fab Technologies, Inc. Manufacture of coated spheres
US6350669B1 (en) * 2000-10-30 2002-02-26 Siliconware Precision Industries Co., Ltd. Method of bonding ball grid array package to circuit board without causing package collapse
JP2004165511A (en) * 2002-11-14 2004-06-10 Nec Corp Csp connection method
EP1834377A1 (en) * 2004-12-30 2007-09-19 Robert Bosch Gmbh Antenna array for a radar transceiver
EP2040296A2 (en) * 2007-09-24 2009-03-25 Delphi Technologies, Inc. Method for forming BGA package with increased standoff height
US20090168367A1 (en) * 2007-12-27 2009-07-02 Shinko Electric Industries Co., Ltd. Electronic apparatus
WO2010058337A1 (en) * 2008-11-19 2010-05-27 Nxp B.V. Millimetre-wave radio antenna module

Also Published As

Publication number Publication date
GB201017755D0 (en) 2010-12-01

Similar Documents

Publication Publication Date Title
US7911050B2 (en) Semiconductor device and method for manufacturing the same
US8021932B2 (en) Semiconductor device, and manufacturing method therefor
EP1894239B1 (en) Flip chip die assembly using thin flexible substrates
US9698072B2 (en) Low-stress dual underfill packaging
US20130252380A1 (en) Method for fabricating packaging structure having embedded semiconductor element
KR100652242B1 (en) Flip-chip type semiconductor device, production process for manufacturing such flip-chip type semiconductor device, and production process for manufacturing electronic product using such flip-chip type semiconductor device
US10679916B2 (en) Circuit module and manufacturing method thereof
KR20170123596A (en) Manufacturing method of semiconductor packages
US20140061951A1 (en) Package on package structure and method for manufacturing same
CN102237470A (en) Light emitting diode packaging structure and manufacturing method thereof as well as manufacturing method of base
US20080150096A1 (en) Multi-chip module, manufacturing method thereof, mounting structure of multi-chip module, and manufacturing method of mounting structure
US8179686B2 (en) Mounted structural body and method of manufacturing the same
US20150003029A1 (en) Stacked semiconductor device, printed circuit board, and method for manufacturing stacked semiconductor device
JP3221210U (en) Semiconductor device provided with high frequency conduction element and method of manufacturing the same
US20160329269A1 (en) Chip package structure and manufacturing method thereof
KR102409692B1 (en) Communication module
GB2484704A (en) Patch antenna structure formed with an air gap in a flip-chip assembly
GB2484908A (en) Layered structures comprising controlled height structures
CN102420202B (en) Semiconductor device and manufacture method thereof
US8878070B2 (en) Wiring board and method of manufacturing a semiconductor device
JP4596053B2 (en) Semiconductor device manufacturing method and semiconductor structure assembly
JP2008171904A (en) Laminated semiconductor device and its manufacturing method
KR101418264B1 (en) Semiconductor package manufacturing method
US8614504B2 (en) Chip package and method for making same
KR101544488B1 (en) Mount board for surface mount and method of mounting the same of semiconductor sensor

Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)