GB2459311A

GB2459311A - Cosine wave DAC for direct digital synthesis

Info

Publication number: GB2459311A
Application number: GB0807188A
Authority: GB
Inventors: Peter Henry Saul; Andrew Peter Saul
Original assignee: Individual
Current assignee: Individual
Priority date: 2008-04-19
Filing date: 2008-04-19
Publication date: 2009-10-21
Also published as: GB0807188D0

Abstract

A direct digital synthesiser DDS includes a digital to analogue converter 7 which has a cosinusoidal internal characteristic such that the digital output of a digital accumulator is converted into analogue form with a cosinusoidal waveform, without the requirement of a ROM. The DAC may comprise a resistor ladder or current source combination where the values of the resistors/current sources follow a cosine pattern such that the output analogue voltage from the DAC is equal to the cosine of the input digital word. Alternatively, a sine pattern could be used for the DAC.

Description

Sine Wave DAC for Direct Frequency Synthesis This invention shows a Direct Digital Synthesiser (DDS) using a sine wave Digital to Analogue Converter (DAC) to replace the Read Only Memory (ROM) in conventional DDS devices.

The Direct Digital Synthesiser (DDS) approach has been used for at least 30 years in specialist applications. The known system uses a digital accumulator, a Read Only Memory (ROM) and a linear Digital to Analogue Converter (DAC) as in figure 1. This has the disadvantage that the ROM access time limits the speed of operation in many implementations of this approach.

The present invention shows that a DAC may be designed such that it responds to the accumulator code in a non linear way, specifically in the form of a cosine wave. Thus a DDS may be built with a digital accumulator and a DAC only. This saves chip area and power consumption. This invention shows that the DAC may be made in a more accurate form than a conventional DAC and with a lower level of spurious output signals.

Preferably, the DAC has a cosine wave pattern of resistors in the structure.

Preferably, the DAC has one resistor element per least significant bit.

Preferably, the accumulator and DAC are on the same chip.

The invention will now be described solely by way of example and with reference to the accompanying drawings in which: Figure 1 shows a direct digital synthesiser according to prior art.

Figure 2 shows a direct digital synthesiser according to this invention Figure 3 shows a detail of a direct digital synthesiser according to this invention Figure 1 shows a conventional Direct Digital Synthesiser. A digital programming word 3 is applied to a digital accumulator 2. Data is clocked out of the accumulator under control of an externally supplied Clock Input 1. This digital word is passed through lines 4 to the Read Only Memory 5. The data is linearly related to the programming word. The Read Only Memory 5 converts the output into a sine wave in digital form. This is passed by lines 6 to the Digital to Analogue Converter 7. The DAC converts the digital sine wave to an analogue equivalent 8.

Figure 2 shows an embodiment of this invention. It is similar to Figure 1 at the top level, but the ROM is omitted because the DAC includes bit sizes which are related to a cosine wave form. A digital programming word 3 is applied to a digital accumulator 2. Data is clocked out of the accumulator under control of an externally supplied Clock Input 1.

This digital word is passed through lines 4 to the DAC 7. The data is linearly related to the programming word. The DAC 7, which operates in a cosinusoidal mannar, converts the digital input to an analogue output 8.

Figure 3 shows a detail of a simplified version of this invention. All of the circuit blocks 9 to 16 are required in the DAC. The digital accumulator can be provided using standard techniques. The blocks 9 and 10 are digital address generators. These provide an address into the array through connections not shown here. For an 8 bit DAC these are required to have 16 X and 16 Y address points. The array for an 8 bit DAC has 256 of the blocks 15 in a 16 X 16 arrangement. Other arrangements could be used. For 12 bits the corresponding figures are 64 X and 64Y, with 4096 blocks 15. Unequal combinations could be used. The blocks 15 consist of a switching arrangement and a resistor. All the resistors in the blocks 15 are in series. The switching signals from 9 and 10 cause one of the blocks 15 to connect at its output from the series resistor ladder to the output common point 13. The resistor ladder consisting of the blocks 15 is connected across an accurate reference voltage at the points 11 and 12. Thus the resistor ladder is connected across a reference voltage at Ii and 12 and at any time a unique point on the resistor ladder is connected to the output under digital control. The values of the resistors in the blocks 15 differ across the array. At the ends of the resistor chain, i.e. close to point 11 or point 12 the resistors are relatively low in value. At a point in the centre of the chain 16 the resistors are relatively high. The actual values chosen follow a cosine pattern such that the output analogue voltage from the DAC is equal to the cosine of the input digital word.

Thus the DAC output under control of the accumulator is a cosirwsoid without the requirement for a ROM. An additional advantage of this invention is that even if individual resistors are in error by substantial amounts, the accuracy of the whole remains

acceptable.

The DDS is preferably designed in a Complementary Metal Oxide Semiconductor (CMOS) technology.

Figure 4 shows the chip powered only by the clock input signal as in copending application "Power scavenging supply for semiconductor circuits". The DDS may be powered by the input clock waveform only for low power applications. The clock input is typically I volt rms, 3V peak to peak. This feeds to the chip input connection. In figure 4 the input clock is at 17. Input diodes 19 and 20 on the chip convert part of the clock waveform to a DC supply which powers the chip through rails 23 and 24. A coupling capacitor 18 takes the signal to the DDS block 21. A capacitor 22 smoothes the supply. The clock input which powers the chip may be at a frequency limited only by the technology of the DDS block 21.

Claims

Claims 1) A Direct Digital Synthesiser with a Cosinusoidal Digital to Analogue converter.
2) A Digital to Analogue converter where the bit size is determined by a resistor ladder having unequal resistors in a cosinusoidal pattern.
3) A Direct Digital Synthesiser where a single bit in a resistor ladder of cosinusoidal pattern as in 2 above is electrically switched to the output line.
4) A Direct Digital Synthesiser as in I where the bit pattern is sinusoidal.
5) A DDS where the chip is powered from the clock drive signal only.
6) A Digital to Analogue converter where the bit size is determined by a resistor ladder having unequal resistors in a sinusoidal pattern.
7) A Direct Digital Synthesiser where a single bit in a resistor ladder of sinusoidal pattern as in 2 above is electrically switched to the output line.
8) A Digital to Analogue converter where the bit size is determined by a current source combination having unequal currents in a cosinusoidal pattern.
9) A Digital to Analogue converter where the bit size is determined by a current source combination having unequal currents in a sinusoidal pattern.