GB2314708A

GB2314708A - Direct digital synthesiser

Info

Publication number: GB2314708A
Application number: GB9613532A
Authority: GB
Inventors: Alan Jones
Original assignee: Motorola Ltd
Current assignee: Motorola Solutions UK Ltd
Priority date: 1996-06-27
Filing date: 1996-06-27
Publication date: 1998-01-07
Anticipated expiration: 2016-06-27
Also published as: GB9613532D0; GB2314708B

Abstract

A direct digital synthesiser (DDS) for a cellular radio network uses a digital to analogue converter (12) having a raised cosine characteristic providing an output which is spectrally cleaner than that produced by conventional linear DAC techniques. To permit full use of the raised cosine characteristic a phase accumulator (10) permitting both addition and decrementation in an ALU (11) is employed in place of the conventional additive phase accumulator.

Description

SIGNAL SYNTHESISER Field of the Invention This invention relates generally to signal synthesis and particularly to the direct digital synthesis of signals in radio communication networks.

Background of the Invention In frequency division multiplexed (FDM) networks such as those operating under the Global System for Mobile Communication (GSM) protocol, a mobile station (MS) is connected to the network for communication by allocating a duplex traffic channel to establish a link to one of a number of base transceiver stations (BTS) together defining a subsystem of communication cells referred to as a Base Subsystem (BSS). Information for transmission over the link is coded into a digital bit stream. After combination with various flags and control data the resulting data is used to modulate the carrier of the allocated channel, typically by phase modulation. A reverse transformation, involving demodulation and decoding, is performed at the receiver.

As the operating speeds of digital devices and the demands for size reduction, particularly for the mobile station, increase, direct digital synthesis becomes increasingly attractive for radio subsystem implementation.

Typically such synthesis is performed by using the input digital bit stream to produce a series of digital phase position instructions which are then converted in a look up table into digital representations of a sinusoid which are converted into voltage levels by means of a digital to analogue converter (DAC). The voltage levels so derived are then used as samples to reconstruct the carrier waveform.

It is well known that in accordance with the theorem of Nyquist a pure sinusoid can be reconstructed from a series of such samples as long as the number of samples exceeds a predetermined minimum. However the process is subject to a number of limitations due to the fact that the samples are taken digitally in the form of words of finite length and phase so that quantization errors arise in the conversion process. These errors lead to spurious components in the output carrier which cause degradation of the performance of the system.

It is accordingly desirable to provide a signal synthesis system which permits a substantial reduction of such spurious components.

Summary of the Invention According to the invention there is provided a digital signal synthesiser for modulating an output signal with input digital data, including means for developing from said input data a series of digital instructions each identifying a sampling position in the output signal waveform, and a digital to analogue converter responsive to said digital instructions to produce a series of samples of said output signal for application to a low pass filter to permit reconstruction of said output signal waveform, wherein said digital to analogue converter has a conversion characteristic which corresponds to said output signal waveform.

In a radio communication network the waveform to be synthesised is sinusoidal, and the digital to analogue converter will accordingly have a sinusoidal characteristic.

In a preferred embodiment of the invention the characteristic of the digital to analogue converter follows a raised cosine law, which permits the converter to be conveniently implemented using laser trimming of the output network resistors.

In order that the invention may be well understood a preferred embodiment thereof will now be described with reference to the accompanying drawings.

Brief Description of the Drawings FIG.1 shows in block diagram form a typical known direct digital synthesiser (DDS).

FIG.2 shows the contents of the lookup table in the system of FIG.1 required to permit the generation of a sinusoid.

FIG.3 shows the sampling spectrum of the DDS of FIG.1 illustrating the development of alias sidebands.

FIG.4 illustrates the development of subharmonics in the DDS of FIG.1 when the control word value of the phase accumulator is equal to three.

FIG.5 illustrates the raised cosine DAC output characteristic of the preferred embodiment in comparison with the linear characteristic of the DAC of FIG.1.

FIG. 6 shows the structure of a preferred DDS embodying the present invention.

Detailed Description of the Preferred Embodiment A basic block diagram of a typical known direct digital synthesiser (DDS) is shown in FIG.1. A phase accumulator (1) comprising an adder (2) and a latch (3) is connected to receive an input bit stream (4). The phase accumulator operates effectively as an integrator, forming from the input bit stream a series of input instructions corresponding to phase positions in the output carrier.

These input instructions, typically in the form of eight bit words are applied to a look up table (5) which holds a group of sample values also in the form of eight bit words which when addressed by appropriate input instructions provide output samples defining the desired output waveform. These output samples are applied to a digital to analogue converter (DAC)(6) whose analogue output provides the output carrier (8) after filtering by a low pass filter (7).

As indicated earlier the process of direct digital synthesis relies on the fact that a pure sinusoid can be reconstructed from samples of itself provided that the number of such samples equals or exceeds the minimum number determined by the theorem of Nyquist. Provided that this criterion is met the gaps between samples can be reconstructed by interpolation because the samples contain sufficient information to permit such interpolation. In the arrangement of FIG.1 this interpolation is performed by the low pass filter (7).

Referring now to FIG.2 the words stored in look up table (5) are addressed by the output of the phase accumulator (1) to produce a digital word for input to the DAC which correctly represents a phase position in the output sinusoid, enabling the DAC (6) to produce the appropriate output amplitude. Clearly, if the look up table (5) is controlled to read out its stored samples one at a time it will produce an output sinusoid at a frequency determined by the number of samples stored and the clocking rate of the system.

If the DDS operates at a fixed clock rate, that is the speed at which the digital circuits perform their basic function, the stored samples can only be read out of the look up table at a fixed rate. However, if the look up table is instructed to output every other sample rather than every one, it will generate two cycles instead of one for the same number of clock cycles, since the samples are being accessed at a fixed rate. Similarly if the DDS is instructed to repeat the process, but this time taking every fourth sample at the fixed clock rate the output will be four times the minimum frequency. Thus the output frequency of the DDS is given by fo=kfC2-m where fc is the fixed clock frequency, k is the step length and m is the width of the memory address range. Provided Nyquist's theorem is not violated the filtered outputs will still be pure sinusoids regardless of the frequency generated. Thus, modulation can be readily effected by simply instructing the phase accumulator(l) which accesses the LUT (5) to increment by a certain phase amount k each time, thereby determining the output frequency.

Ideally the output from the DDS of FIG.1 will be a single pure sinusoid. However, since the synthesised output is a reconstructed waveform a sampling spectrum is generated, as shown in FIG.3. This includes a number of frequency components in the bandwidth of interest i.e.

around fO and a number of alias sidebands outside this bandwidth. The alias sidebands are normally not a problem since they are removed by the low pass filter (7).

However because of quantisation errors a number of spurious components occur within the bandwidth of interest and these pose a more serious problem.

These spurious components occur because of a fundamental problem in describing signals in digital form.

When an analogue voltage is converted into a digital word uncertainty is introduced because the magnitude of the analogue signal at the sample point has to be asigned a digital code which represents the nearest voltage level for which a digital word exists. The longer the digital word used the more accurately the actual voltage level at the sample point can be defined but unless the word has an infinite number of bits there is bound to be a finite error in coding the sample voltage in memory. This error reappears when digital words are converted into analogue voltages by the DAC. Because the quantisation errors are each associated with each sample point and the LUT is accessed in a cyclic manner the errors will emerge as regularly recurring disturbances in the voltages produced by the DAC. Such cyclic disturbances translate, via Fourier transformation of the disturbed waveform, into additional spectral lines in the DDS output. These spurious lines will be at a lower level than the wanted output but can have seriously degrading effects on system performance. If the step length is a power of two, the spurious lines are harmonically related to the wanted component and can usually be filtered out using a phaselocked loop tracking filter, adding some complexity to the system but not posing an insuperable problem.

However another mechanism, referred to here as phase accumulator overflow, also operates in the system of FIG.1.

The examples considered above result in samples being addressed in exactly the same position on the stored waveform in every pass of the memory. This happens if the number of samples stored corresponds to a number of phase positions which is a power of two and the number of intervals at which samples are addressed is also a power of two. However it can occur that there are 2m stored samples and memory is accessed at every third phase point.

As the phase accumulator increments the phase at each sample point it is clear that at the end of the first pass through the memory the next phase incrementation will not return to the position it started from initially. It will take up a slightly different sequence of samples in the next pass returning finally to the original sequence of phase positions in the fourth pass. This process is illustrated in FIG.4.

Since the phase of the synthesised signal is referred to the fixed clock frequency, this phase will as a result change by small amounts each time the memory is read out.

Such small changes amount to angle modulation of the output and again result in the appearance of spurious output spectral components. The problem is now twofold. The phase variation is slow in relation to the wanted output and this means that the spurious components are generated at sub-harmonic frequencies and are therefore much more difficult to filter out. Also, the angle modulation process is a nonlinear one resulting in more spurious components than just those at the sub-harmonic frequency.

In summary both quantisation error and phase accumulator overflow determine the spectral position of the spurious frequency components, while the resolution of the DAC essentially determines their magnitude.

Referring now to FIG.6 a direct digital synthesiser embodying the invention includes a phase accumulator (10) in which the adder (2) of FIG.1 is replaced by an arithmetic and logic unit (ALU) (11) which permits subtraction as well as addition. The look up table (5) and linear DAC (6) of FIG.1 are replaced by a raised cosine digital analogue converter (12) the output characteristic of which is shown in FIG.5 in comparison with the linear characteristic of the conventional DAC. As before a low pass filter (13) is used to remove modulation products outside the band width of interest.

The characteristic of the raised cosine DAC (12) is described by the equation to=0.5 [1-cos tp2-m)] where p is the output from the phase accumulator. In order to produce a continuous sinusoidal wave form at the DDS output it is necessary to make provision in the phase accumulator for decrementation as well as addition in order to trace the second half of the sinusoid, hence the replacement of the adder of FIG.1 by the ALU of FIG.6.

Thus the phase accumulator of FIG.6 counts in steps k up to 2m and then on the next clock cycle k is subtracted from 2m and the count is decremented.

While in a conventional DDS employing a linear DAC a look up table is required in order to provide the necessary conversion for obtaining a sinusoidal input, the use of a DAC having a sinusoidal characteristic in accordance with the invention eliminates the necessity for a look up table, and more importantly, the spurious components are significantly reduced, since the DAC output voltages lie exactly on a sinusoid. In simple terms this means that the DAC (12) of the preferred embodiment more closely approximates the ideal DAC with infinite resolution. Thus the magnitude of the spurious components comes close to zero and the effects of quantisation error and phase accumulator overflow are minimised.

The raised cosine characteristic has been selected for the preferred embodiment because it can be conveniently implemented in a digital analogue converter having a resistive current summing network in its output by using laser trimming techniques to set the values of the summing network resistors. As will be seen from FIG.5 the raised cosine characteristic has three points in common with the characteristic of the linear DAC and departs therefrom by relatively small amounts elsewhere on the characteristic, permitting minimal amounts of trimming from a standard resistor network. It will be appreciated however that other sinusoidal characteristics may be used and of course where wave forms other than sinusoidal wave forms are to be generated similar advantages may be gained by tailoring the output response characteristic of the DAC appropriately.

What is claimed is:

Claims

CLAIMS 1. A digital signal synthesiser for modulating an output signal with input digital data including means (10) for developing from said input digital data a series of digital instructions each identifying a sampling position in the output signal waveform, and a digital to analogue converter (12) responsive to said digital instructions to produce a series of samples of said output signal for application to a low pass filter (13) to permit reconstruction of said output signal waveform, wherein said digital to analogue converter has a conversion characteristic which corresponds to said output signal waveform.
2. A synthesiser as claimed in claim 1 for modulating a sinusoidal signal, wherein said digital to analogue converter has a sinusoidal characteristic.
3. A synthesiser as claimed in claim 2, wherein said digital to analogue converter has a raised cosine characteristic.
4. A synthesiser as claimed in claim 3 including a phase accumulator (10) for developing said digital instructions from said input digital data, said phase accumulator including an arithmetic and logic unit (11) operable to increment and decrement said phase accumulator in successive clock cycles, thereby permitting reconstruction of a continuous sinusoid output signal.
5. A direct digital synthesiser, substantially as described with reference to Figures 5 and 6 of the accompanying drawings.