GB2459301A - A method of dicing wafers to give high die strength - Google Patents
A method of dicing wafers to give high die strength Download PDFInfo
- Publication number
- GB2459301A GB2459301A GB0807099A GB0807099A GB2459301A GB 2459301 A GB2459301 A GB 2459301A GB 0807099 A GB0807099 A GB 0807099A GB 0807099 A GB0807099 A GB 0807099A GB 2459301 A GB2459301 A GB 2459301A
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- United Kingdom
- Prior art keywords
- wafer
- etching
- dicing
- back face
- thinning
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 235000012431 wafers Nutrition 0.000 title claims description 133
- 238000000034 method Methods 0.000 title claims description 35
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 230000002269 spontaneous effect Effects 0.000 claims abstract description 16
- 229910052736 halogen Inorganic materials 0.000 claims abstract description 12
- 150000002367 halogens Chemical class 0.000 claims abstract description 12
- 230000007547 defect Effects 0.000 claims abstract description 9
- 239000000463 material Substances 0.000 claims abstract description 7
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims abstract description 6
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052801 chlorine Inorganic materials 0.000 claims abstract description 6
- 239000000460 chlorine Substances 0.000 claims abstract description 6
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 6
- 239000011737 fluorine Substances 0.000 claims abstract description 6
- 229910052756 noble gas Inorganic materials 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 50
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 claims description 10
- 239000007788 liquid Substances 0.000 claims description 9
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 8
- 150000001875 compounds Chemical class 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- IGELFKKMDLGCJO-UHFFFAOYSA-N xenon difluoride Chemical compound F[Xe]F IGELFKKMDLGCJO-UHFFFAOYSA-N 0.000 claims description 7
- -1 halide compound Chemical class 0.000 claims description 5
- 229910000042 hydrogen bromide Inorganic materials 0.000 claims description 5
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 abstract description 2
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052794 bromium Inorganic materials 0.000 abstract description 2
- 229910052743 krypton Inorganic materials 0.000 abstract description 2
- DNNSSWSSYDEUBZ-UHFFFAOYSA-N krypton atom Chemical compound [Kr] DNNSSWSSYDEUBZ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052754 neon Inorganic materials 0.000 abstract description 2
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052724 xenon Inorganic materials 0.000 abstract description 2
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 5
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- 239000000126 substance Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 238000010926 purge Methods 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 238000003631 wet chemical etching Methods 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 150000004820 halides Chemical class 0.000 description 1
- 150000002366 halogen compounds Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 239000011343 solid material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dicing (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
A semiconductor wafer, having a first face including active devices and a back face opposed to the first face, is mounted on a tape 2 supported by a wafer carrier 5 with the back face of the wafer accessible. The wafer is thinned by removing material from the back face to form a thinned wafer. A back face of the thinned wafer is etched with a spontaneous etchant such as XeF 2 while the wafer is still on the wafer carrier, at least to reduce defects generated in thinning the wafer, to produce an etched wafer 12. The etched wafer is diced while still on the wafer carrier to form dies with a high flexural strength. Spontaneous etchants which may be used include those consisting of a noble gas (for example neon, xenon and krypton) and a halogen (for example fluorine, chlorine and bromine), or interhalogens.
Description
A method of dicing wafers to give high die strength This invention relates to a method of dicing wafers to give high die strength.
In recent years, a demand for thin die for semiconductor devices has been increasing. Typically "thin" die are less than 150 microns thick with current typical thicknesses in production of 50 and 75 microns, but this is expected to be frirther reduced in coming years. In a known method die are thinned by mechanical lapping a back face of the die opposed to a face bearing active devices, before dicing the wafers with a mechanical saw or laser. This so-called backgrind process adds significant additional stress and warping to thin silicon wafers that may already be stressed by device layers on the front or active face.
Microcracks are produced by such backgrinding in a surface layer of the silicon wafer, about 5-10 im thick, entirely destroying the silicon in the surface layer.
Crystal dislocations are also formed in a second underlying layer of silicon, which cause degradation of some electrical properties. These effects of backgrinding create increasingly significant risks of yield loss during de-taping, handling, dicing and package assembly processing. The defects generated during backgrinding also adversely affect the flexural bend strength of die produced from the wafer.
Stress relief for example after mechanical backgrinding, improves die strength providing greater durability and reducing die warping for greater usability in stacks and thin packages. Three known types of stress relief arc chemical mechanical polishing (CMP), wet etching, and dry etching.
CMP employs abrasive, corrosive slurry physically to grind away microscopic irregularities on a wafer surface. However, this requires remounting of the wafer and CMP type solutions also induce some mechanical damage to the substrate surface.
Wet chemical etching comprises spin processing with chemicals such as KOH and TMAH (tetramethyl ammonium hydroxide) to relieve stress in a wafer.
A predetermined thickness of material is etched from the back of the wafer, eliminating microcracks and crystal dislocations. However, this also requires remounting the wafer and application of a capping layer.
Anisotropic plasma etching of the back of a post-backgrind wafer by, for example, SF5 gas is another means of eliminating backgrind defects and relieving stress in dies. However, this also requires remounting the wafer and plasma etching is relatively expensive compared with, for example, wet chemical etching.
US 6,498,074 discloses a method of partially dicing and then thinning semiconductor wafers using a dry etch to obtain, semiconductor chips with rounded bottom edges and corners. In this process, which is a reverse process of grind and dice, a wafer is partially diced to form grooves on the active side of the wafer. The wafer is remounted in a non-contact wafer holder active face up and is then dry etched, with an atmospheric plasma etch to remove the silicon from a back of the wafer until the grooves are exposed. The dry etching removes stress built up on the backside and sidewall of the dies by removal of silicon from these areas. It also adds a rounded edge to the dies. However, the method involves remounting the wafer and using relatively expensive plasma etching.
Thus, all these known methods of stress relief have at least the disadvantage of requiring re-mounting of the wafer between process steps.
It is an object of the present invention at least to ameliorate the aforesaid
shortcomings in the prior art.
According to a first aspect of the present invention there is provided a method of dicing a semiconductor wafer having a first face including active devices and a back face opposed to the first face, the method comprising the steps of: mounting the wafer on wafer carrier means with the back face accessible; thinning the wafer on the wafer carrier means by removing material from the back face to form a thinned wafer; etching a back face of the thinned wafer on the wafer carrier means with a spontaneous etchant at least to reduce defects generated in thinning the wafer, to produce an etched wafer; and dicing the etched wafer on the wafer carrier means to form dies.
Preferably, the step of mounting the wafer on wafer carrier means comprises mounting the wafer on one of backgrinding tape means, mechanical clamping means, electrical clamping means and vacuum clamping means.
Advantageously, the step of thinning comprises one of mechanical lapping, dry etching and wet etching.
Conveniently, the step of etching the thinned wafer comprises etching with a gaseous or liquid etehant.
Advantageously, the step of etching with a gaseous or liquid etchant comprises etching with a halogen or a halide compound.
Conveniently, the step of etching comprises etching with one of fluorine, chlorine, hydrochloric acid and hydrogen bromide.
Conveniently, the step of etching comprises etching with an etchant comprising a compound of a noble gas and a halogen.
Preferably, the step of etching comprises etching with xenon fluoride.
Preferably, the step of etching comprises etching with an interhalogen compound.
Advantageously, the etching step is at least partially carried out before the dicing step.
Conveniently, the step of dicing comprises dicing with mechanical saw means or laser means.
Advantageously, the step of dicing the wafer comprises aligning, through transparent carrier means, alignment marks on the wafer with dicing means.
Conveniently, the semiconductor wafer is a silicon wafer.
According to a second aspect of the invention, there is provided a dicing apparatus for dicing semiconductor wafers having a first face including active devices and a back face opposed to the first face, the apparatus comprising: wafer carrier means arranged for mounting the wafer with the back face accessible; thinning means arranged for thinning the wafer on the wafer carrier means by removing material from the back face to form a thinned wafer; etching means arranged for etching a back face of the thinned wafer on the wafer carrier means with a spontaneous etchant at least to reduce defects generated in thinning the wafer, to produce an etched wafer; and dicing means arranged for dicing the etched wafer on the wafer carrier means to form dies.
Preferably, the wafer carrier means comprises one of backgrinding tape means, mechanical clamping means, electrical clamping means and vacuum clamping means.
Advantageously, the thinning means comprises one of mechanical lapping means, dry etching means and wet etching means.
Conveniently, the etching means comprises a gaseous or liquid etchant.
Advantageously, the etching means comprises a halogen or a halide compound.
Conveniently, the etching means comprises one of fluorine, chlorine, hydrochloric acid and hydrogen bromide.
Conveniently, the etching means comprises a compound of a noble gas and a halogen.
Preferably, the etching means compriscs xenon fluoride.
Preferably the etching means comprises an interhalogen.
Conveniently, the dicing means comprises mechanical saw means or laser means.
Advantageously, the dicing means comprises aligning means for aligning, through transparent carrier means, alignment marks on the wafer with the dicing means.
The invention will now be described, by way of example, with reference to the accompanying drawings in which: Figure 1 is a schematic perspective drawing of a semiconductor wafer mounted active side down on a caTTier tape preparatory to processing according to the present invention; Figure 2 is a schematic perspective drawing of the wafer of Figure 1 after baekgrinding; Figure 3 is a schematic perspective drawing of the wafer of Figure 2 being dry etched; Figure 4 is a schematic perspective drawing of the wafer of Figure 3 after dicing; Figure 5 is a schematic drawing on an enlarged scale compared with the preceding Figures of a die removed from the diced wafer of Figure 4 and mounted on a substrate; and Figure 6 is a flowchart of a method according to the invention.
In the Figures like reference numerals denote like parts.
Referring to Figures 1 and 6, a semiconductor wafer I is mounted 61 active side down on a known backgrind tape 2 which may be supported by a glass substrate or carrier 5. However, the wafer carrier can be made of any optically transparent flexible or solid material that holds the wafer in place either, for example, through the use of an adhesive layer or by mechanical means such as physical, electrical or vacuum clamping.
The wafer is thinned 62 by "backgrinding" a back side, opposed to the active side, in a known manner to form a thinned wafer 11 of a required thickness, as shown in Figure 2, for example by mechanical lapping or wet or dry etching.
Referring to Figures 3 and 6, the thinned wafer 11, still mounted on the wafer backgrind tape carrier 2 used in the backgrind step, is placed in contact with, and etched 63 by, a spontaneous etehant of silicon for a predetermined time in a chamber 3 having an inlet 31 and an outlet 32. By spontaneous etchants will be understood etehants which etch without a need for an external energy source such as electricity or kinetic energy activation. Such etching is exothermic so that more energy is released during the reaction than is used to break and reform inter-atomic bonds of the reactants. Examples of such spontaneous etehants are a class of etehants consisting of a noble gas (for example neon, xenon and krypton) and a halogen (for example fluorine, chlorine and bromine), not all such combinations are stable but in principle most could be used. Other spontaneous etchants are interhalogens where the compound consists of ABn where A and B are halogens abd A is the less electronegative of the two halogens and n the number of atoms of B. That is, particularly in the ease of a silicon semiconductor wafer, the chamber 3 is cycled with XeF2, or, for such a silicon wafer, any spontaneous etchant of silicon, followed by a chamber purge for a predetermined one or more cycles with a predetermined etching time period. Alternatively, continuous etching may be used where uniformity of etch across the area can be achieved.
Moreover, other spontaneous etchants such as halides and halogen compounds, including interhalogens, in gaseous and liquid form such as, but not restricted to, F2, Cl2, HC1, HBr can be used for silicon or other semiconductor wafers as appropriate. The etchant removes a layer of semiconductor from the backside of the wafer to form an etched wafer 12, eliminating defects generated in the baekgrind process thereby increasing resultant die strength.
The etched wafer 12, still mounted on the wafer carrier 5 used in the backgrind step, is then aligned, either using infrared light through the carrier with alignment marks on the active side or with alignment marks on the ground backside and diced 64 from the backside with a laser or mechanical saw to form dies 13, as shown in Figure 4. The laser may be a diode-pumped solid-state laser, a mode-locked laser or any other laser suitable for machining the semiconductor and other materials of the wafer. Suitable laser wavelengths may be selected from infrared to ultraviolet wavelengths. Alternatively the etched wafer may be remounted and diced active side up, stopping at the carrier when the wafer is diced.
As shown in Figure 5, the dies 13 are then removed from the wafer carrier 2 and remounted on a die pad 4 or die cavity of a support system of a semiconductor package.
Alternatively the wafer may be etched partially before and partially during dicing, providing additional advantages of removing defects from side walls of the dies and rounding at least some edges and corners of the dies to remove stress points.
Thus there is provided a method of producing dies 13 with high die strength in which a silicon or other semiconductor wafer after backgrinding is etched in contact with a spontaneous etchant. The method provides high flcxural strength dies, as measured, for example, in a three or four point flexural bend test, from a wafer in which the means of supplying the spontaneous silicon etchant and the means of dicing the wafers are part of a same mechanical system. That is, high flexural strength dies are produced from a wafer using an apparatus in which means of wafer backgrinding, supplying a spontaneous silicon etchant, wafer backside alignment, wafer dicing and die removal are all part of a single mechanical sequence, without a requirement for re-mounting the wafer during the process.
The present invention has an advantage, in a preferred embodiment, over CMP for stress relief of being a dry process, although a liquid etchant may be used in less preferred embodiments, in which the wafer preferably is diced and stress relieved in the same machine and the wafer does not need to be remounted at any stage.
However, it will be understood that the invention may be used in an apparatus including integrated etching and laser machining or dicing on a single machine, with a standalone dicing saw or laser, and with a standalone etcher.
The present invention has an advantage over chemical wet etching of being a dry process in preferred embodiments, although a liquid etchant may be used in a less preferred embodiments, which does not require the application of a capping layer, as the active layer itself acts as a mask to an etchant such as XeF2. In the present invention, the wafer can also be stress relieved and diced in a same machine and does not need to be remounted at any stage.
The present invention has an advantage over anisotropic plasma etching that the spontaneous etchant of the present invention is far less costly than plasma etching and the wafer can also be stress relieved and diced in a same machine and does not need to be remounted at any stage.
The present invention has the advantage over the disclosure of US 6,498,074 that the wafer does not need to be remounted. The wafers are background, stress relieved and diced while mounted on a same carrier in the present invention.
EXAMPLE
Five 125mm diameter, 1 SOp. thick, background silicon wafers were placed in a chamber and etched with XeF2 for a predetermined etching time of 10 sec. as shown in Table 1. After this period the chamber was evacuated and purged. This etch, evacuate and purge cycle was repeated a plurality of times to remove a predetermined amount of silicon. The etch conditions are shown in Table 2.
Table 1. Wafer description
____________
Waler biijitciieptii number Process (jtm) I Not etched 2 2 3 Laser 3 4 4 25 Table 2. Etching parameters N:rolTirnePffcleffec 2pm 8 10 3pm 12 10 4pm 16 10 ___ 25pm 100 10 The wafers were then diced and the die strength of each wafer was measured using 3-point and 4-point fiexural bend strength testing. The results of 3-point and 4-point flexural bend strength testing show that the average die strength is higher than a die produced without such etching, although the actual value of ilexural die strength is very dependent on other processes to which the die has been subjected.
Claims (26)
- CLAIMS1. A method of dicing a semiconductor wafer having a first face including active devices and a back face opposed to the first face, the method comprising the steps of a. mounting the wafer on wafer carrier means with the back face F accessible; b. thinning the wafer on the wafer carrier means by removing material from the back face to form a thinned wafer; e. etching a back face of the thinned wafer on the wafer carrier means with a spontaneous etchant at least to reduce defects generated in thinning the wafer, to produce an etched wafer; and d. dicing the etched wafer on the wafer carrier means to form dies.
- 2. A method as claimed in claim 1, wherein the step of mounting the wafer on wafer carrier means comprises mounting the wafer on one of backgrinding tape means, mechanical clamping means, electrical clamping means and vacuum clamping means.
- 3. A method as claimed in claims 1 or 2, wherein the step of thinning comprises one of mechanical lapping, dry etching and wet etching.
- 4. A method as claimed in any of the preceding claims, wherein the step of etching the thinned wafer comprises etching with a gaseous or liquid etehant.
- 5. A method as claimed in claim 4, wherein the step of etching with a gaseous or liquid etehant comprises etching with a halogen or a halide compound.
- 6. A method as claimed in claim 5, wherein the step of etching comprises etching with one of fluorine, chlorine, hydrochloric acid and hydrogen bromide.
- 7. A method as claimed in claim 5, wherein the step of etching comprises etching with an etehant comprising a compound of a noble gas and a halogen.
- 8. A method as claimed in claim 7, wherein the step of etching comprises etching with xenon fluoride.
- 9. A method as claimed in claim 4, comprising etching with an interhalogen compound.
- 10. A method as claimed in any of the preceding claims, wherein the etching step is at least partially carried out before the dicing step.
- 11. A method as claimed in any of the preceding claims, wherein the step of dicing comprises dicing with mechanical saw means or laser means.
- 12. A method as claimed in any of the preceding claims, wherein the step of dicing the wafer comprises aligning, through transparent carrier means, alignment marks on the wafer with dicing means,
- 13. A method as claimed in any of the preceding claims, wherein the semiconductor wafer is a silicon wafer.
- 14. A dicing apparatus for dicing semiconductor wafers having a first face including active devices and a back face opposed to the first face, the apparatus comprising: a. wafer carrier means arranged for mounting the wafer with the back face accessible; b. thinning means arranged for thinning the wafer on the wafer carrier means by removing material from the back face to form a thinned wafer; c. etching means arranged for etching a back face of the thinned wafer on the wafer carrier means with a spontaneous etchant at least to reduce defects generated in thinning the wafer, to produce an etched wafer; and d. dicing means arranged for dicing the etched wafer on the wafer carrier means to form dies.
- 15. A dicing apparatus as claimed in claim 14, wherein the wafer carrier means comprises one of baekgrinding tape means, mechanical clamping means, electrical clamping means and vacuum clamping means.
- 16. A dicing apparatus as claimed in claims 14 or 15, wherein the thinning means comprises one of mechanical lapping means, dry etching means and wet etching means.
- 17. A dicing apparatus as claimed in any claims 14 to 16, wherein the etching means comprises a gaseous or liquid etchant.
- 18. A dicing apparatus as claimed in claim 17, wherein the etching means comprises a halogen or a halide compound.
- 19. A dicing apparatus as claimed in claim 18, wherein the etching means comprises one of fluorine, chlorine, hydrochloric acid and hydrogen bromide.
- 20. A dicing apparatus as claimed in claim 18, wherein the etching means comprises a compound of a noble gas and a halogen.
- 21. A dicing apparatus as claimed in claim 18, wherein the etching means comprises xenon fluoride.
- 22. A dicing apparatus as claimed in claim 17, wherein the etching means comprises an interhalogen.
- 23. A dicing apparatus as claimed in any of claims 14 to 20, wherein the dicing means comprises mechanical saw means or laser means.
- 24. A dicing apparatus as claimed in any of claims 14 to 23, wherein the dicing means comprises aligning means for aligning, through transparent carrier means, alignment marks on the wafer with the dicing means.
- 25. A method of dicing a semiconductor wafer substantially as described herein with reference to and as shown in the accompanying Figures.
- 26. A dicing apparatus substantially as described herein with reference to and as shown in the accompanying Figures.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB0807099A GB2459301B (en) | 2008-04-18 | 2008-04-18 | A method of dicing wafers to give high die strength |
| PCT/EP2009/054674 WO2009127738A1 (en) | 2008-04-18 | 2009-04-20 | A method of dicing wafers to give high die strength |
| TW098113118A TW201009915A (en) | 2008-04-18 | 2009-04-20 | A method of dicing wafers to give high die strength |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB0807099A GB2459301B (en) | 2008-04-18 | 2008-04-18 | A method of dicing wafers to give high die strength |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB0807099D0 GB0807099D0 (en) | 2008-05-21 |
| GB2459301A true GB2459301A (en) | 2009-10-21 |
| GB2459301B GB2459301B (en) | 2011-09-14 |
Family
ID=39472342
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB0807099A Expired - Fee Related GB2459301B (en) | 2008-04-18 | 2008-04-18 | A method of dicing wafers to give high die strength |
Country Status (3)
| Country | Link |
|---|---|
| GB (1) | GB2459301B (en) |
| TW (1) | TW201009915A (en) |
| WO (1) | WO2009127738A1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102157426B (en) * | 2011-01-28 | 2015-10-07 | 上海华虹宏力半导体制造有限公司 | Wafer support and wafer processing process |
| KR101372805B1 (en) * | 2012-11-30 | 2014-03-19 | 로체 시스템즈(주) | Wafer etching process and using the same wafer etching system |
| BR112015019393B1 (en) | 2013-02-13 | 2021-11-30 | Hewlett-Packard Development Company, L.P. | FLUID EJECTION DEVICE |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0475259A2 (en) * | 1990-09-05 | 1992-03-18 | Sumitomo Electric Industries, Limited | Semiconductor element manufacturing process |
| EP1098365A2 (en) * | 1999-11-05 | 2001-05-09 | Tokyo Seimitsu Co.,Ltd. | Method for manufacturing semiconductor chips |
| JP2002093752A (en) * | 2000-09-14 | 2002-03-29 | Tokyo Electron Ltd | Method and device of isolating semiconductor elements |
| US6498074B2 (en) * | 1996-10-29 | 2002-12-24 | Tru-Si Technologies, Inc. | Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners |
| WO2003100829A2 (en) * | 2002-05-20 | 2003-12-04 | Imagerlabs | Forming a multi segment integrated circuit with isolated substrates |
| US6743722B2 (en) * | 2002-01-29 | 2004-06-01 | Strasbaugh | Method of spin etching wafers with an alkali solution |
| EP1453090A2 (en) * | 2003-02-25 | 2004-09-01 | Sanyo Electric Co., Ltd. | Manufacturing method of semiconductor device |
| US20060032834A1 (en) * | 2004-08-16 | 2006-02-16 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor wafer and method of manufacturing semiconductor device |
| US20060284285A1 (en) * | 2005-06-17 | 2006-12-21 | Seiko Epson Corporation | Manufacturing method for a semiconductor device, semiconductor device, circuit substrate and electronic device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1266399B1 (en) * | 2000-01-26 | 2012-08-29 | ALLVIA, Inc. | Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners |
| GB2420443B (en) * | 2004-11-01 | 2009-09-16 | Xsil Technology Ltd | Increasing die strength by etching during or after dicing |
| JP2007165706A (en) * | 2005-12-15 | 2007-06-28 | Renesas Technology Corp | Manufacturing method of semiconductor integrated circuit device |
-
2008
- 2008-04-18 GB GB0807099A patent/GB2459301B/en not_active Expired - Fee Related
-
2009
- 2009-04-20 WO PCT/EP2009/054674 patent/WO2009127738A1/en active Application Filing
- 2009-04-20 TW TW098113118A patent/TW201009915A/en unknown
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0475259A2 (en) * | 1990-09-05 | 1992-03-18 | Sumitomo Electric Industries, Limited | Semiconductor element manufacturing process |
| US6498074B2 (en) * | 1996-10-29 | 2002-12-24 | Tru-Si Technologies, Inc. | Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners |
| EP1098365A2 (en) * | 1999-11-05 | 2001-05-09 | Tokyo Seimitsu Co.,Ltd. | Method for manufacturing semiconductor chips |
| JP2002093752A (en) * | 2000-09-14 | 2002-03-29 | Tokyo Electron Ltd | Method and device of isolating semiconductor elements |
| US6743722B2 (en) * | 2002-01-29 | 2004-06-01 | Strasbaugh | Method of spin etching wafers with an alkali solution |
| WO2003100829A2 (en) * | 2002-05-20 | 2003-12-04 | Imagerlabs | Forming a multi segment integrated circuit with isolated substrates |
| EP1453090A2 (en) * | 2003-02-25 | 2004-09-01 | Sanyo Electric Co., Ltd. | Manufacturing method of semiconductor device |
| US20060032834A1 (en) * | 2004-08-16 | 2006-02-16 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor wafer and method of manufacturing semiconductor device |
| US20060284285A1 (en) * | 2005-06-17 | 2006-12-21 | Seiko Epson Corporation | Manufacturing method for a semiconductor device, semiconductor device, circuit substrate and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2459301B (en) | 2011-09-14 |
| GB0807099D0 (en) | 2008-05-21 |
| WO2009127738A1 (en) | 2009-10-22 |
| TW201009915A (en) | 2010-03-01 |
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