GB2455989A

GB2455989A - Sending a signal on a single line representing two data bits on a pair of input lines, and converting back to data bits on a pair of output lines at a receive

Info

Publication number: GB2455989A
Application number: GB0725249A
Authority: GB
Inventors: Namik Bardhi
Original assignee: Individual
Current assignee: Individual
Priority date: 2007-12-27
Filing date: 2007-12-27
Publication date: 2009-07-01
Also published as: GB0725249D0

Abstract

The invention enables the transfer of digital data by two bits per line at the same time. A Two Bits per Line Transfer device includes a transmitter 1 connected to input lines 4, a receiver 2 connected to output lines 5, and transfer lines 3 connecting the transmitter and receiver. For each pair of input lines, a voltage representing the combination of bits on that line pair is sent on a respective single line 3. The voltage has a unique value for each combination of bits on the input lines. The voltages received at the receiver are then converted back to the original data bit values and output on respective pairs of lines 5. The Two Bits per Line Transfer can be of any desirable capacity depending on the need of its application and the limitations. Circuitry for conversion between data bits and voltages is described (figs. 2-5, not shown).

Description

1 2455989 Two Bits per Line Transfer This invention relates to an electronic digital device that makes possible the instant transfer of every two bits of digital data in a single line of transfer or communication, from one point of electronic circuitry to another in a given digital device, or from one digital device to another.

The invention enables the transfer of digital data by two bits per line instantly (at the same time) Many digital devices are made-up of different circuitry or parts that do carry different processes on given digital data.

All these circuits or parts need to communicate and transfer digital data in between.

This transfer or communication of digital data it is accomplished by lines of digital data transfer (digital data communication lines).

Also many digital devices do communicate and transfer digital data in between by means of digital data transfer or communication lines.

One of the most important characteristics that defines the performance of almost all digital devices (been it the most sophisticated or the simpler) it is the speed and the capacity of digital data processing in overall.

One of the important features this overall speed and capacity depends on, it is the speed and the capacity of digital data transfer thorough the transfer or communication lines of the digital device.

Also on many digital devices that communicate and transfer digital data in between, the quality of the signal these digital data represent (example video and sound), to a certain extent depends on the capacity of the digital data transfer of these digital devices.

No mater what format or technicality involved on the digital data transfer the basic hardware principle of data transfer it is one bit per line at a time.

One bit per line at a time it is the present digital data transfer capacity standard of a digital device.

The invention does enhance that capacity and offers a new digital data transfer capacity standard of iwo bits per line instant transfer.

In principal the invention it is an electronic digital device made of two parts: Part A -The transmitter; and Part B -The receiver.

The Part A of the invention it is meant to be connected at the transmitting point (s) of the digital data and the Part B at the receiving point (s).

The digital input lines of the Part A are intended to be connected at the transmitting point (s) and the output lines at the transfer or communication lines.

The digital input lines of the Part B are intended to be connected at the other side of transfer or communication lines and the output at the receiving point (s).

All digital data or digital signals in their most basic form are represented in a binary format as long strings of zeros (0) and ones (I).

In a digital electronic device all the zeros and ones are represented or defined as two different states of voltage values. (For example in a positive logic device the zeros are virtually represented or defined by a 0 volt value while the ones generally by +5 volt value) The binary form of two digits of data has only four possible combinations: 00;0l; 10; 11.

The principal process and function of the Part A of the invention it is based on this particular fact.

For every two input lines the Part A of the invention has one respective output line.

Every output line would represent accordingly the current possible combination of its respective two input lines.

To achieve this, the Part A of the device does assign to every one of the four possible combinations of two bits, a digital voltage value different and distinguishable from the other three.

The four possible combinations of every two bit of data will be represented by four different and distinguishable digital voltage values. For example: 00 by OV; 01 by+3V; 10 by +7.5V; 11 by+SV So every two bit of binary data at the inputs of the Part A will be represented at the respective output as a digital voltage value assigned accordingly to the current combination.

So every two bit of digital data can be transferred as an assigned digital voltage value accordingly through the transfer line to the receiving side where Part B of the invention reverses the process. The Part B for every one of its input lines has two respective output lines.

Every line of transfer will be subjected to four different digital voltage values.

The invention it will greatly enhance the capacity of digital data or signal transfer.

In many digital devices the further physical expansion of the bus data transfer lines it is difficult and in some occasions it is not cost-efficient.

The invention offers a direct double up of any existing digital data transfer capacity of any digital device. For many digital devices this could be quite an achievement. If only imagining a virtual double expansion of an address bus in a PC or any other computer without the problems the physical expansion has to offer.

Considering the contemporary technological achievements in electronic industry and electronic design, the problem of overcoming the inventions noise factor, it is quite possibly achievable.

The invention can be a new step in the digital technological evolution, no matter how small a step. It will inspire new developments in the digital technology. For example the contemporary memory devices are two state memories. Imagining a combination of the invention with four state memory devices in a digital computer or any other digital device, how much of all that digital information it will shrink in its physical form? Also the Two Bits per Line Transfer offers in some areas of digital data processing an enhancement of signal quality, such as video and sound.

The invention will now be described solely by way of exaiiipie and with rcfcrcnce to the accompanying drawings in which: Figure 1 shows a schematic drawing of the general functioning principle of the invention (Two Bits per Line Transfer), Figure 2 shows a schematic drawing of the basic functioning principle of the transmitter part of the invention (Part A), Figure 3 shows a schematic drawing of the basic functioning principle of the receiver part of the invention (Part B), Figure 4 shows a further detailed schematic drawing of the basic functioning principle of the transmitter part of the invention (Part A), Figure 5 shows a further detailed schematic drawing of the basic functioning principle of the receiver part of the invention (Part B).

In figure 1, a Two Bits per Line Transfer device including the transmitter (Part A) I and the receiver (Part B) 2 connected respectively at each side of the digital transfer lines 3 through the output lines of (for) the transmitter part (Part A) 6 and input lines of (for) the receiver part (Part B) 7.

The input lines 4 of the transmitter I are the input lines for the Two Bits per Line Transfer device (the invention) and the output lines 5 of the receiver 2 are the output lines for the Two Bits per Line Transfer device.

Figure 1 shows a Two Bits per Line Transfer device of eight bit capacity connected at four digital transfer lines. While the digital data or signal to be transferred it is of eight bit capacity, the digital transfer lines needed to carry it is four.

The Two Bits per Line Transfer can be of any desirable capacity depending on the need of its application and the limitations.

in figure 2 a schematic drawing of the basic functioning principle of the transmitter part of the Two Bits per Line where 4 it is the digital input lines and 6 it is the digital output line.

The connection ofNl to Al and N2 to A2, in figure 2, certifies that the binary logical state of II' at input 4 will generate a binary logical state of 1' at the output of AO and an output 0' at Al and A2. Considering that the TI and T2 will not change or affect the 0' output, respectively of Al and A2, but carry it as a true O'at their own output, the binary logical state at output 6 will be I'.

If the binary logical state input at 4 it is 1O',considering the lines of input from up to down in figure 2, then the A0 and A2 outputs will be a binary logical state 0' and the output of A I will be 1'.

The TI it is a digital component (or circuit) that for a binary logical state 0' at its input it will give a 0' at the output and for a value I' input it will give a I' at the output but to a increased digital voltage value compared to the input.

Let say for example:

If the input 1' at Ti = +SV then the output 1' at TI = +7.5V.

If the binary logical state input at 4 it is 01', considering the lines of input from up to down in figure 2, then the Al and A0 outputs will be a binary logical state 0' and the output of A2 will be I'.

The T2 as the TI it is a digital component (or circuit) that for a binary logical state 0' input will give a 0' at the output and for a value 1' input will give a I' at the output but to a decreased digital voltage value compared to the input.

Let say for example:

If the input I' at T2 = +5V then the output I' at T2 +3V.

If the binary logical state input at 4 it is OO',then the Al, AO and A2 outputs will be O'and the output at 6 will be also 0'.

So for every one of the four possible combinations of the two bits at input 4, there will be a different digital voltage output at 6 respectively.

The transmitter part of the Two Bits per Line Transfer (Part A), shown in figure 2 it is of two bit capacity.

One of a higher capacity can be constructed by considering a 2bit capacity transmitter as a basic cell and then multiply the number of these cells connected in parallel to a desirable or necessary capacity.

Depending in the characteristics and operating values of the main digital device that the invention may be integrated at, the TI and 12 can be designed to be configured in any possible way regarding their digital voltage output value that accordingly represent the respective combination at the input of the transmitter (Part A), as long as these values are considerably (acceptably) different from each other and also considerably different from the digital voltage value output of AO that represent the respective combination at the input of the transmitter (Part A).

For example:

For the logical state 1' as their input, the TI and 12 can be design to; both have (give) an output of logical state I' on a decreased digital voltage value regarding the digital voltage value of their input for the logical state 1' , but these must be considerably (acceptably) different from each other and the digital voltage value of A0 output for the logical state 1', or; vice versa, both have (give) an output of logical state 1' on an increased digital voltage value or any other possible combination as long as the above principle maintained.

The transmitter part (Part A) of the invention also can be designed in quite different ways as long as the basic principle of the invention it is maintained.

For example, different logical gates and different possible connections of these logical gates than ones shown in figure 2 can be used to design a Two Bits per Line Transfer transmitter.

In figure 3 a schematic drawing of the basic functioning principle of the receiver part of the invention where 7 it is the input line(s) and 5 it is the output lines.

TB it is a digital component which for every digital voltage value at its input that it is smaller than the digital voltage value for the logical state I' at the output of the TI, in the figure 2, it will have a logical state 0' at its output (OV) and for a digital voltage value at its input that it is equal to the digital voltage value for the logical state I' at the output of the 12, in the figure 2, it will have a logical state I' at its output equal to the logical state 1' of the main device that the invention (Two Bits per Line Transfer) may be integrated.

For example:

TB1 for digital input values of OV, +3V and +5' it will have a digital output of OV (logical state 0' of the main device that the invention may be integrated).

TBI for digital input value of +7.5V (logical state 1' at output of TI) it will have a digital output of +5V (logical state I' of the main device that the invention may be integrated).

So the output of TB I it will be logical state I' (of the main device) only if (or when) the output of the Al, figure 2, it is a logical state 1'.

N3 ensures (certifies) that if (or while) TBI output at logical state 1', the digital output of A3, A4 and consequently that of the AS will be a logical state 0' (OV) and vice versa.

AOB it is a digital component which for every digital voltage value at its input that it is different than the digital voltage value for the logical state' 1' of the AO, in the figure 2, it will have a digital output 0' (OV) and for a digital voltage value at its input that it is equal to the digital value of the logical state 1' of the A0, in figure 2, the AOB it will have a logical state I at its output equal to the logical state 1' of the main device that the invention may be integrated.

For example:

AOB for digital input values of OV and +3V and +7.SV it will have a digital output 0 (0V).

AOB for digital input value of +5V (logical state I' of A0) it will have a digital output of +SV (logical state 1' of the main device that the invention may be integrated).

Digital output of A3 it will be I only if (or when) TBI digital output 0 and the AOB digital output 1.

N4 ensures (certifies) that if (or when) digital output of A3 it is I (logical state 1') the digital output of A5 it isO (logical state 0') and vice versa.

TB2 it is a digital component which for every digital voltage value at its input, that it is equal to the digital voltage value for logical state 1' of the 12 output, in figure 2, it will have a logical state I' at its output equal to the logical state I' of the main device other wise TB2 output will be 0'.

For example:

TB2 for digital input values of OV, +5V and +7.5V it will have a digital output 0 (OV).

TB2 for digital input values of +3V it will have a digital output of +5V (logical state 1' of the main device).

The digital output of AS it will be only if (or when) A4 digital output 1 and A3 digital output 0.

The digital output of A4 it will be I only if (or when) TBI digital output 0 and TB2 digital output I. Considering the schematic arrangement of the Cl and C2: When TBI, A3 and AS outputs are a digital state 0 then the output 5 of the receiver it is a digital state of 0,0.

When TB I output digital state it is 1, the digital output state of the A3 and AS are 0 and therefore the digital output 5of the receiver (counting the lines from up to down) it is a digital state of 1,0 When TB I output digital state 0, A3 output digital state I and A5 output digital state 0 the output 5 of the receiver (counting the lines from up to down) it is a digital state of 1,1 When TBI output digital state 0, A3 output digital state 0 and AS output digital state I the output 5 of the receiver (counting the lines from up to down) it is a digital state of 0,1.

The receiver part capacity by default must match that of the transmittcr.

in figure 4 where TI, figure 2, it is comprised as a serial connection of Nil to N 12 (NOT logical gates).

NIl for a digital state 1' input will have an output of digital state 0' and vice versa, in accordance with the digital voltage values of the main device for both logical states.

N12 for a digital state 1' input will give an output of digital state 0' (OV) and for a 0' digital state input it will give a digital state I but to an increased digital voltage value compared to the main device's (that invention may be integrated at) digital voltage value for the logical state I'.

For example:

NI I input +5V output OV.

NI I input OV output +5V.

N12 input +5V output OV.

N 12 input OV output +7.5V.

In figure 4 where T2, figure 2, it is comprised as a serial ofN2l to N22 (NOT logical gates) The functioning principle of T2 it is the same as that of Ti but the N22 instead of increasing it does decrease the digital voltage for the logical state I of the output.

For example:

N21 input +5V output OV.

N21 input OV output +5V.

N22 input +5V output OV.

N22 input OV output +3V.

In figure 5 where TBI, figure3, it is comprised as a serial connection Zi to NBI2 to NBI I. Input at Zi it is the TB! input and the output of NB! I it is the output ofTBl.

ZI ensures (certifies) that only the digital voltage value for the logical state I at the output of Tl,figure 2, (+7.5V) will be considered by the TB1 as a logical statel input and the other three(OV,+3Vand +5V) all will be considered as a logical state 0.

The serial connection NBI2 to NBII functioning in the same principle as the serial connection N2 I to N22, figure 4, can decrease the digital voltage value for logical state I at the output (+7.5V) to equal the digital voltage value for the logical state I' of the main device (+5V).

For example:

Zi input +7.5V output +7.5V.

Zi input +5V output OV.

ZI input OV output OV.

ZI input +3V output OV.

N12 input +7.5V output OV.

N12 input QV output +7.5V.

Nil input +7.SV output OV.

Ni I input OV output +5V (logical state 1' for the main device where invention integrated).

In figure 5 where AOB, figure 3, it is comprised as serial connection of Z2 to one of the A6 inputs and the N3 connected to the other A6 input. The input of Z2 it is the input for AOB and the output of A6 it is the output of AOB.

Z2 ensures (certifies) that any digital voltage value smaller than the digital voltage value for the logical state I' of the A0 (+5V) it will be considered by the AOB as a digital state 0.

So the output of the A6 (the MB output) it will be logical state I', -5V, (the logical state I' of the main device) only when the input at Z2 it is equal to the output of the N3, meaning that it will be so only when the digital voltage value at the input 7 of the receiver it is +5V (the logical state 1' of the main device in this example).

In figure 5 where TB2, figure 3, it is comprised as the serial connection of the N3 1 to N32 to one of A7 inputs, the N4 I to N42 to one of A7 inputs, the input 7 of the receiver to the other input and the output of A7 to the serial connection NB2 I to NB22.

The input 7 to one of the inputs of A7 it is the input of TB2 and the other inputs respectively at N3 I and N41 can be considered as driving inputs for TB2.

The output of the NB22 it is the output for TB2.

The driving input at N31 it is the output of N3. The driving input at N41 it is the output of N4.

The serial connection N3 I to N32 and the serial connection N4 I to N42 function on the same principle as the serial connection N21 to N22 (T2), decreasing the digital voltage value for the logical state I from +5V at the input to +3Vat the output of the respective serial connection.

So the A7 output it will be logical state I' (+3V) only when the digital voltage value at the input 7 of the receiver it is +3V.

The serial connection NB21 to NB22 functions in the same principle as the serial connection Nil to N 12 (TI), increasing the digital voltage value of the logical state I from +3V at its input to +5V (logical state 1' for the main device) at its output.

The output of N22 (TB2 output) it will be logical state I' (+5V) only when the digital voltage value at the input 7 of the receiver it is +3V.

The function of ZI and Z2 may probably be achieved by other means and ways as long as the principle of the function holds.

The design of the receiver part must synchronise with that of the transmitter part.

Claims

Claims I. A Two Bits per Line Transfer device enabling the instant transfer of every two bits of digital data or digital signal per line transfer, by means (way) of transferring accordingly (appropriately) one of the four possible combination of every two bits of digital data or signal thorough a transfer line, where each of the four possible combinations it is identified or represented by a different and distinguishable digital voltage value assigned accordingly to the current combination.
2. A Two Bits per Line Transfer device according to claim 1, has a Part A, the transmitter, that for every two of its digital data or digital signal input lines, has a respective one digital output line.
3. A Two Bits per Line Transfer device according to claims I and 2, where the Part A the transmitter, it is identified as the part of the invention that assigns to every one of its own digital output lines of signal one of the four digital voltage values representing the current combination of the respective two input lines accordingly.
4. A Two Bits per Line Transfer device according to claim 1, has a Part B, the receiver identified as the part of the invention that reverses the process of the Part A,the transmitter, described in the claims 2 and 3.
5. A Two Bits per Line Transfer device according to claims 1, 2, 3 and 4, has a Part A connected at transmitting point (s) of digital data or signal, and a Part B connected at the receiving point (s).
6. A Two Bits per Line Transfer device according to claim 5, where the Part B has two digital data or signal output lines for every one of its own digital input lines respectively.
7. A Two Bits per Line Transfer device according to claims 5 and 6, where its digital data or signal input lines are the input lines of the Part A and the output lines are the output lines of the Part B.
8. A Two Bits per Line Transfer device according to claim 7, that its digital data or signal outputs will be equal in any regards to its digital data or signal inputs.
9. A Two Bits per Line Transfer device according to claim 3, conceived or constructed (partially) only as a Part A of the invention, the transmitter.