GB2449508A

GB2449508A - Cut-outs around pads in the interconnect path of multi- layered substrates

Info

Publication number: GB2449508A
Application number: GB0716790A
Authority: GB
Inventors: Amarjit Singh Bhandal
Original assignee: Texas Instruments Ltd
Current assignee: Texas Instruments Ltd
Priority date: 2007-05-22
Filing date: 2007-08-31
Publication date: 2008-11-26
Anticipated expiration: 2027-08-31
Also published as: GB0716790D0; GB2449508B; GB0709792D0

Abstract

A PCB or package substrate comprises a number of metal layers interleaved between a number of dielectric layers to form a stack and an electronic signal interconnect path comprising a plurality of micro-vias, each micro-via connecting a pair of adjacent metal layers. The micro-vias are positioned in a staggered arrangement in relation to each other, so that vertically adjacent micro-vias in the stack do not coincide in their alignment. This reduces the level of excess capacitance in the vicinity of the vias, and so causes their characteristic impedance to be closer to the 50 Ohm value implemented for the traces. In a further invention, the geometry of the landing pad associated with the via is arranged to minimize the area of the pad whilst maintaining mechanical stability (fig 5).

Description

OPTIMIZATION OF ORGANIC PACKAGING INTERCONNECT FOR GIGABIT

SIGNALLING

FIELD OF THE INVENTION

The present invention relates to multi-layered substrates and, more particularly, to an electronic signal interconnect path in said structure and a method of reducing impedance mismatch therein.

BACKGROUND OF THE INVENTION

Printed circuit boards (PCBs) and package substrates used to implement the interconnect between electronic devices generally consist of layers of conducting sheets sandwiched between layers of non-conducting (dielectric) sheets. Signals are transferred between devices by means of conducting strips of metal (traces) etched into the conducting sheets and vertical cylindrically shaped (in general) conducting components (vias, balls, bumps) placed through the dielectric layers to connect the traces. At the connection points between the vertical components (henceforth to be referred to as vias) and the traces, landing pads are etched into the conducting sheets to ensure the connection points between the traces and vias can cope with manufacturing tolerances.

By convention most high speed electronic signal interconnects are required to have a characteristic impedance of 50 Ohms.

Layered PCB and package substrate materials and their stack-ups are chosen to make it easy to implement 50 Ohm traces. However, the same is not true for the vias, which tend to have an excess capacitance due to coupling between their pads and the conducting layers above or below. This results in their characteristic impedance being below 50 Ohms. The effect of the change in impedance on a propagating signal is to cause the signal to reflect back towards its source rather than continue on towards its destination. The larger the difference in impedance between the traces and the vias, the greater the level of reflected signal (and corresponding reduction in transmitted signal)

SUMMARY OF THE INVENTION

The present invention provides a method of and a PCB or package substrate structure that reduces the level of excess capacitance in the vicinity of the vias, and so causes their characteristic impedance to be closer to the 50 Ohm value implemented for the traces. Accordingly, there is provided a PCB or package structure having a landing pad formed in an outermost metal layer, at least one of the dielectric layers in the stack having a cut-out pad in vertical alignment with and having a crosssection substantially similar in size to that of the landing pad.

According to another aspect of the invention, there is provided a PCB or package substrate comprising: a number of metal layers interleaved between a further number of dielectric layers to form a stack; and an electronic signal interconnect path comprising a plurality of micro-vias, each micro-via connecting a pair of adjacent metal layers. The micro-vias are positioned in a staggered arrangement in relation to each other, so that vertically adjacent micro-vias in the stack do not coincide in their alignment.

According to a further aspect of the invention, there is provided a PCB or package substrate comprising: a number of metal layers interleaved between a further number of dielectric layers to form a stack; a plurality of micro-vias, each micro-via connecting a pair of adjacent metal layers; and a patterned landing pad having a trace geometry of minimal area whilst maintaining a level of mechanical stability during use of the PCB or package substrate. Preferably, the patterned landing pad comprises a trace which has a staggered geometry in a horizontal plane lying parallel to the layers of the stack Advantageously, the present invention reduces the amount of impedance mismatch between the traces and vias in the PCB or package structure, thereby reducing the level of reflected signal and increasing signal transmission, without compromising mechanical reliability.

Advantageously, the present invention provides an improvement of one to two orders of magnitude in bit error rate (BER) when utilized in a high frequency Serial-Deserialjzer (SERDES) According to another aspect of the invention, there is provided a method of constructing a PCB or package substrate having the features of any one of the previous aspects of the invention described hereinabove.

Specific embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a schematic diagram of a cross-section through a organic build-up layered package substrate in accordance with a preferred embodiment of the invention; Figures 2a to 2e are schematic diagrams of cross-sections through layers lOm to the BOT layer of the layered package substrate shown in Figure 1 in accordance with a preferred embodiment of the invention; Figure 3a a graphical diagram showing a comparison of the die-end reflection coefficient for a short net, for an organic build-up layered package substrate formed according to conventional techniques and two preferred embodiments of the present invention; Figure 3b is a graphical diagram showing a comparison of the die-end reflection coefficient for a medium net, for an organic build-up layered package substrate formed according to conventional techniques and two preferred embodiments of the present invention; Figure 3c is a graphical diagram showing a comparison of the die-end reflection coefficient for a long net, for an organic build-up layered package substrate formed according to conventional techniques and two preferred embodiments of the present invention; Figures 4a is a graphical diagram showing a comparison of the transmission coefficient for a short net, for an organic build-up layered package substrate formed according to conventional techniques and two preferred embodiments of the present invention; Figures 4b is a graphical diagram showing a comparison of the transmission coefficient for a medium net, for an organic build-up layered package substrate formed according to conventional techniques and two preferred embodiments of the present invention; Figures 4c is a graphical diagram showing a comparison of the transmission coefficient for a long net, for an organic build-up layered package substrate formed according to conventional techniques and two preferred embodiments of the present invention; and Figure 5 is a diagram showing an alternate geometry for a patterned landing pad according to another embodiment of the invention.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS OF THE INVENTION

The present invention concerns a technique and structure for reducing the level of excess capacitance in PCB and layered package substrates due to coupling between landings pads and the conducting layers above or below them.

With reference to Figure 1, which shows a simplified cross-section through a layered package substrate structure, a number of conducting sheets (metal layers) are interleaved between a number of non-conducting sheets (dielectric layers) to form a first stack. A second stack is formed from a further number of metal layers interleaved between a further number of dielectric layers. Sandwiched in between the first and second stacks is an organic build-up core layer with a plated through hole (PTH) via connecting the lower most metal layer of the first stack with the upper most metal layer of the second stack. Pairs of adjacent metal layers in the second stack are connected to each other by micro-vias. The micro-vias are positioned in a staggered arrangement in relation to each other, so that vertically adjacent micro-vias in the stack do not coincide in their alignment.

Figures 2b and 2d show how vertically adjacent micro-vias may be coupled to form an interconnect path through the layered package substrate in accordance with alternate embodiments of invention.

As seen from Figure 1 and Figure 2a-e, the cut-out pads in the dielectric layers have the same, or a substantially similar, crosssection as that of the landing pad of the structure in layer 1OM.

Although the present invention has been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the scope of the invention as defined by the appended claims. --7-

Claims

WHAT IS CLAIMED IS: 1. A PCB or package substrate comprising: a number

of metal layers interleaved between a further number of dielectric layers to form a stack; and an electronic signal interconnect path comprising, a plurality of micro-vias, each micro-via connecting a pair of adjacent metal layers, wherein the micro-vjas are positioned in a staggered arrangement in relation to each other, so that vertically adjacent micro-vias in the stack do not coincide in their alignment.
2. A PCB or package substrate comprising: a number of metal layers interleaved between a further number of dielectric layers to form a stack; a plurality of micro-vias, each micro-via connecting a pair of adjacent metal layers; and a patterned landing pad having a trace geometry of minimal area whilst maintaining a level of mechanical stability during use of the PCB or package substrate.
3. A PCB or package substrate according to claim 2, wherein the patterned landing pad comprises a trace which has a staggered geometry in a horizontal plane lying parallel to the layers of the stack.
4. A PCB or package substrate according to any one of claims 1 to 3, wherein the or a landing pad is formed in an outermost metal layer, at least one of the dielectric layers in the stack having a cut-out pad in vertical alignment with and having a cross-section substantially similar in size to that of the landing pad.
5. A PCB or package substrate according to claim 1 or 2, wherein
6. A PCB or package substrate substantially as hereinbefore described.
7. A PCB or package substrate substantially as hereinbefore described with reference to Figure 1 of the drawings.
8. A PCB or package substrate substantially as hereinbefore described with reference to Figures 2a to 2e of the drawings.
9. A method of reducing impedance mismatch in an electronic signal interconnect path substantially as hereinbefore described
10. A method of forming a PCB or package substrate substantially as hereinbefore described with reference to Figure 1 of the drawings.
11. A method of forming a PCB or package substrate substantially as hereinbefore described with reference to Figures 2a to 2e of the drawings.