GB2440771A

GB2440771A - Adaptive regulation of current and voltage peaks by chopped gate drive adjustment

Info

Publication number: GB2440771A
Application number: GB0615967A
Authority: GB
Inventors: Shankar N Ekkanath Madathil; Miguel Cacheda Fondevila; Mark Robert Sweet
Original assignee: De Montfort University
Current assignee: De Montfort University
Priority date: 2006-08-11
Filing date: 2006-08-11
Publication date: 2008-02-13
Anticipated expiration: 2026-08-11
Also published as: GB2440771B; GB0615967D0

Abstract

The gate drive signal for an IGBT 20 is pulse-width-modulated at high frequency (20 MHz) during turn-on and turn-off to allow control of the gate drive strength. Reduction of gate drive reduces transient current peaks during turn-on and transient voltage peaks during turn-off. Measurements of deviations from the desired voltage and current peaks are fed back 22 to a mark-space controller 21 to allow adaptive adjustment of gate drive strength, which controls collector current rate of change (dIc/dt) and hence transient peak amplitudes. The switch control thus adapts automatically to any application. The gate drive circuit may be integrated into the same package as the IGBT.

Description

ACTIVE GATE DRIVER SYSTEM

The present invention relates to a universal adaptive gate driver system and method for a gate driven switching device. For example, the gate driven switching device may be a MOS controlled power switching device.

Gate driven switching devices are power devices that usually work in a switching mode, ie. switching between two states on (ideally working as a short circuit) and off (ideally working as an open circuit). These devices can be made to conduct when an appropriate gate voltage V9, above a threshold voltage VT is applied to them and the current is cut off if V9 drops below the threshold voltage. They are used in many different types of switching circuits, including those utilising hard and soft switching.

One example of a MOS controlled Power Switching device is an insulated Gate Bipolar Transistor (IGBT device). The IGBT device is the switching power device most used in high and moderate power applications because of its low on resistance and easy drive circuit requirements. Known IGBT device based switching circuits generate peaks in the voltage across the IGBT emitter and collector terminals (referred to herein as VCE) and peaks in the current passing through the IGBT device, ie. between the emitter and collector terminals (referred to herein as lc) as shown in Figure 2. These current and voltage peaks influence circuit reliability and efficiency.

Using as an example an IGBT device deployed in a basic switching circuit as shown in Figure 1, it can be seen from Figure 2, that the switching of the IGBT device generates a current peak (2) on turn-on and voltage peak (4) on turn-off. In Figure 1, the circuit parasitic IGBT device capacitances between the collector (c), emitter (e) and gate (g) terminals of the IGBT device are represented as Ccg. Cge and C and the parasitic inductance in the high power side of the switching circuit is represented by inductance Lp in Figure 1.

Typical IGBT device switching waveforms generated when the device is used as shown in Figure 1 are shown in Figure 2. During the turn-on transient (Figure 2a) as the gate voltage Vg switches to its on value, four stages I to IV (as identified in Figure 2a and shown in the table in Figure 3) can be distinguished: I. Vg nses as the capacitance of the IGBT device is charged by the gate current, while V remains relatively constant due to the gate voltage V9 being less than the threshold voltage VT of the IGBT device, ie. while V9<V1; II. When V9>V1 and while the gate voltage V9 continues to rise, the gate current charges the gate-source capacitance Cge and discharges the gate-collector capacitance C as V decreases quickly. At this stage I starts to rise quickly; Ill. When V decreases, the gate collector capacitance C increases due to the Miller effect. Because of this V9 remains relatively constant while the gate current charges the gate-collector capacitance C as V falls slowly; and IV. When V falls below a specified value, V9 continues to rise and V8 continues to fall slowly.

The IGBT device overcurrent or current peak (2) generated during turn-on exists due to the reverse recovery of the freewheeling diode (D) of Figure 1.

The reverse current through the diode (0), roughly equivalent to the magnitude of the current peak (2) is proportional to the rate of change of current through the IGBT device dijdt, ie. the rate of change of current between the collector and emitter of the IGBT device.

During the turn-off transient (Figure 2b) as the gate voltage Vgg switches to zero or negative voltage value, again four stages I to IV (as identified in Figure 2b) can be distinguished: I. As soon as V9 decreases as the gate capacitance is discharged and V rises by a few volts. The decrease of V9 stops after some time due to the Miller effect; Il. During this V9 plateau, the gate current charges the gate collector capacitance C and V rises faster; III. Once the gate collector capacitance C is charged, V9 continues to decrease and V increases even faster. During this stage I starts to fall sharply; IV. When Vg falls below the threshold value VT for the IGBT device, V is at the applied voltage and l decreases slowly to zero due to recombination. r

When the IGBT device is turned off, an overvoltage or voltage peak (4) is generated due to the unclamping of the inductance Lp by the diode D. Again this peak voltage is proportional to the rate of change of current through the IGBT device dijdt, ie. the rate of change of current between the collector and emitter of the IGBT device.

It is known to control dijdt by controlling the gate current g or gate resistance R9 of the IGBT device during switching. However, reducing gate current (equivalent to increasing gate resistance in voltage driven circuits) so as to avoid these peaks is known to increase switching losses in the IGBT device.

In order to minimise these losses it is known to control the gate current only during those stages of turn-on (stage II only in Figure 2a) and turn-off (stages II and Ill in Figure 2b) in which dijdt can be controlled by controlling the gate current.

In order to achieve the best optimisation of the switching losses versus the control of dijdt, gate drivers have to differentiate between the different switching stages I to IV, described above in relation to Figure 2. This can be achieved by an inspection of the gate voltage, V9, the voltage between the collector and emitter terminals of the IGBT, V and the current through the IGBT, l. An active gate drive circuit for an IGBT device generally monitors currents and voltages on the IGBT device in order to optimise the switching and protect the IGBT device against fault conditions. r

These current and voltage peaks are known in other types of gate driven switching devices and it is known to control these peaks with appropriate gate driver circuits, however, known gate driver circuits are generally specific to the design of switching circuit in which the gate driven switching device is used.

The following optimisation methods are known to reduce the current and voltage peaks during the switching of gate driven switching devices, which can be classified into four different types: Close loop control: This method is designed to reduce the gate current depending on the magnitude of I and V for turn on, so as to compensate for the current peak and increase the gate current depending on the magnitude of l and V for turn off, so as to compensate for the voltage peak.

Gate capacitance change: This method alters the gate capacitance during specific switching stages.

Pulse codification control: This method codifies into a pulse signal the maximum and limited current switching stages so that time periods for stages with maximum current are represented into a pulse signal as a logic 1' and time periods for stages with minimum current are represented into a pulse signal logic 0'. The resulting signal is flows through a low pass filter and drives the device so as to deliver the desired current magnitudes to the device for the different switching stages. -Different gate current level changes: This method implements different current levels to drive the device at different stages of the switching r process, for example by using different current sources for the different stages.

A disadvantage with these approaches is that the design of the gate drive circuit is specific to the switching circuit within which the gate driven switching device is used. This is because the drive currents required to control dijdt so as to remove the current and voltage peaks depend on the design of switching circuit. This means that each time a gate driven switching device is used in a different switching circuit, the gate drive circuit has to be redesigned.

Therefore, if the gate drive circuit is to be integrated into the same package as the gate driven switching device, then the gate drive circuit needs to be able to calculate and set up the drive current dependent on the switching circuit in which the device is used.

The present invention aims to overcome this problem by providing an active gate driver circuit for a gate driven switching device which reduces the current and voltage peaks and which is independent of the switching circuit in which the device is used. This means that the gate driver circuit and the switching device are suitable to be integrated within a single package for end use.

In order to overcome this problem the present invention provides: an algorithm for calculating the optimum value of dijdt at turn-on and turn-off; and a method to control dijdt during switching.

This provides an active gate driver circuit with switching optimisation and peak suppression which can be integrated with the switching device. It can also enable such an integrated package to be directly driven by a digital signal without any additional interface or external components.

According to the present invention there is provided an adaptive gate driver system for driving one or more gate driven switching device(s): a Pulse Width Modulated (PWM) signal generator: for generating a primary PWM signal, having successive rising and falling portions referred to herein as switching portions, for driving such a switching device between its on and off state; for generating at least one secondary PWM signal of higher frequency than the first; and for superimposing the or one of the secondary PWM signals over the switching portions of the primary PWM signal so as to generate an Expanded PWM (EPWM) signal; a duty cycle control means for adjusting the duty cycle of the or each secondary PWM signal to compensate for current and/or voltage peaks through such a switching device generated by the switching portions of the primary PWM signal; and a gate driver circuit for receiving the EPWM signal and using it to drive such a device.

The adaptive gate driver system may be suitable for driving one or a plurality of gate driven switching devices.

As a simplification a single PWM signal can be used as.the secondary PWM signal, although preferably two secondary PWM signals of different frequencies can be used and the PWM signal generator superimposes a first of the secondary PWM signals over rising portions of the primary signal and a second of the secondary PWM signals over falling portions of the primary signal.

In order to provide accurate drive current to the device gate at turn-on (rising portion) and turn off (falling portion) the PWM signal generator generates the or each secondary PWM signal with a period 1, which is less than a minimum predicted time length of the switching time of the device. The switching time may be divided into a plurality of switching time stages, for example as described in relation to Figures 2 and 3, in which case the period T is less than a minimum predicted time length of the switching stages.

In order to compensate for current peaks in the device at turn-on and voltage peaks in the device at turn-off, the PWM signal generator may superimpose a first secondary PWM signal on the rising portions of the primary PWM signal with the duty cycle control means adjusting the duty cycle of the first PWM signal to compensate for a current peak at turn-on of the switching device and the PWM signal generator may superimpose a second secondary PWM signal on the falling portions of the primary PWM signal with the duty cycle control means adjusting the duty cycle of the second PWM signal to compensate for a voltage peak at turn-off of the switching device.

To do this, the duty cycle control means may comprise an error calculator for generating an error signal for each rising portion representing the size of the current peak and the duty cycle control means may adjust the duty cycle of the PWM signal to be superimposed on the next rising portion dependent on the error signal. In particular, the error calculator may calculate the error signal to be the size of the current peak as a proportion of the current level through the device when the device is switched on and may operate in accordance with the following rules, for each rising portion: if the error in the current peak is greater than zero and the device is on, reduce the duty cycle for the PWM signal superimposed on the next rising portion by the error signal; otherwise, increase the duty cycle for the PWM signal superimposed on the next rising portion by a predetermined amount.

The error calculator may also generate an error signal for each falling portion representing the size of the voltage peak and the duty cycle control means may adjust the duty cycle of the PWM signal superimposed on the next falling portion dependent on the error signal. In particular, the error calculator may calculate the error signal to be the size of the voltage peak as a proportion of the voltage across the device when the device is switched on and may operate in accordance with the following rules, for each falling portion: if the error in the current peak is greater than zero and the device is on, increase the duty cycle for the PWM signal superimposed on the next falling portion by the error signal; otherwise, decrease the duty cycle for the PWM signal superimposed on the next rising portions by a predetermined amount.

The duty cycle control means may be responsive to any one of or any combination of the following parameters of the gate driven switching device, so as to adjust the duty cycles: the current through the device; the gate voltage of the device; the device voltage, representing the voltage between the emitter and collector of the device; and the temperature of the device.

Monitoring of one or more of the above parameters may also be used by a fault protection system to protect the gate driven switching device against fault conditions. In addition, monitoring of the temperature of the device may be used in a temperature control system for maintaining the temperature of the device within desired limits. Such fault protection and temperature control systems may be integrated as part of the system or method according to the present invention.

The present invention also provides an integrated switching system comprising a system as described above integrated with one or more gate driven switching device(s).

The present invention also provides an adaptive method of driving a gate driven switching device, comprising the steps of: generating a primary PWM signal, having successive rising and falling portions referred to herein as switching portions, for driving such a device between its on and off state; generating at least one secondary PWM signal of higher frequency than the first; superimposing the or one of the secondary PWM signals over the switching portions of the primary PWM signal so as to generate an Expanded PWM (EPWM) signal; adjusting the duty cycle of the or each secondary PWM signal to compensate for current and/or voltage peaks through such a device generated by the switching portions of the primary PWM signal; and driving the device using the EPWM signal.

The method has the same preferred features as the adaptive gate driver system according to the present invention and as described above, and may be used to drive one or a plurality of gate driven switching devices.

Temperature control and fault protection features, which are well known in the art in relation to known gate driver systems can also be implemented into the adaptive gate driver system described above.

The adaptive gate driver system and method as described above can be used in applications with just one switching device. However, the same methodology can be applied to control different kinds of switching device combinations, such as parallel or series arrangements of switching devices.

The invention will now be described by way of example only and with reference to the accompanying schematic drawings, wherein: Figure 1 shows a basic switching circuit incorporating an IGBT device; Figure 2 shows the switching waveform for the IGBT device of Figure 1 against time at turn-on (Figure 2a) and turn-off (Figure 2b) for the gate voltage, V9, the voltage between the collector and emitter terminal of the IGBT device, V and the current through the IGBT device, I; Figure 3 shows a table of the IGBT device switching stages shown in Figure 2, the influence of each stage on dijdt and the optimum gate current va'ue for each stage; Figure 4 is a schematic representation of the EPWM signal waveform; Figure 5 shows schematically a circuit comprising an EPWM generator, gate driver circuit and an IGBT in a switching circuit, for demonstrating the efficacy of the present invention; Figure 6 show the results of a simulation of the circuit of Figure 5; Figure 7 shows graphs of the relationship between the current and voltage peaks as percentage of the final value of the currentIvoltage for the turn-on and turn-off duty cycles of the EPWM signal respectively; r Figure 8 shows schematically an embodiment of an adaptive gate drive system according to the present invention driving an IGBT device; Figure 9 shows a schematic block diagram an embodiment of an adaptive gate driver system according to the present invention for driving an IGBT device in a switching circuit; Figure 10 shows a further more detailed block diagram of the proposed adaptive gate driver system, of Figure 9; Figure 11 shows a suitable resistor based current sensor with galvanistic isolation, suitable for detecting a voltage proportional to the IGBT collector current, l; Figure 12 shows schematically a circuit implementation for turn-on of the block diagram of Figure 10; Figure 13 show the results of a simulation of the turn-on circuit of Figure 12 and shows the peaks in collector current with and without the use of the circuit of Figure 12; Figure 14 shows a circuit implementation for turn-off of the block diagram of Figure 10; Figure 15 show the results of a simulation of the turn-off circuit of Figure 14 and shows the peaks in collector current with and without the use of the circuit of Figure 14; Figure 16 shows a possible implementation of part of the gate drive system of Figure 10; and Figure 17 shows schematically a printed circuit board implementation of the block diagram of Figure 10.

The method of controlling dijdt during switching according to the present invention uses Extended Pulse Width Modulation (EPWM) and is described below, as an example, in relation to an IGBT device. r

To control dijdt in an IGBT device it is required to control the timing of the gate charge. This timing control is equivalent to controlling the current delivered to or recovered from the gate.

The basic PWM signal x(t) is described by the following equation: x(t) h(t -nT) where h(t) J0,O <t <t01, - V0fftp <1 <T These equations describe a two level (usually related to on/off or 0/1' states) periodic square wave with period T. The means value of this signal is given by: Xi,yg = havg = (v0 -V0ff).

where the t0/T ratio is called the duty cycle. Thus, during any time period t the PWM mean value x0(t) can be modified by changing the duty cycle over this period.

This PWM property can be applied to control the IGBT device gate current level and therefore, to control di0/dt. Thus, to supply a specific current level, 19, to an IGBT device gate during a time period t9 is equivalent to applying a PWM current signal to the gate with a specific duty cycle during the same time period t9, provided T<tg. That is, in the time period t9 there is at least one complete PWM signal period T. ( The present invention proposes the generation of a gate drive current signal composed by more than one, for example three, different PWM signals. A primary PWM signal is used, which is the usual waveform applied to the gate to control the energy delivered through the switching circuit when it is on to power the load. Then to control the IGBT device switching process, two more switching PWM signals can be superimposed on the primary PWM signal, provided for each signal the period T is less than a time period t,,,i,,, where t$Jfljfl is the minimum expected time period for any of the switching stages I to IV (as shown in Figure 3) either during turn-on or turn-off.

The Extended PWM (EPWM) waveform is shown partially in Figure 4. The primary PWM signal is the low frequency square waveform (6). Figure 4 also shows the higher frequency turn-on switching PWM signal (8) which is superimposed on the primary signal (6) at the rising edge (10) of each pulse of the primary PWM signal so as to control di,/dt at turn-on. Similarly, a higher frequency turn-off PWM signal (not shown) is superimposed at the falling edge (12) of each wave of the primary signal (6) so as to control dijdt at turn off. This EPWM method controls the IGBT device gate current by controlling two parameters; the turn-on PWM signal duty cycle and the turn-off PWM signal duty cycle.

The EPWM signal has the following parameters: Main frequency, fma,n -frequency of the primary PWM signal. This is the IGBT device switching frequency and usually is defined by the application for which the switching circuit is designed and is generally no more than 20kHz; Main duty cycle, dmain -duty cycJe of the primary PWM signal again defined by the application: Fast PWM frequency, ffa -frequency of the switching PWM signals, although the turn-on and turn-off switching PWM signals may each have a different frequency; Turn-on duty cycle, d0 -duty cycle of turn-on switching PWM signal, superimposed on the rising edge (10) of the primary signal; and Turn-off duty cycle, d0ff -duty cycle of turn-off switching PWM signal, superimposed on the falling edge (12) of the primary signal.

Thus, the main parameters, fmain and dmejn are determined by the application for which the switching circuit incorporating the IGBT is used. The parameters d0 and d0ff are calculated by the algorithm discussed below.

A suitable value for the frequency ftast can be determined by using the requirement that T<tsmjn, and T = frasj1. As an example, a typical switching time for high power IGBT device application is I ps. Then assuming that the switching stages each have a equal time length then the time period of each switching stage I to IV is t5 = 250ns. So an estimate of the upper limit could be (mm = 5Ons, which leads to a value of feast Of 20MHz.

Figure 5 shows a simple circuit designed to prove that EPWM is a valid method for controlling an IGBT device so as to reduce current and voltage peaks. The circuit includes gate driver circuit (14, 16) and an IGBT device incorporated in a basic switching circuit (18). An EPWM circuit (14) generates a digital EPWM signal of the type described above in relation to Figure 4 prior to amplification to reach Vd+ = 1 5V. Vd+ is the maximum voltage applied to the gate and so gate voltage switches between 0 and I 5V in this example. The EPWM signal parameters used are: frnain = 2OkHz dmajn = 0.5; and ffast = 20MHz.

The switching circuit (18) shown as an example in Figure 5 is similar to that shown in Figure 1 with an inductive load, using a commercial IGBT device switching 400V at 30A. In the power circuit an additional inductance has been introduced to represent parasitic inductance of a real circuit and the free-wheeling diode is not ideaL Also, shown is a gate driver circuit (16) which enables the use of different resistors at turn-on and turn-off.

This circuit was simulated with circuit simulation software Saber available from Synopsys Inc for different d0 and doff values in order to verify, in theory, that the EPWM signal is able to control dijdt at turn-on and turn-off in an IGBT device. The results of this simulation are shown in Figure 6 and show that with respect to values of d0 and d0ff, EPWM signals of the type described above can control dijdt of the IGBT device. Figure 6a shows that by decreasing d0 the current peak reduces (that is an effect of reducing dijdt at turn on). A similar effect can be observed in Figure 6b where the collector voltage peak is reduced by increasing doff. The simulation results also show that the EPWM signal introduces a delay into the IGBT device switching characteristics. Switching optimization requires current limitation in specific stages, but in the simulated circuit the EPWM is limiting the gate current on all switching stages introducing the switching delay.

The EPWM duty cycle at the rising edge of the primary PWM wave is related by a monotonic function, shown in Figure 7a, to the level of the turn-on current peak. Similarly, the EPWM duty cycle at the falling edge of the primary PWM wave is related by a monotonic function, shown in Figure 7b, to the level of turn-off voltage peak. Peaks are expressed as percentage of the final value of the current/voltage. Thus, for example, if the voltage switches between OV and bOy and the voltage peak reaches 150V then in these graph the peak is represented as 50%. This simple, quasi-linear relation is used, according to the present invention by a control algorithm discussed below to calculate automatically the optimum duty cycles required to reduce such peaks when detected.

In order for the gate driver circuit according to the present invention to be integrated with the gate driven switching device, the algorithm selected has to be independent of the parameters of the different application circuits in which the device could potentially be used.

Figure 8 shows a block diagram of the proposed adaptive gate drive system, integrated with the IGBT device used in a switch circuit (20). The error calculator block (22) generates an error signal which is proportional to the current or voltage peak and based on its value the duty cycle controller (21) increases or decreases the turn-on or turn-off PWM signal in order to reduce the error.

The adaptive gate drive system must include full on/off state detection to know whether the IGBT device is on or off. This detection is necessary because at turn-on, the lowest d0 value will reduce the current peak, but this duty cycle value will be too low to switch on the IGBT device. A similar situation happens at turn-off.

An adaptive algorithm is used to calculate the error signal at turn-on. One possible example of an adaptive algorithm which could be used is described by the following pseudo computer program code: if error_on>O and IGBT=on then d_on = d_on -delta*error_on; else don = don + delta; end Thus, when the IGBT device is switched on the system measures the error, ie.

the percentage of the magnitude of the current peak to the magnitude of the overall current level and checks that the IGBT device has reached its switched on state. With the IGBT device switched on, if such a current peak has been detected, d00 is reduced proportionally to the magnitude of the error. Thus, the over-current or current peak will be reduced at the next turn-on, If no error is detected or the IGBT device has not been switched totally on, d0 is increased so providing faster switching for the next turn-on.

The only difference between the algorithm for correcting the peak at turn-on and turn-off is that an error greater than zero at turn- on leads to a decrease in the duty cycle d0, whereas at turn-off such an error value leads to an increase in the duty cycle doff.

An adaptive gate driver system according to the present invention is shown in Figure 9. It is composed mainly be three sub-systems, which are the conditioning circuits (40), the control system (42) and the gate drive circuit (44) and provides the following features: * collector over-voltage/current suppression target; * EPWM IGBT gate control; * adaptive control algorithm; and * fully digital control circuits to increase noise immunity.

In order to provide an active gate drive circuit suitable forintegration the error calculation method has to be independent of the voltage/current absolute values. This method is mathematically described as follow: di(t) I zf------>error error = dt 0 otherwise However, the error signal contains no information regarding the magnitude of the over-voltage/current. To provide this information to the system a pulse width codifier can be used as a cheaper alternative to an ADC (Analog to Digital Converter).

Figure 10 shows a further more detailed block diagram of a proposed implementation of the adaptive gate drive system according to the present invention. The system shown in Figure 10 receives inputs i(t), v(t) and vg(t).

From these inputs, the conditioner blocks shown in Figure 10 provide the digital controller (24) the following digital signals: collector over-current measures (26) (in embodiment for turn-off collector over voltage measures (28)) -provided as pulses whose length is proportional to the over-current; collector current change detection (30) -this signal is 1' during the voltage/current edges and 0' when they have a stable value (in embodiment for turn-off collector voltage change detection); collector voltage high value (32): signal equal to 1' when voltage is near to its maximum value; and miller detection (34)-signal equal to 1' when v9(t) > Vmiiier.

From these signals the digital controller (24) generates the following signals: the optimum EPWM signal to be applied to the IGBT device through the gate drive circuit (36); and control signals to reset the over-voltage/current detectors after every turn on/off.

An example of a current sensor connected to the IGBT switching circuit and which can be used to obtain a voltage proportional to the IGBT collector current is shown in Figure 11 and is based on a small resistor (38). A transformer (40) provides galvanic isolation between the low and high power circuits.

A circuit implementation for turn-on of the system of Figure 10 is shown in Figure 12. This circuit was simulated using circuit simulation software Saber and generated the results of Figure 13, which shows the reduction in current peaks with EPWM control provided by the circuit of Figure 12. As can be seen, the IGBT device collector current peaks are significantly reduced by the use of the circuit of Figure 12 as compared to the peaks without it (peak in dotted lines at left hand side of Figure 13). r

A circuit implementation for turn-off of the system of figure 10 is shown in Figure 14 with the results of a simulation of the circuit using circuit simulation software Saber shown in Figure 15. It has been found that d0ff has to be reduced slowly when limited current stages have finished. Otherwise and abrupt end of the fast PWM at turn-off will occur, leading to additional IGBT device collector voltage peaks. In this way, the adaptive control of the turn-off using EPWM is more complex than the adaptive control of the turn-on using EPWM. However, Figure 15 does show reduction in the collector voltage peaks.

Figure 16 shows a possible implementation of part of the gate drive system of Figure 9. As shown in Figure 9, the adaptive gate driver system is composed mainly be three sub-systems, which are the conditioning circuits (40), the control circuit (42) and the gate drive circuits (44). The conditioning circuits (40) perform the function of providing values of i(t), v(t) and vg(t) to the control circuit (42). These values are provided by means of digital signals obtained from the input signals as described above. In Figure 16, the conditioner circuits (50) are implemented in a similar way as in Figure 12. In Figure 16, the control circuit (52) includes digital PWM generators and the gate driver circuit (54) is shown in more detail.

Operational amplifiers are used in the conditioning circuits (50) and are used to convert digital values coming from the control circuit (52) into analogue values which are powerful enough to switch the control circuit transistors. The gate driver (54) sources and/or sinks current from the IGBT device gate.

A vertical division can also be seen in Figure 16. The bottom sub-circuit (composed by Q3, Q8, Q9 and U3) and the middle sub-system (composed by Q2, Q6, Q7 and U2) have the same basic function of sinking current from the IBGT device gate. The difference between the bottom and middle sub-circuit is the current value they are able to sink. The upper sub-circuit (composed by Qi, Q4, Q5, UI and Q10) provides current to the IGBT device gate at turn-on. r

The gate drive circuit of Figure 16 requires three different power voltages. The voltage at the gate oscillates between OV and I 5V, but the control circuit (52) and gate driver (54) uses a reduced voltage range in order to work at higher frequencies. Thus, on the upper sub-circuit, the control circuit (52) and gate driver (54) switch between I OV and 1 5V and the middle and bottom sub-circuits switch between OV and 5V.

Simulation of the circuit of Figure 16 generates similar results to those shown in Figures 13 and 15.

The circuit of Figure 16 may for example be implemented in accordance with Figure 17. It is composed of the three sub systems on separate PCBs; the conditioner (60), control circuit (62) and gate driver (64), as is described above in relation to Figure 16. In addition, the design includes a CPLD/FPGA programmer board. A four layer PCB design is used for the conditioner (60) which leads to a smaller circuit which can work at high slew rate signals. A four layer design is also used for the control circuit (62). Here a MAX II CPLD from Altera, a crystal oscillator and connectors were used to form the control circuit (62). The gate driver circuit (64) can be implemented as an independent two layer PCB and a further board is necessary to implement the CPLD programmer (66), which functions to load the required configuration from the computer (68) to the CPLD of the control circuit (62).

In the examples of the present invention described herein, hard switching is utilised. However, it should be noted that the gate driver system according to the present invention can also be implemented using soft switching of resonant methodologies in order to decrease power consumption.

Claims

CLAIMS

1. An adaptive gate driver system for driving a gate driven switching device, comprising: a Pulse Width Modulated (PWM) signal generator: for generating a primary PWM signal, having successive rising and falling portions referred to herein as switching portions, for driving such a switching circuit between its on and off state; for generating at least one secondary PWM signal of higher frequency than the first; and for superimposing the or one of the secondary PWM signals over the switching portions of the primary PWM signal so as to generate an Expanded PWM (EPWM) signal; a duty cycle control means for adjusting the duty cycle of the or each secondary PWM signal to compensate for current and/or voltage peaks through the switching device generated by the switching portions of the primary PWM signal; and a gate driver for receiving the EPWM signal and using it to drive the device.

2. A system according to claim I wherein there are two secondary PWM signals of different frequencies and the PWM signal generator superimposes a first of the secondary PWM signals over rising portions of the primary signal and a second of the secondary PWM signals over falling portions of the primary signal.

3. A system according to claim I or claim 2 wherein the switching device is a MOS controlled power switching device.

4. A system according to any one of claims 1 to 3 wherein the PWM signal generator generates the or each secondary PWM signal with a period T, which is less than a minimum predicted time length of the switching time of such a switching device.

5. A system according to claim 4 wherein the switching time is divided into a plurality of switching stages and the period T is less than a minimum predicted time length of the switching stages.

6. A system according to any one of the preceding claims wherein the PWM signal generator superimposes a first secondary PWM signal on the rising portions of the primary PWM signal and the duty cycle control means adjusts the duty cycle of the first PWM signal to compensate for a current peak at turn-on of such a switching device and the PWM signal generator superimposes a second secondary PWM signal on the falling portions of the primary PWM signal and the duty cycle control means adjusts the duty cycle of the second PWM signal to compensate for a voltage peak at turn-off of such a switching device.

7. A system according to any one of the preceding claims wherein the duty cycle control means is responsive to any one of or any combination of the following parameters of such a gate driven switching device, so as to adjust the duty cycles: the current through such a device; the gate voltage of such a device; device voltage, representing the voltage between the emitter and collector of such a device; and the temperature of such a device.

8. A system according to any one of the preceding claims wherein the duty cycle control means comprises an error calculator for generating an error signal for each rising portion representing the size of the current peak and the duty cycle control means adjusts the duty cycle of the PWM signal to be superimposed on the next rising portion dependent on the error signal.

9. A system according to claim 8 wherein the error calculator calculates the error signal to be the size of the current peak as a proportion of the current level through such a device when such a device is switched on and operates in accordance with the following rules, for each rising portion: if the error in the current peak is greater than zero and device is on, reduce the duty cycle for the PWM signal superimposed on the next rising portion by the error signal; otherwise, increase the duty cycle for the PWM signal superimposed on the next rising portion by a predetermined amount.

10. A system according to any one of the preceding claims wherein the duty cycle control means comprises an error calculator for generating an error signal for each falling portion representing the size of the voltage peak and the duty cycle control means adjusts the duty cycle of the PWM signal superimposed on the next falling portion dependent on the error signal.

11. A system according to claim 10 wherein the error calculator calculates the error signal to be the size of the voltage peak as a proportion of the voltage across such a device when such a device is switched on operates in accordance with the following rules, for each falling portion: if the error in the current peak is greater than zero and device is on, increase the duty cycle for the PWM signal superimposed on the next falling portion by the error signal; otherwise, decrease the duty cycle for the PWM signal superimposed on the next rising porUons by a predetermined amount.

12. A system according to any one of the preceding claims, wherein the duty cycle control means comprises: a sensor for sensing the current through the device so as to generate a current signal; a conditioning system for conditioning: the current signal; a gate voltage signal tapped from the device, representing the voltage across the gate of the device; and a device voltage signal tapped from the device, representing the voltage between the emitter and collector of the device, wherein the conditioned signals are used by the duty cycle control means in the adjustment of the duty cycles of the or each secondary PWM signal.

13. An integrated switching system compnsing a system according to any one of claim I to 12 and one or more semiconductor switching device(s) driven by the system.

14. An adaptive method of driving a gate of a gate driven switching device, comprising the steps of: generating a primary PWM signal, having successive rising and falling portions referred to herein as switching portions, for driving such a switching circuit between its on and off state; generating at least one secondary PWM signal of higher frequency than the first; superimposing the or one of the secondary PWM signals over the switching portions of the primary PWM signal so as to generate an Expanded PWM (EPWM) signal; adjusting the duty cycle of the or each secondary PWM signal to compensate for current andlor voltage peaks through such a semiconductor switching device generated by the switching portions of the primary PWM signal; and driving such a device with a gate drive circuit using the EPWM signal.

15. A method according to claim 14 wherein there are two secondary PWM signals of different frequencies and comprising the step of superimposing a first of the secondary PWM signals over rising portions of the primary signal and a second of the secondary PWM signals over falling portions of the primary signal.

16. A method according to claim 14 or claim 15 wherein the semiconductor switching device is a MOS controlled power switching device.

17. A method according to any one of claims 14 to 16 wherein the or each secondary PWM signal is generated with a period T, which is less than a minimum predicted time length of the switching time of such a switching device.

18. A method according to claim 17 wherein the switching time is divided into a plurality of switching stages and the period T is less than a minimum predicted time length of the switching stages.

19. A method according to any one of claims 14 to 18, comprising the steps of: superimposing a first secondary PWM signal on the rising portions of the primary PWM signal and adjusting the duty cycle of the first PWM signal to compensate for a current peak at turn-on of such a switching device; and superimposing a second secondary PWM signal on the falling portions of the primary PWM signal and adjusting the duty cycle of the second PWM signal to compensate for a voltage peak at turn-off of such a switching device 20. A method according to any one of the claims 14 to 19 additionally comprising the step of generating an error signal for each rising portion representing the size of the current peak and adjusting the duty cycle of the PWM signal to be superimposed on the next rising portion dependent on the error signal.

21. A method according to any one of claims 14 to 20 wherein the step of adjusting the duty cycle is responsive to any one of or any combination of the following parameters of such a gate driven switching device: the current through such a device; the gate voltage of such a device; device voltage, representing the voltage between the emitter and collector of such a device; and the temperature of such a device.

22. A method according to claim 20 comprising the step of calculating the error signal to be the size of the current peak as a proportion of the current level through such a device when such a device is switched on and adjusting the duty cycle in accordance with the following rules, for each rising portion: if the error in the current peak is greater than zero and device is on, reduce the duty cycle for the PWM signal superimposed on the next rising portion by the error signal; otherwise, increase the duty cycle for the PWM signal superimposed on the next rising portion by a predetermined amount.

23. A method according to any one of claims 14 to 22 additionally comprising the step of generating an error signal for each falling portion representing the size of the voltage peak and adjusting the duty cycle of the PWM signal superimposed on the next falling portion dependent on the error signal.

24. A method according to claim 23 wherein comprising the step of calculating the error signal to be the size of the voltage peak as a proportion of the voltage across such a device when such a device is switched on and adjusting the duty cycle in accordance with the following rules, for each falling portion: if the error in the current peak is greater than zero and device is on, increase the duty cycle for the PWM signal superimposed on the next falling portion by the error signal; otherwise, decrease the duty cycle for the PWM signal superimposed on the next rising portions by a predetermined amount.

25. A method according to any one of claims 14 to 24, additionally comprising one or more of the steps a. to d. of: a. sensing the current through the device so as to generate a current signal; b. generating a gate voltage signal tapped from the device; c. generating a device voltage signal tapped from the device, representing the voltage between the emitter and collector of the device; d. sensing the temperature of the device so as to generate a temperature signal; and using the one or more of the signals in the steps of altering the duty cycle of the or each secondary PWM signal.