GB2439125A

GB2439125A - DQPSK timing estimation using quaternary to polar conversion

Info

Publication number: GB2439125A
Application number: GB0611680A
Authority: GB
Inventors: Chris Stratford
Original assignee: Siconnect Ltd
Current assignee: Siconnect Ltd
Priority date: 2006-06-13
Filing date: 2006-06-13
Publication date: 2007-12-19
Also published as: GB0611680D0

Abstract

A timing estimator for Differential Quaternary Phase Shift Keying demodulation receives two quaternary components of a modulated signal. The timing estimator uses the CORDIC algorithm to convert the quaternary components into polar co-ordinates. A symbol timing estimation means uses the phase component of the polar co-ordinates to produce a timing estimation signal by determining phase differences for a number of taps in a delay period.

Description

Phase Shift Keying Demodulator The present invention is concerned with

a demodulator for a phase shift keying (PSK) signal. It is particularly, but not exclusively, directed to Differential Quaternary Phase Shift Keying (DQPSK).

Symbol timing estimation is an essential element of demodulation in a PSK system.

Detection of phase shifts, and thus data, can only be achieved by having a robust timing estimation to ensure that phase is measured effectively. Sampling can easily become early or late, and recovery of timing is required in order to ensure a robust demodulator.

A typical conventional timing estimator for a DQPSK demodulator is illustrated in figure 1. The estimator 10 is supplied with a modulated signal as a received signal which is transmitted from a transmitter (not shown). For example, the modulated signal is produced by differential quadrature phase shift keying (DQPSK) in the transmitter.

Using such a modulation, the data borne on the signal is represented by phase information, rather than amplitude or frequency. The estimator 10 is operable to demodulate the received signal into a demodulated signal by differential detection.

The illustrated embodiment in figure 1 presumes that measurements have been taken from the received signal to derive signals at quadrature -i.e. candidate I and Q signals.

However, it will be appreciated that the veracity of these I and Q signals depends on the phase synchronisation of the receiver with the transmitter, and the channel between these may cause shift in the phase during transmission. Feedback from the decoded signal can improve this estimation, and thereby impart suitable correction to take account of rotation imposed by the channel.

The illustrated estimator 10 thus includes means for processing these two input signals together. A symbol period delay unit 12 imposes a 1 symbol period delay to the received signals, and the delayed signals are then passed together with the original received signals to a signal state transition detector 14. This removes the differential element of the signals, reverting them to absolute values.

The processed signals are then passed to a matched filters array 16, which is illustrated in further detail in figure 2.

The signals enter the array 16 and are passed to respective delay lines 22. These delay lines 22 present the signals to complex multipliers 24 which multiply the complex values from the respective delay lines 22 with taps of a rotational clock signal. The complex products are then presented to a summing unit 26 which then passes a summation signal to a normaliser 28 which renders the signal conforniant with an expected amplitude range. This then provides a timing estimates back to other components of the demodulator.

Although this is theoretically a suitable approach, and is widely adopted in the state of the art, it can lead to complications in hardware implementation. It is an object of the invention to provide an approach to demodulation which takes account of hardware implementation and limitations thereon.

According to a first aspect of the invention, there is provided a timing estimator for QPSK demodulation, the timing estimator being operable to receive two quaternary components of a modulated signal, the timing estimator comprising reference frame conversion means for converting said quaternary components into a corresponding phase component of a polar reference frame, and symbol timing estimation means operable on the phase component to produce a timing estimation signal.

According to a second aspect of the invention, there is provided a method of estimating timing for use in QPSK demodulation, comprising receiving two quaternary components of a modulated signal, converting said quaternary components into a corresponding phase component of a polar reference frame, and producing a timing estimation signal from said phase component.

Further aspects of the invention will now be described by a specific embodiment of the invention, by way of example only, with reference to the accompanying drawings, in which: Figure 1 illustrates a timing estimator in accordance with a prior art example set out above; Figure 2 illustrates a matched filter array in the example set out in figure 1; Figure 3 illustrates a timing estimator in accordance with a specific embodiment of the invention; and Figure 4 illustrates a matched filters array in the timing estimator illustrated in figure 3.

As shown in figure 3, a timing estimator 100 is shown, in accordance with a specific embodiment of the invention. As previously, the timing estimator 100 is operable to received a pair of signals defining the received signal resolved into two orthogonal reference phases, noted as I and Q in the drawing.

The timing estimator 100 comprises a Cartesian to Polar converter 104 operable to convert the two input signals into an argument of a polar coordinate description of the signal, with reference to the fact that the I and Q elements can be considered as, respectively, x and y coordinates in a Cartesian reference frame in IQ space. The Cartesian to Polar converter is implemented by use of the CORI)IC algorithm, which is widely adopted as a hardware method of making this conversion, and has been used for trigonometric calculations in pocket calculators for many years.

In this example, piI2-DQPSK is employed, which means that the magnitude part of the polar coordinates can be discarded. Only the phase part of the polar coordinate form of the input signal needs to be retained. This is then forwarded to a symbol period delay unit 112, which imposes a 1 symbol period delay to the phase signal, and the delayed phase signal is then passed together with the non-delayed phase signal to a signal state transition detector 114. This removes the differential element of the phase signal, reverting it to a stream of absolute values. No normalisation is required.

It will be noted that due to this Cartesian to Phase conversion, only one signal needs to be processed in this way.

The processed signal is then passed to a matched filter array 116 as illustrated in figure 4. This matched filter array 116 comprises a single delay line 122 which the phase signal enters. The delay line 122 presents the signal to adders 124 which subtract the signal from a respective tap of a rotational clock signal with which the input signal is intended to be locked. The consequent differences are then presented to a summing unit 126 which then passes a summation signal to a minimum phase detection unit 128, the output of which constitutes the timing estimation for use elsewhere in the demodulator.

This approach is advantageous because it allows use of differences in the match filter, rather than complex products. A complex product, such as would be found in the prior art example, would require in a hardware implementation, four multipliers and two subtractors. This could be expensive of chip area. In contrast, the specific embodiment above uses one subtractor per tap.

This saving can be captured in two ways, or a combination of the two. It is generally held that 64-80 taps are required to impart sufficient robustness to a timing estimator.

Therefore, the chip area saving for one timing estimator could be considerable. Power consumption could be decreased. Moreover, the chip area could be used for additional teclmology, or to provide space for additional taps if additional robustness is desired.

Whereas the invention has been described in the context of a specific embodiment for use with piI2-DQPSK, it will be appreciated that the same approach can be taken with any quadrature based modulation scheme.

While the foregoing represents a suitable example of a specific embodiment of the invention, it will be understood that this is but one of a plurality of other possible embodiments of the invention. Variations from the above will be recognised by the skilled person, and should not be considered to fall outside the scope of the invention.

The scope of the invention should be considered as defined by the accompanying claims, read in conjunction with the description, and with the appended drawings.

Claims

CLAIMS: 1. A timing estimator for QPSK demodulation, the timing

estimator being operable to receive two quaternary components of a modulated signal, the timing estimator comprising reference frame conversion means for converting said quatemary components into a corresponding phase component of a polar reference frame, and symbol timing estimation means operable on the phase component to produce a timing estimation signal.

2. A timing estimator in accordance with claim 1, wherein the symbol timing estimation means is operable to determine phase differences between a timing estimate and the phase component, for a plurality of taps in a delay period.

3. A timing estimator in accordance with claim 2 wherein the symbol timing estimation means is operable to add said determined phase differences to generate a timing estimation signal.

4. A timing estimator in accordance with any preceding claim wherein said QPSK modulation comprises DQPSK.

5. A timing estimator in accordance with claim 4 and further comprising integrating means operable on the phase component, the symbol timing estimation means being operable on the resultant integrated signal.

6. A timing estimator in accordance with claim 5 wherein said integrating means comprises means for determining a difference between a signal and said signal at a delay of one QPSK symbol.

7. An integrated circuit comprising a timing estimator in accordance with any preceding claim.

8. A QPSK demodulator comprising a timing estimator in accordance with any of claims 1 to 7.

9. A QPSK demodulator in accordance with claim 8 wherein said demodulator is a DQPSK demodulator.

10. A demodulator in accordance with claim 9 wherein said demodulator is a piI2-DQPSK demodulator.

11. A method of estimating timing for use in QPSK demodulation, comprising receiving two quaternary components of a modulated signal, converting said quaternary components into a corresponding phase component of a polar reference frame, and producing a timing estimation signal from said phase component.

12. A method in accordance with claim 11, comprising determining phase differences between a timing estimate and the phase component, for a plurality of taps in a delay period.

13. A method in accordance with claim 12 comprising adding said determined phase differences to generate a timing estimation signal.