KR100764356B1 - A timing estimator in a oqpsk demodulator - Google Patents

Abstract

The timing estimator of the OQPSK demodulator of the present invention includes an A / D converter for converting analog received signals Ir and Qr into digital received signals r (k); After delaying the digital received signal from the A / D converter by a predetermined time, the conjugate complex signal r (k-1Tc) of the delayed digital received signal and the digital received signal r (from the A / D converter) k)) a differential circuit unit for phase difference to cancel the frequency error present in the digital received signal r (k); A correlation calculation unit obtaining a correlation value by performing a correlation operation between the reference symbol differentiated in the same manner as the derivative of the differential circuit unit and the received signal from the differential circuit unit; And a synchronization detection unit that detects a synchronization time point based on the correlation value from the correlation calculation unit.

 Zigbee Receiver, OQPSK Demodulator, Timing Estimator

Description

TIMING ESTIMATOR IN A OQPSK DEMODULATOR}

1 is a block diagram of a timing estimator of a conventional OQPSK demodulator.

2 is a basic configuration diagram of a timing estimator of the OQPSK demodulator according to the present invention.

3 is a configuration diagram of a differential circuit of FIG. 2.

4 is a modified configuration diagram of a timing estimator of the OQPSK demodulator according to the present invention.

5 is a configuration diagram of a differential circuit of FIG. 4.

Explanation of symbols on the main parts of the drawings

Ir, Qr: Analog Receive Signal 100: A / D Converter

r (k): Digital receiving signal 200: Differential circuit part

201: delay unit 202: conjugate complex part

203: Multiplier 210: First Differentiator

220: second minute 230: third third minute

300: correlation calculation unit 301: first matched filter

302: second matched filter 303: third matched filter

304: fourth matched filter 305: first adder

306: Second adder 307: First square part

308: second square part 309: adder

310: first correlation operator 320: second correlation operator

330: third correlation operator 340: output adder

400: synchronization detection unit

The present invention relates to a timing estimator of an OQPSK demodulator applied to a Zigbee receiver. In particular, the present invention implements a phase difference between a conjugate complex signal of a received signal delayed in a set time and a received signal to cancel a frequency error of the received signal, thereby realizing a frequency error. The present invention relates to a timing estimator of an offset quadrature phase shift keying (OQPSK) demodulator capable of improving reception performance deterioration.

Recently, Ubiquitous, which means a communication environment that can be connected to a network anytime, anywhere regardless of time and place, has been proposed, and a small wireless communication system, for example, WLAN (Wireless) rather than a large communication network such as a cellular network, has been proposed. Local area network (WPAN), wireless personal area network (WPAN), sensor network and RFID are being actively researched.

Among such wireless communication systems, in particular, in the field of WPAN or / and sensor networks, not only communication performance, but also small size, low power consumption, and low price are the main requirements. In such wireless communication systems such as WPAN, existing cellular communication systems and WLAN systems are required. It is difficult to apply the high performance expensive equipment or components used in the market as it is. On the contrary, if the low cost components are adopted to lower the price, a large frequency error or phase error that cannot be ignored may occur in the receiver. In this regard, measures are required.

In view of such a situation, in a communication system environment, a demodulator capable of exhibiting excellent performance without using expensive equipment or products should be researched and developed. In particular, receivers receiving OQPSK symbol packets should be able to perform symbol synchronization more accurately.

In addition, the OQPSK demodulator includes a timing estimator to accurately recover a symbol in a received signal. This conventional timing estimator will be described with reference to FIG. 1.

1 is a block diagram of a timing estimator of a conventional OQPSK demodulator.

The timing estimator of the conventional OQPSK demodulator shown in FIG. 1 includes a frequency synchronization / phase synchronization processing unit 5 which processes frequency synchronization and phase synchronization with respect to an RF signal or an IF signal, and from the frequency synchronization / phase synchronization processing unit 5. A / D converter (ADC) 10 for converting the analog received signals Ir and Qr into digital received signals, and a correlation operation between the signal from the A / D converter ADC 10 and the reference symbol Performing a correlation calculation unit 20 for obtaining each correlation value and a synchronization detection unit 30 for determining a simultaneous point in time at which the largest correlation value among the correlation values from the correlation calculation unit 20 is detected and outputting a synchronization signal. Include.

The correlation calculating unit 20 performs a correlation between the received signal real part r {r (k)} and the real part r {s (k) of the reference symbol from the A / D converter 10. 1 matched filter 21, the correlation between the received signal imaginary part im {r (k)} and the imaginary part im {s (k) of the reference symbol from the A / D converter 10 A second matched filter 22 and an adder 23 for adding correlation values of the first and second matched filters 21 and 22.

In this case, when the reception signal r (k) and the reference symbol s (k) are defined as Equation 1 below, the signals S1 and S2 output from the A / D converter 10 are represented by the following equation. It is expressed as Equation 2. The real part S3 (r {s (k)) of the reference symbol and the imaginary part S4 (i {) of the reference symbol respectively input to the first matched filter 21 and the second matched filter 22, respectively. s (k)) is represented by Equation 3 below, wherein the output signals S5 and S6 of the first matched filter 21 and the second matched filter 22 are represented by Equation 4 below.

일 경우에 간단히 정리될 수 있다.In addition, the output signal S7 of the adder 23 is expressed as Equation 5 below, Equation 6 is expressed by Equation 5,

In this case it can be summarized simply.

However, in the conventional OQPSK or demodulation method, when there is a phase error or a frequency error component in the final correlation output S7, the correlation result is very low even at the point of synchronism due to the influence, so that accurate synchronization cannot be obtained.

Thus, in the case of conventional PSK series signals, synchronous demodulation is generally performed. Synchronous demodulation is included in r (k) by exactly matching the synchronization of the RF signal received at the front end of the A / D converter with the local oscillator (LO) of the receiver. Correlation is performed after removing both frequency and phase errors.

However, in the conventional method, although the performance is good, the system for removing the frequency error and the phase error is very complicated, and thus there is a problem that it is not suitable for applying to a low power, miniature system.

The present invention has been proposed to solve the above problems, and an object thereof is to implement a phase difference between a conjugate complex signal of a received signal delayed by a set time and a received signal to cancel a frequency error of the received signal, thereby providing a frequency error. The present invention provides a timing estimator for an OQPSK demodulator capable of improving reception performance deterioration.

In order to achieve the above object of the present invention, the timing estimator of the OQPSK demodulator of the present invention, the A / D converter for converting an analog received signal into a digital received signal; After delaying the digital reception signal from the A / D converter by a predetermined time, the phase difference between the conjugate complex signal of the delayed digital reception signal and the digital reception signal from the A / D converter is present in the digital reception signal. A differential circuit unit for canceling a frequency error to be made; A correlation calculation unit obtaining a correlation value by performing a correlation operation between the reference symbol differentiated in the same manner as the derivative of the differential circuit unit and the received signal from the differential circuit unit; And a synchronization detection unit that detects a synchronization time point based on the correlation value from the correlation calculation unit.

The differential circuit unit may include: a delayer configured to delay a digital reception signal from the A / D converter by a predetermined time; A conjugate complex unit for extracting a conjugate complex signal from the signal from the delay unit; And a multiplier that multiplies the digital received signal from the A / D converter and the conjugate complex signal from the conjugate complex unit.

The correlation calculator comprises: a first matched filter for correlating the real part of the reference symbol differentiated in the same manner as the derivative of the digital received signal and the real part of the digital received signal from the differential circuit part; A second matched filter for correlating the imaginary part of the differential symbol and the imaginary part of the digital received signal from the differential circuit part in the same manner as the derivative of the digital received signal; A third matched filter for correlating the real part of the reference symbol differentiated in the same manner as the derivative of the digital received signal and the imaginary part of the digital received signal from the differential circuit part; A fourth matched filter for correlating the imaginary part of the reference symbol differentiated in the same manner as the derivative of the digital received signal and the real part of the digital received signal from the differential circuit part; A first adder for adding correlation values of the first and second matched filters; A second adder for adding correlation values of the third and fourth matched filters; A first square unit which squares an addition value of the first adder; A second square unit that squares an addition value of the second adder; And an adder for adding the square values of the first and second square parts.

The differential circuit unit respectively delays the digital reception signal from the A / D converter by a predetermined different time, extracts a conjugate complex signal from the delayed digital reception signal, and then connects each digital signal from the A / D converter. And a plurality of differentiators for multiplying each conjugate complex signal to cancel a frequency error present in the digital reception signal from the A / D converter.

The correlation calculating unit may perform a correlation operation between the corresponding reference symbols differentiated in the same manner as the derivative of the plurality of digital reception signals from the plurality of differentiators of the differential circuit unit and the respective digital reception signals to obtain respective correlation values. A correlation operator; And an output adder for adding each correlation value from the plurality of correlation calculators.

The differential circuit unit delays the digital reception signal from the A / D converter by a predetermined first time, extracts a conjugate complex signal from the delay signal, and multiplies the digital reception signal by the conjugate complex signal to generate the digital signal. A first differentiator for canceling the frequency error present in the received signal; Delaying the digital received signal from the A / D converter by a second predetermined time, extracting a conjugate complex signal from the delayed signal, multiplying the digital received signal by the conjugate complex signal, and presenting the digital received signal; A second differentiator canceling the frequency error; And delaying the digital reception signal from the A / D converter by a predetermined third time, extracting a conjugate complex signal from the delay signal, and multiplying the digital reception signal by the conjugate complex signal and present in the digital reception signal. And a third differentiator for canceling the frequency error.

The correlation calculator comprises: a first correlation calculator configured to perform a correlation operation between the signal from the first differentiator and a corresponding reference symbol; A second correlation calculator for performing a correlation operation between the signal from the second differentiator and a corresponding reference symbol; A third correlation calculator configured to perform a correlation operation between the signal from the third differentiator and a corresponding reference symbol; And an output adder for adding each correlation value from the first, second, and third correlation calculators.

Each of the first, second and third correlation calculators may be configured to correlate a real part of a reference symbol differentiated in the same manner as the derivative of the digital received signal and a real part of a digital received signal from the differential circuit part. filter; A second matched filter for correlating the imaginary part of the differential symbol and the imaginary part of the digital received signal from the differential circuit part in the same manner as the derivative of the digital received signal; And an adder configured to add correlation values of the first and second matched filters to the output adder.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings referred to in the present invention, components having substantially the same configuration and function will use the same reference numerals.

2 is a basic configuration diagram of a timing estimator of the OQPSK demodulator according to the present invention.

Referring to FIG. 2, the timing estimator of the OQPSK demodulator according to the present invention includes an A / D converter 100 for converting an analog received signal Ir and Qr into a digital received signal r (k) and the A / D converter 100. After delaying the digital received signal from the D converter 100 by a predetermined time, the conjugate complex signal r (k-1Tc) of the delayed digital received signal and the digital received signal r (from the A / D converter) k)) to phase-differentiate, to offset the frequency error present in the digital received signal r (k), and a predetermined time in the digital received signal from the A / D converter 100. Phase difference between the conjugate complex signal r (k-1Tc) delayed by and the digital reception signal r (k) from the A / D converter 100 and present in the digital reception signal r (k). Differential circuit portion 200 for canceling the frequency error, and the reference is differentiated in the same manner as the derivative of the differential circuit portion A correlation calculation unit 300 for performing correlation calculation between the ball and the received signal from the differential circuit unit 200 to obtain each correlation value, and a synchronization for detecting a synchronization time point based on the correlation value from the correlation calculation unit 300. The detector 400 is included.

3 is a configuration diagram of the differential circuit unit of FIG. 2.

Referring to FIG. 3, the differential circuit unit 200 includes a delay unit 201 for delaying the digital reception signal r (k) from the A / D converter 100 by a predetermined time and the delay unit. A conjugate complex unit 202 for extracting a conjugate complex signal from the signal from 201, the digital received signal r (k) from the A / D converter 100, and the conjugate complex unit 202 from the conjugate complex unit 202; A multiplier 203 that multiplies the conjugate complex signal.

The correlation calculating unit 300 may determine the real part Re {Ds (k)} of the reference symbol differentiated in the same manner as the derivative of the digital received signal and the digital received signal Dr (k) from the differential circuit part. The first matched filter 301 for correlating the real part Re {Dr (k)}, and the imaginary part Im of the reference symbol differentiated in the same manner as the derivative of the digital received signal Im {Ds (k) }) And a second matched filter 302 for correlating the imaginary part Im {Dr (k)} of the digital received signal Dr (k) from the differential circuit part, and the derivative of the digital received signal; In the same way, the real part Re {Ds (k)} of the differential reference symbol and the imaginary part Im {Dr (k)} of the digital reception signal Dr (k) from the differential circuit part are correlated. A third matched filter 303, an imaginary part Im (s (k)) of the reference symbols differentiated in the same manner as the derivative of the digital received signal, and a digital received signal Dr (k) from the differential circuit part. Of A first matched filter 304 for correlating the real part Re {Dr (k)} and a first value for adding correlation values S9 and S10 of the first and second matched filters 301 and 302. An adder 305, a second adder 306 that adds correlation values S11, S12 of the third and fourth matched filters 303, 304, and an adder S15 of the first adder 305; Square of the first and second squares (307, 308), the first and second squares (307, 308) squared the addition value (S16) of the second adder (306), and the first and second squares (307, 308) And an adder 309 that adds the values 2 | S15 |, 2 | S16 |.

4 is a modified configuration diagram of a timing estimator of the OQPSK demodulator according to the present invention.

Referring to FIG. 4, the timing estimator of the OQPSK demodulator according to the present invention is a modification of the timing estimator of the present invention illustrated in FIG. 2, and the differential circuit unit 200 and the correlation calculating unit 300 of the timing estimator of FIG. Each can be modified as follows.

Referring to FIG. 4, the differential circuit unit 200 delays the digital reception signal from the A / D converter 100 by a predetermined time, and takes the conjugate complex number of the delayed digital reception signal. A plurality of differentiators for multiplying each digital signal from the A / D converter (ADC) 100 by the respective conjugate complex signals to cancel the frequency error present in the digital received signal from the A / D converter 100 Include.

The correlation calculating unit 300 performs a correlation operation between the corresponding reference symbols differentiated in the same manner as the derivative of the differential circuit unit and each of the received signals from the plurality of differentiators of the differential circuit unit 200 to obtain each correlation value. And a correlation adder, and an output adder that adds each correlation value from the plurality of correlation calculators.

As an example of the differential circuit unit 200, as shown in FIG. 5, the first to third differentiators 210, 220, and 230 may be included.

The first differentiator 210 delays the digital reception signal from the A / D converter 100 by a predetermined first time 1TC, extracts a conjugate complex signal from the delay signal, and then delays the conjugated complex number. The signal is multiplied by the digital reception signal from the A / D converter 100 to cancel the frequency error present in the digital reception signal.

The second differentiator 220 delays the digital reception signal from the A / D converter 100 by a preset second time 2TC, extracts a conjugate complex signal from the delay signal, and then delays the conjugated complex number. The signal is multiplied by the digital reception signal from the A / D converter 100 to cancel the frequency error present in the digital reception signal.

The third differentiator 230 delays the digital reception signal from the A / D converter 100 by a predetermined third time 3TC, extracts a conjugate complex signal from the delay signal, and then delays the conjugated complex number. The signal is multiplied by the digital reception signal from the A / D converter 100 to cancel the frequency error present in the digital reception signal.

In addition, the first, second and third differentiators 210, 220, 230 of the differential circuit unit 200 may be implemented as shown in FIG.

5 is a configuration diagram of the differential circuit unit of FIG. 4.

Referring to FIG. 5, the first, second, and third differentiators 210, 220, and 230 will be described in detail. The first differentiator 210 may receive a digital reception signal r (r) from the A / D converter 100. k)) a delay unit 211 for delaying the predetermined first time 1Tc, a conjugate complex unit 212 for extracting a conjugate complex signal from the signal from the delay unit 211, and the A / D The multiplier 213 multiplies the digital received signal r (k) from the converter 100 by the conjugate complex signal from the conjugate complex unit 212.

The second differentiator 220 includes a delay unit 221 for delaying the digital reception signal r (k) from the A / D converter 100 by a predetermined second time 2Tc, and the delay unit. A conjugate complex unit 222 for extracting a conjugate complex signal from the signal from 221, a digital received signal r (k) from the A / D converter 100 and the conjugate complex unit 222 A multiplier 223 that multiplies the conjugate complex signal.

The third differentiator 230 includes a delay unit 231 for delaying the digital reception signal r (k) from the A / D converter 100 by a predetermined third time 3Tc, and the delay unit. A conjugate complex unit 232 for extracting a conjugate complex signal from the signal from 201, the digital received signal r (k) from the A / D converter 100, and the conjugate complex unit 232 A multiplier 233 to multiply the conjugate complex signal.

In addition, with reference to FIGS. 4 and 5, in relation to an implementation of the differential circuit unit 200, the correlation calculating unit 300 calculates a correlation between a signal from the first differentiator 210 and a corresponding reference symbol. From the first correlation operator 310, the second correlation operator 320 to perform a correlation operation between the signal from the second differentiator 220 and the corresponding reference symbol, and from the third differentiator 230. A third correlation calculator 330 that performs a correlation operation between the signal of S and a corresponding reference symbol, and an output adder 340 that adds each correlation value from the first, second, and third correlation calculators 310, 320, 330. It may include.

In this case, each of the first, second, and third correlation calculators 310, 320, and 330 may be formed from the real part Re {Ds (k)} of the reference symbol differentiated in the same manner as the derivative of the digital received signal and the differential circuit part. A first matched filter 301 for correlating the real part Re {Dr (k)} of the digital received signal Dr (k) and a reference symbol differentiated in the same manner as the derivative of the digital received signal A second matched filter for correlating the imaginary part Im {Ds (k)} with the imaginary part Im {Dr (k)} of the digital reception signal Dr (k) from the differential circuit part 302 and an adder 305 for adding the correlation values S9 and S10 of the first and second matched filters 301 and 302 to the output adder 340.

Hereinafter, the operation and effects of the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIGS. 2 to 6, a timing estimator of an OQPSK demodulator according to an embodiment of the present invention will be described. First, in the timing estimator of the present invention of FIG. 2, the A / D converter 100 includes an analog received signal Ir. , Qr is converted into a digital reception signal r (k) and output to the differential circuit unit 200.

) 및 수신신호(r(k))는 하기 수학식 7과 같이 표현되는 경우, 상기 A/D 컨버터(100)에서 출력되는 신호(S1,S2)는 하기 수학식 8과 같이 표현된다. First, the reference symbol (s (k)), the reference symbol is a non-referenced reference symbol (

) And the received signal r (k) are represented by Equation 7, the signals S1 and S2 output from the A / D converter 100 are represented by Equation 8.

The differential circuit unit 200 is a conjugate complex signal r (k-1Tc) delayed by a predetermined time from the digital reception signal from the A / D converter 100 and the digital signal from the A / D converter 100. The phase difference of the received signal r (k) is output to the correlation calculating unit 300. At this time, the differential circuit unit 200 cancels the frequency error present in the digital reception signal r (k).

The correlation calculating unit 300 performs a correlation operation between the reference symbol differentiated in the same manner as the derivative of the differential circuit unit and the received signal from the differential circuit unit 200 to obtain each correlation value to the synchronization detection unit 400. Output

The synchronization detector 400 detects a synchronization time point based on the correlation value from the correlation calculation unit 300 and outputs a synchronization signal.

The differential circuit unit 200 will be described with reference to FIG. 3.

In FIG. 3, the delay unit 201 of the differential circuit unit 200 delays the digital reception signal r (k) from the A / D converter 100 by a predetermined time so as to conjugate the complex unit 202. Output to

The conjugate complex unit 202 extracts a conjugate complex signal from the signal from the delayer 201 and outputs it to the multiplier 203.

The multiplier 203 multiplies the digital received signal r (k) from the A / D converter 100 by the conjugate complex signal from the conjugate complex unit 202 and outputs the result to the correlation calculating unit 300. .

Output signals S3 and S4 of the differential circuit unit 200 are expressed by Equation 9 below.

The correlation calculating unit 300 will be described with reference to FIGS. 2 and 3.

As shown in FIG. 2, when the correlation calculating unit 300 includes first to fourth matched filters 301 to 304, the first matched filter 301 may be configured to generate the digital received signal. The real part Re {Ds (k)} of the reference symbol differentiated in the same manner as the derivative and the real part Re {Dr (k)} of the digital reception signal Dr (k) from the differential circuit part are correlated. The second matched filter 302 calculates an imaginary part Im {Ds (k)} of the reference symbol differentiated in the same manner as the derivative of the digital received signal and the digital received signal from the differential circuit part. The imaginary part Im (Dr (k)} of (Dr (k)) is correlated, and the third matched filter 303 is a real number of the reference symbol differentiated in the same manner as the derivative of the digital received signal. The unit Re {Ds (k)} is correlated with the imaginary part Im {Dr (k)} of the digital reception signal Dr (k) from the differential circuit unit. The fourth matched filter 304 may include an imaginary part Im (s (k)) of the reference symbols differentiated in the same manner as the derivative of the digital received signal and a digital received signal Dr ( k)) and the correlation part Re {Dr (k)}.

In this case, in FIG. 2, when the real part and the imaginary part S5 to S8 of the reference symbol input to the first to fourth matched filters 301 to 304 are expressed by Equation 10, the first to The output signals S9 to S12 of the fourth matched filters 301 to 304 are expressed by Equation 11 below.

In addition, the first adder 305 of the correlation calculator 300 adds correlation values S9 and S10 of the first and second matched filters 301 and 302, and adds a second value of the correlation calculator 300 to the second adder 305. The adder 306 adds correlation values S11 and S12 of the third and fourth matched filters 303 and 304.

Next, the first square unit 307 of the correlation calculator 300 squares the addition value S15 of the first adder 305, and the second square unit 308 of the correlation calculator 300 is Then, the added value S16 of the second adder 306 is squared.

)을 가산한다.Next, the adder 309 of the correlation calculating unit 300 is a square value of the first and second square units 307 and 308.

Add).

In this case, each of the output signals S13 and S14 of the first and second adders 305 and 306 is represented by Equation 12, and each of the output signals S15 and S16 of the first and second square units 307 and 308, The output signal S17 of the adder 309 is expressed by Equation 13 below.

The timing estimator of the OQPSK demodulator of the present invention as described above with reference to FIGS. 2 and 3 cancels the frequency error included in the received signal through the differential circuit unit, thereby preventing degradation of reception performance caused by the frequency error. Can be.

On the other hand, when the timing estimator of the OQPSK demodulator of the present invention is deformed as shown in Figs. 4 and 5, it is possible to detect the synchronization more accurately.

The differential circuit unit 200 may include a plurality of differentiators, and may also include a plurality of correlation operators of the correlation operation unit 300, and with reference to FIGS. 4 and 5, another embodiment of the present invention. Explain the example.

As shown in FIGS. 4 and 5, the differential circuit unit 200 includes first to third differentiators 210, 220, and 230, and the correlation calculating unit 300 includes first, second and third correlation calculators ( A case including 310, 320, 330 will be described.

The first differentiator 210 delays the digital reception signal from the A / D converter 100 by a predetermined first time 1TC, extracts a conjugate complex signal from the delay signal, and then the digital reception signal. And the conjugate complex signal are multiplied to cancel the frequency error present in the digital received signal.

The second differentiator 220 delays the digital reception signal from the A / D converter 100 by a preset second time 2TC, extracts a conjugate complex signal from the delay signal, and then the digital reception signal. And the conjugate complex signal are multiplied to cancel the frequency error present in the digital received signal.

The third differentiator 230 delays the digital reception signal from the A / D converter 100 by a predetermined third time 3TC, extracts a conjugate complex signal from the delay signal, and then the digital reception signal. And the conjugate complex signal are multiplied to cancel the frequency error present in the digital received signal.

Referring to FIG. 5, in the first differentiator 210, first, in the delay unit 211, the digital reception signal r (k) from the A / D converter 100 is preset to a predetermined first time ( It delays by 1Tc) and outputs it to the conjugate complex part 212. The conjugate complex unit 212 extracts a conjugate complex signal from the signal from the delayer 211 and outputs the conjugate complex signal to the multiplier 213. The multiplier 213 multiplies the digital received signal r (k) from the A / D converter 100 by the conjugate complex signal from the conjugate complex unit 212 to form a first multiplication unit 300 of the correlation calculator 300. Output to correlation operator 310.

First, the second differentiator 220 delays the digital reception signal r (k) from the A / D converter 100 by a predetermined second time 2Tc in the delay unit 221. Output to the conjugate complex unit 222. The conjugate complex unit 222 extracts a conjugate complex signal from the signal from the delayer 221 and outputs the conjugate complex signal to the multiplier 223. The multiplier 223 multiplies the digital received signal r (k) from the A / D converter 100 by the conjugate complex signal from the conjugate complex unit 222 to generate a second signal of the correlation calculating unit 300. Output to correlation operator 320.

The third differentiator 230 firstly conjugates by delaying the digital reception signal r (k) from the A / D converter 100 by a predetermined third time 3Tc in the delay unit 231. Output to the complex number unit 232. The conjugate complex unit 232 extracts a conjugate complex signal from the signal from the delayer 231 and outputs the conjugate complex signal to the multiplier 233. The multiplier 233 multiplies the digital received signal r (k) from the A / D converter 100 by the conjugate complex signal from the conjugate complex unit 232 to generate a second signal of the correlation calculating unit 300. Output to correlation operator 330.

In addition, referring to FIG. 4, in relation to the implementation of the differential circuit unit 200, the correlation calculator 300 includes first, second and third calculators 310, 320, 330, and the correlation calculator 300. First correlation operator 310 performs a correlation operation between the signal from the first differentiator 210 and the corresponding reference symbol, and the second correlation operator 320 performs the second differentiator 220. A correlation operation between the signal from the reference symbol and the corresponding reference symbol is performed, and the third correlation calculator 330 performs a correlation operation between the signal from the third differentiator 230 and the reference symbol. The output adder 340 adds the correlation values from the first, second and third correlation calculators 310, 320, and 330.

In this case, each of the first, second and third correlation calculators 310, 320, 330 includes a first matched filter 301, a second matched filter 302, and an adder 305. The matched filter 301 is configured to determine the real part Re {Ds (k)} of the reference symbol differentiated in the same manner as the derivative of the digital received signal and the digital received signal Dr (k) from the differential circuit part. The real part Re {Dr (k)} is correlated, and the second matched filter 302 performs an imaginary part Im of the reference symbol differentiated in the same manner as the derivative of the digital received signal Im {Ds (k )}) And the imaginary part Im {Dr (k)} of the digital reception signal Dr (k) from the differential circuit part, and the adder 305 is configured to perform the first and second matched filters. Correlation values S9 and S10 of 301 and 302 are added and output to the output adding unit 340.

In this case, in FIG. 4, as described with reference to FIG. 2, if S3 and S4 are the same, the real part and the imaginary part S5, of the reference symbol input to the first and second matched filters 301 and 302, may be used. S6) may be represented by Equation 14, and the output signals S7 and S8 of the first and second matched filters 301 and 302 may be expressed by Equation 15 below.

The output signal S9 of the first adder 305 is expressed by Equation 16 below.

"의 크기를 줄일 수 있으므로 "

"에 의한 크기 감소를 최소화 할 수 있다.According to the present invention as described above, the phase error component due to the frequency error is not completely eliminated and affects the final correlation output value. However, the magnitude of the frequency error is determined by the analog frequency error component fo, the sampling period Ts, and the derivative time interval Tc of the differentiator.

So as to reduce the size of "

Size can be minimized.

In particular, the embodiment of Figure 4 of the present invention, when the frequency error size is not very large, compared to the embodiment of Figure 2 of the present invention, the performance degradation is not large and instead, the complexity of the system can be reduced a lot, and the low There is no effect of square loss in the noise ratio (S / N ratio) signal.

As described above, according to the present invention, a larger correlation value can be obtained. Accordingly, the failure rate of detection of the synchronization point is low, so that the simultaneous point detection can be performed quickly and the performance is also improved.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, but is defined by the claims, and the apparatus of the present invention may be substituted, modified, and modified in various ways without departing from the spirit of the present invention. It is apparent to those skilled in the art that modifications are possible.

According to the present invention as described above, in the timing estimator of the OQPSK demodulator applied to the Zigbee receiver, by performing a phase difference between the conjugate complex signal of the received signal delayed by the set time and the received signal to implement to cancel the frequency error of the received signal Therefore, there is an effect that can improve the reception performance degradation due to the frequency error.

In detail, the differential filter is used to reduce the influence of the frequency error, so that the reception performance can be improved by compensating for the degradation of the reception performance due to the frequency error, and the delay time of the differentiator even when the frequency error is very large. If the interval is set shorter than the chip period, performance deterioration due to phase error can be minimized. Therefore, a simple coherent correlation is not used instead of the conventional noncoherent method that causes square loss and increases complexity. By using the calculation unit, the performance improvement / equivalence (performance of the final proposed method over the initial improvement method) and complexity reduction can be obtained.

In addition, by performing multiple correlation operations corresponding to the multiple differential signals differentiated for a plurality of delay times, the results of these calculations are summed together to further improve performance. In other words, additional performance can be improved by using multiple differentiators and multiple correlation operators.

Claims (6)

An A / D converter converting an analog received signal into a digital received signal; After delaying the digital reception signal from the A / D converter by a predetermined time, the phase difference between the conjugate complex signal of the delayed digital reception signal and the digital reception signal from the A / D converter is present in the digital reception signal. A differential circuit unit for canceling a frequency error to be made; A correlation calculation unit obtaining a correlation value by performing a correlation operation between the reference symbol differentiated in the same manner as the derivative of the differential circuit unit and the received signal from the differential circuit unit; And A synchronization detector for detecting a synchronization time point based on a correlation value from the correlation calculator A timing estimator of the OQPSK demodulator comprising a. The method of claim 1, wherein the differential circuit unit, A delay unit for delaying the digital received signal from the A / D converter by a predetermined time; A conjugate complex unit for extracting a conjugate complex signal from the signal from the delay unit; And A multiplier that multiplies the digital received signal from the A / D converter and the conjugate complex signal from the conjugate complex unit Timing estimator of the OQPSK demodulator, comprising a. The method of claim 2, wherein the correlation calculation unit, A first matched filter for correlating the real part of the reference symbol differentiated in the same manner as the derivative of the digital received signal and the real part of the digital received signal from the differential circuit part; A second matched filter for correlating the imaginary part of the differential symbol and the imaginary part of the digital received signal from the differential circuit part in the same manner as the derivative of the digital received signal; A third matched filter for correlating the real part of the reference symbol differentiated in the same manner as the derivative of the digital received signal and the imaginary part of the digital received signal from the differential circuit part; A fourth matched filter for correlating the imaginary part of the reference symbol differentiated in the same manner as the derivative of the digital received signal and the real part of the digital received signal from the differential circuit part; A first adder for adding correlation values of the first and second matched filters; A second adder for adding correlation values of the third and fourth matched filters; A first square unit which squares an addition value of the first adder; A second square unit that squares an addition value of the second adder; And An adder for adding squares of the first and second squares; A timing estimator of the OQPSK demodulator comprising a. The method of claim 2, wherein the differential circuit unit, Respectively delaying the digital received signal from the A / D converter by a predetermined different time, extracting a conjugate complex number from the delayed digital received signal, and multiplying the A / D converter digital signal by the conjugate complex signal; Multiple Differentiators to Offset Frequency Error in Digital Received Signals from Digital / D Converters Timing estimator of the OQPSK demodulator, comprising a. The method of claim 4, wherein the correlation calculation unit, A correlation value is obtained by performing a correlation operation between each corresponding reference symbol differentiated in the same manner as the derivative of the plurality of digital received signals from the plurality of differentiators of the differential circuit unit and the respective digital received signals from the plurality of differentiators of the differential circuit unit. A plurality of correlation operators; And An output adder for adding each correlation value from the plurality of correlation calculators Timing estimator of the OQPSK demodulator, comprising a. The method of claim 5, wherein each of the plurality of correlation operators A first matched filter for correlating the real part of the reference symbol differentiated in the same manner as the derivative of the digital received signal and the real part of the digital received signal from the differential circuit part; A second matched filter for correlating the imaginary part of the reference symbol differentiated in the same manner as the derivative of the digital received signal and the imaginary part of the digital received signal from the differential circuit part; And An adder configured to add correlation values of the first and second matched filters to the output adder; A timing estimator of the OQPSK demodulator comprising a.

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