GB2434912A

GB2434912A - Semiconductor X-ray detector device structure

Info

Publication number: GB2434912A
Application number: GB0526075A
Authority: GB
Inventors: Arnab Basu; Ben Cantwell; Max Robinson; Andy Brinkman
Original assignee: Durham Scientific Crystals Ltd
Current assignee: Durham Scientific Crystals Ltd
Priority date: 2005-12-21
Filing date: 2005-12-21
Publication date: 2007-08-08
Also published as: WO2007072021A1; GB0526075D0

Abstract

A bulk semiconductor crystal detector layer (eg CdTe, CdZnTe) 300 of thickness of up to 11mm is grown by a bulk vapour deposition method on a substrate 100 comprising, for example, Si or GaAs, and on which electronic circuitry is provided. An intermediate lattice matching layer(s) 200 is/are provided between the substrate and the detector layer.

Description

SEMICONDUCTOR DEVICE STRUCTURE

FIELD OF INVENTION

The present invention relates to a novel semiconductor device structure.

BACKGROUND TO THE INVENTION

Semiconductor materials are used in many applications, including electronic circuits and detectors. Different semiconductor materials may be especially suited for use in particular applications For example, it is known to use materials such as cadmium telluride or cadmium zinc telluride (CZT) for detection of x-rays and gamma rays, since these materials are able to absorb 1 0 photons and generate an electrical signal in response Where different semiconductor materials are required for different uses, it is known to connect different semiconductor materials electrically together. For example, in the case of a detector, it is known to connect a semiconductor detector material to a semiconductor circuit using wire bonds or bump bonds.

SUMMARY OF THE INVENTION

According to the present invention, a semiconductor device structure comprises a first bulk single crystal semiconductor material, an interfacial region provided on the first bulk single crystal semiconductor material, and a second bulk single crystal semiconductor material provided on the interfacial region, the second bulk single crystal semiconductor material being dissimilar to the first bulk single crystal semiconductor material.

The interfacial region is able to provide an interface between the two dissimilar single crystal semiconductor materials which may, for example, enable electron passage between the two different single crystal I.'

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semiconductor materials, and which may allow efficient heat or other transfer between the two materials.

The provision of the device structure according to the present invention having two dissimilar semiconductor materials may allow a single device to perform a number of functions, each of which are associated with one of the two dissimilar single crystal semiconductor materials forming the device.

Alternatively or additionally, the device can enable the transfer of heat, electrons and other signals between the materials. The inventors consider that this cannot be achieved by merely placing two dissimilar single crystal semiconductor materials next to each other, for example by clamping or otherwise adhering these to each other. Where two dissimilar materials are joined directly, or are placed against each other, the interface between the two materials will prevent the efficient transfer of electrons, heat and the like between the two materials. If an adhesive was used to join two 1 5 semiconductor materials together, the adhesive itself would probably result in the scattering of any electrons that are transferred between the semiconductors, leading to a reduction in transmission and poor quality signal output. This is thought to be at least partly due to the different crystal lattice structure of the two materials. However, the provision of an interfacial region between the two dissimilar crystal materials may act as a transition and transfer region avoiding the disadvantages of a natural barrier between the materials The interfacial region may have other benefits in assisting or controlling flows between the dissimilar single crystal materials, for example other transition of matter in, among or between the two bulk single crystal semiconductor materials.

Many different semiconductor materials may be used as the two dissimilar sing'e crystal semiconductor materials in the device of the present invention The semiconductor materials may include silicon (Si), gallium arsenide (GaAs) cadmium telluride (CdTe), cadmium zinc telluride (CZT), zinc selenide (ZnSe), cadmium suiphide (CdS), lead iodide (Pb12), mercury iodide (Hg12), zinc telluride (ZnTe), gallium nitride (GaN), silicon carbide (SiC) and zinc sulphide (ZnS).

In a preferred example, the first bulk single crystal semiconductor material comprises silicon or gallium arsenide. An advantage of such materials is that these substrates have good mechanical strength and are commercially available at an acceptable price. Such materials are currently commercially available with a diameter greater than 50 mm, and indeed with a diameter of around 150 mm. This helps in maintaining integrity of the formed material during subsequent processing and transportation which may be more difficult with a less robust substrate. The second, dissimilar, semiconductor material advantageously comprises cadmium telluride, cadmium zinc telluride, zinc selenide (ZnSe), cadmium suiphide (CdS), lead iodide (Pb12), mercury iodide (Hgl2), zinc telluride (ZnTe), gallium nitride (GaN), silicon carbide (SiC) or zinc sulphide (ZnS).

In one example of the present invention, the interfacial region may comprise an interfacial layer comprising a thin-film. In a preferred example, the interfacial layer comprises one of the two dissimilar semiconductor materials of the semiconductor device It may be beneficial to provide an interfacial region comprising a plurality of thin-film interfacial layers. In this case, one or more of the interfacial layers may be of a material similar to one of the two dissimilar semiconductor materials of the semiconductor device Where the interfacial region comprises one or more interfacial layers, this thin-film may be formed directly onto one of the two materials of the semiconductor device using known thin-film deposition techniques.

The interfacial region may include one or more transition regions in which there is a gradual or stepwise transition of material type. The transition region can be formed with or without interfacial layers. In a preferred arrangement, there is a first transition region from the first bulk single crystal semiconductor material to an interfacial layer, with a second transition region provided between the inter-facial layer and the second bulk single crystal semiconductor material. In this case, the device will have the structure a: x12,3:b:yi,2,3:c where a is the first bulk single crystal semiconductor material, c is the second bulk single crystal semiconductor material and x1,2,3.b:y123 is the interfacial region, where b is an intermediate layer, x123 is the first transition region and y1,2,3 is the second transition region. The first transition region x1,2,3 may comprise one or more layers x1, x2, x3, and the second transition region y1,23 may comprise one or more layers y1, y2, y3 etc. The semiconductor device structure of the present invention may have many applications. In one example, one of the dissimilar semiconductor materials may be used for a detector or electronic circuit, and the other semiconductor materials may be used as the heat sink. In this case, the presence of the interfacial region between the two dissimilar materials helps ensure effective heat transfer between the two materials. In a further example, one of the dissimilar semiconductor materials may be a material suitable for the detection of photons, for example photons of x-rays or gamma rays. The other semiconductor material may include an electronic circuit, for example in the form of an ASIC, able to process the electrical signals generated by the absorption of photons in the other semiconductor material. In this case, the interfacial region acts to ensure the efficient transfer of the electrical signals from the detector material to the circuit material. This avoids problems associated with forming electrical connections between a detector and a processor, for example resulting from the failure of a wire solder bump I.

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connection, and also enabling a greater resolution for more accurate detection. A further possibility with the structure of the present invention is to provide two semiconductor materials that are able to detect photons of different energy, for example where the first bulk single crystal semiconductor material is silicon able to detect low energy photons and the second bulk single crystal semiconductor material is cadmium telluride able to detect high energy photons.

It is envisaged that other applications for semiconductor devices can be achieved using a device structure of the present invention which cannot be otherwise provided.

The device structure according to the present invention can be formed using a number of techniques. It is preferred that one of the dissimilar semiconductor materials is provided as a substrate, onto which the interfacial region is deposited, and onto which the second semiconductor material is subsequently formed.

It is preferred that the second semiconductor material is deposited on the interfacial region using a bulk vapour deposition technique. It is preferred that the second semiconductor single crystal material is grown using a multi-tube physical vapour phase transport method, such as that disclosed in ER-B-1019568.

Where the interfacial region comprises one or more thin film interfacial layers, these can be formed using standard thin film deposition techniques. These include molecular beam epitaxy, chemical vapour deposition, sputtering, metallo organic chemical vapour deposition (MOCVD), metal organic vapour phase epitaxy and liquid phase epitaxy. Whilst all of these methods are relatively slow for, since the interfacia! layer or layers are very thin, the growth rate of the layer is not of significant importance in the overall manufacturing process.

Alternatively, vapour phase deposition techniques can be used to grow the thin film interfacial layer or layers on the substrate. When vapour phase deposition techniques are conventionally used for bulk growth of crystal materials, the growth rate is typically between 100 and 500 microns/hour. In this case, it is necessary for the growth to provide an underlying layer of the same material as that to be deposited. However, when the conditions are adjusted to grow a thin film at a growth rate of between 0.1 and 10 microns/hour, the thin film can be grown on a substrate of dissimilar material.

After formation of thin film interfacial layer or layers by standard thin film deposition techniques or vapour phase deposition techniques, it is desirable that the substrate be treated, for example being cleaned and/or polished, prior to the formation of the second bulk single crystal semiconductor material on the interfacial region.

In an alternative embodiment, an interfacial region comprising one or more transition regions can be formed on the substrate. In this case, the or each transition region can be deposited using the same growth technique as used subsequently for deposition of the second semiconductor material, but with a variation in the growth parameters during the growth cycle to gradually accelerate the rate of growth as the second semiconductor material is grown.

In particular, when the material is initially deposited on the substrate, the growth rate will be slow, enabling the materials to be properly nucleated and formed. After depositing this initial material, the growth parameters can be changed to increase the rate of formation of the crystal material. There will be an initial region where the deposition changes from the slow, thin film type, to faster deposition of the second bulk single crystal semiconductor material.

This change may be a gradual change, or may be an abrupt change.

The parameters that should be changed may include at least one of the source temperature (Tsource) and the substrate temperature (Isub). A variation in the source and/or substrate temperature will result in a change of the temperature differential (iT). Typically, the minimum source temperature will be around 45000 to ensure the sublimation of the material. At temperatures lower than 450 C, no substantial sublimation will occur. The minimum substrate temperature is around 200 C. By increasing the temperature differential, for example by increasing the source temperature, the overall growth rate may be increased. It will be appreciated that the growth and sublimation temperatures are dependent on the material being deposited. For example, the growth temperature for mercury iodide is around 100 to 150 C and the sublimation temperature is around 200 to 300 C.

Alternatively or additionally, where one or more transition regions are provided, these may be formed as regions in which there is a gradual change from the material of the type of an underlying layer to a material of the type of an overlayer, or maybe formed as one or more discreet layers of different materials. This is especially useful where the dissimilar single crystal semiconductor materials have a different lattice structure.

To form one or more transition regions in which there is a gradual change in material type, it is preferred that the apparatus for depositing the material includes a means for introducing different source materials to be deposited onto the substrate In addition to the two dissimilar semiconductor materials and the interfacial region, additional layers may be deposited. It is possible to provide additional interfacial regions on one or other of the dissimilar semiconductor materials, and to provide additional single crystal semiconductor materials on the additional interfacial regions. Any desired number of single crystal semiconductor materials may be formed in this way. Further, a metal layer such as a layer of indium, platinum, gold or aluminium may be formed for electrical contact. Alternatively or additionally a dielectric layer may be provided. This is especially useful where the structure is to be used as a radiation detector as the dielectric layer may act as a filter to block visible and near infra red light.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will now be described by way of example with reference to the accompanying drawings, in which: Figure 1 shows a cross-section of a general example of a structure according to the present invention; Figure 2 shows an apparatus suitable for growing a semiconductor device according to the present invention; Figure 3 shows a cross-section of a particular structure according to the present invention; and, Figure 4 shows a cross-section of another structure according to the present invention.

DETAILED DESCRIPTION OF A PREFERRED EXAMPLE

The semiconductor device structure according to the present invention includes, in order, a first bulk single crystal semiconductor material 100, an interfacial region 200 and a second bulk single crystal semiconductor material 300 different from the first bulk single crystal semiconductor material 100.

In one preferred example, the first bulk single crystal semiconductor material is a substrate 10 that acts as a seed for the formation of the second bulk single crystal semiconductor material 200. The substrate 10 may be formed of a desired semiconductor material such as silicon or gallium arsenide. The substrate 10 will typically have a thickness greater than 100 microns, preferably of at least 200 microns for mechanical stability and can have any available size. Silicon substrates with a diameter of up to 300mm are currently available. Silicon and gallium arsenide are particularly suitable for formation of electronic circuits by appropriate doping.

The second bulk single crystal semiconductor material 300 used in the device structure of the present invention will be dissimilar from the first bulk single crystal semiconductor material 100. In particular, as well as being of a different material, the second bulk single crystal semiconductor material 300 will generally have a different lattice structure from the first bulk single crystal semiconductor material 100. Accordingly, it will generally not be possible to grow the second bulk single crystal semiconductor material 300 directly onto the first bulk single crystal semiconductor material 100, at least without sacrificing the required coupling between the semiconductor materials, for example in terms of electron transfer, stability and heat transfer. The formation of the interfacial region 200 on a substrate 10 of the first bulk single crystal semiconductor material 100 and onto which the second bulk single crystal semiconductor material 300 is formed enables an acceptable interface between the semiconductor materials for the particular use of the semiconductor device to be achieved. Furthermore, the interfacial region 200 may provide advantageous electrical or other coupling between the semiconductor materials 100, 300.

The interfacial region 200 formed on a substrate 10 of the first bulk single crysta' semiconductor material 100 may be formed of the same material as the second bulk single crystal semiconductor material 300, but formed in such a way that an acceptable interface is formed between the first single semiconductor material 100 and the overlying regions and layers.

Alternatively, the interfacial region 200 may comprise one or more discrete layers or transitional regions that gradually change the lattice structure between that of the underlying first bulk single crystal semiconductor material to the second bulk single crystal semiconductor material 300. The interfacial region 200 may be deposited on a substrate 10 of the first bulk single crystal semiconductor material 100 using a number of techniques, dependent upon the nature of the interfacial region 200 required.

An apparatus and method suitable for formation of the second bulk single crystal semiconductor material 300 on an interfacial region 200 will first be described, and then preferred examples of methods for forming the interfacial region 200 will be described.

A preferred apparatus for the formation of the second bulk single crystal semiconductor material 300 on the interfacial region 200 is shown in Figure 2.

The apparatus comprises an evacuated U-tube in the form of a quartz envelope 20 encased in a vacuum jacket 21. Two separate three zone vertical tubular furnaces are provided 22, 23 for the source 24 and the sink zone 25 respectively. The source and sink zones are connected by an optically heated horizontal cross member 27 forming a passage 26. A flow restrictor 28 -which may comprise a capillary or sintered quartz disk -is provided in the passage 26. The passage comprises two separate points of deviation, in each case at an angle of 90 , providing respective junctions between diverging passages for in-situ monitoring and vapour transport from the source to the sink zone. Windows allowing optical access to source and sink respectively are provided. The temperature of the surface of growing crystal in the sink zone can be monitored by a pyrometer or other optical

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diagnostic apparatus 33 located external to the vacuum jacket and in optical communication with the surface of the growing crystal. The diagnostic apparatus is in communication with a suitable control system to vary the sink zone temperature. The apparatus also comprises means for in-situ monitoring of vapour pressure by access ports 33 to 36 in the region of the flow restrictor 28, through which vapour pressure monitoring lamps and optics may be directed from a position external to the vacuum jacket with detectors located as shown at a location 35, 36 diametrically opposed with respect to the passage for vapour transport 26. These are suitably linked to a control system providing for process control The source tube, growth tube and cross member, in which transport takes place, are fabricated from quartz and the system is demountable with ground glass joints between the cross member and the two vertical tubes allowing removal of grown crystals and replenishment of source material Radiation shields (not shown for clarity) together with the vacuum jacket which surrounds the entire system provide thermal insulation.

A substrate 10 of the first bulk single crystal semiconductor material 100, which may or may not include the interface region 200 depending on the method by which the interface region 200 is formed onto which the second bulk single crystal semiconductor material 300 is to be deposited is located on a quartz block in the growth tube with the gap between this glass block and the quartz envelope forming a downstream flow restrictor. Provision is made for a gas inlet to the source tube and the growth tube may be pumped by a separate pumping system or by connection to the vacuum jacket via a cool dump tube.

Methods for forming the interfacial region 200 will now be described.

In one example of the present invention, an interfacial region 200 comprising a thin film of a crystal material is deposited on the upper surface of a substrate of the first bulk single crystal semiconductor material 100 by a conventional thin film deposition method. Suitable methods include molecular beam epitaxy, chemical vapour deposition, sputtering, metallo organic chemical vapour deposition (MOCVD), metal organic vapour phase epitaxy and liquid phase epitaxy methods. The thin film layer of the crystal material is deposited or grown on the substrate 10 of the first bulk single crystal semiconductor material 100 at a typical rate of between 0.1 and 10 micron per hour, although could be greater. However, only a very thin layer is required to be formed on the upper surface of the substrate 10, typically having a thickness of between about 1 and 10 microns, although could be greater. The film thickness should be at least 1 micron to ensure that the layer is fully relaxed. The maximum thickness of the layer is preferably 10 microns so that the layer can be formed within an acceptable time. In a preferred example, the thin film layer is of the same material as the material of the second bulk single crystal semiconductor material 300. According to an alternative example of the present invention, the interfacial region 200 may be formed as an interfacial thin film layer on the first bulk single crystal semiconductor material 100 by controlling the growth parameters, such as the concentration of the source, temperature differential etc are controlled to initially grow the crystal material on the substrate 10 of the first bulk single crystal semiconductor material 100 at a slower rate, for example in the range 1 to 10 microns/hour. As with the first example, after formation of the thin layer of crystal material on the substrate 10 of the first bulk single crystal semiconductor material 100, the substrate 10 is removed and treated, for example by being polished. The crystal with the thin film is then reintroduced to the apparatus for growth of the second bulk single crystal semiconductor material 300 as described above.

As shown Figure 3, the interfacial region 200 may be formed of two or more interfacial thin film layers 202, 204 of different materials. These thin film layers 202, 204 may be selected to best match the underlying first bulk single crystal semiconductor material 100 and the second bulk single crystal semiconductor material 300.

According to a preferred example of the present invention, the interfacial region 200 includes an interfacial layer and at least one transition region provided between an interfacial layer and at least one of the underlying and overlying single crystal material. The transition region or regions may be comprised of a plurality of discrete layers, or a gradual transition in characteristics of the material between the underlying and overlying layers.

In a particularly preferred example as shown in Figure 4, the overall structure of the device can be defined by the formula a: x123:b:y123:c where a is the first bulk single crystal semiconductor material 100, c is the second bulk single crystal semiconductor material 300 and x123:b:y1,23 is the interfacial region 200. In this case, b is the intermediate layer, x123 is a transition region between the first bulk single crystal semiconductor material 100 substrate 10 and the intermediate layer b comprising one or more layers x1, x2, x3 etc, and Y1,2,3 is a transition region between the intermediate layer b and the second bulk single crystal semiconductor material c comprising one or more layers y1, y2, y3etc There are a number of factors which determine whether a particular material can suitably be deposited on an existing layer, or whether problems will arise from the mismatch between the adjacent layers or regions. A mismatch may occur where there is a mismatch between parameters such as the lattice parameters, the thermal expansion coefficient and/or the coefficients of elasticity Ideally, the parameters for the material of adjacent layers or regions should be as close as possible to minimise mismatches. A layer may be of substantially the same material as an adjacent layer or bulk semiconductor material with doping and/or incidental impurities. Where there is a large difference in the lattice parameters for adjacent layers or regions, for example where the difference between lattice parameters is greater than 3%, misfit dislocations will occur as the subsequent layer is deposited. However, these misfit disclocat ions will in most cases grow out over the first few atomic layers -typically within 10 microns -so that the remainder of the material will be fully relaxed. However, this relaxation occurs only at the temperature of growth Where there is a difference between the thermal expansion coefficients of the adjacent layers, at temperatures other than the temperature of growth, there will be thermal strain. Such strain can be transmitted to other layers or regions in the structure, for example to the substrate or crystal material. Where the crystal material is sufficiently thick, the strain will generally be located in the substrate. For example, it has been found that when a CdTe layer, with a thickness of about 250 microns, is formed on a 350 micron gallium arsenide substrate at 500 C, there will be substantially no strain in the CdTe layer when the device is held at a temperature of around 700 C during subsequent crystal formation.

According to a preferred example of the present invention, the source is selected so as to initially deposit a first transition region 210 onto the substrate The first transition region 210 should have similar lattice parameters to that of the substrate 10 and an intermediate layer 12. The first transition region 210 will have a thickness of between about 10 and 200 microns. As discussed above, a thickness of 10 microns will be sufficient for misfit dislocations to grow out, and a thicker layer will help ensure that any strain will be primarily located in the substrate. The region may comprise a number of layers x1, x2 x3 etc of different materials or properties to complete the transition from the substrate 10 to the intermediate layer 12. For example, where the substrate is a silicon substrate, this will have a lattice parameter a=5.4309 A. In this case, and the first transition region may comprise an initial layer of GaP deposited on the substrate. GaP has a lattice parameter a=5.4506A. This lattice parameter is sufficiently close to that of the underlying silicon substrate 10 that any lattice mismatch is minimised. The source material supplied to the growth chamber may be altered so as to deposit a gallium arsenide intermediate layer. Gallium arsenide has a lattice parameter a=5.6533A. This is sufficiently close to the lattice parameter of the GaP layer as to minimise any lattice mismatch.

After forming the first transition region 210, the intermediate layer 12 is deposited. This layer will typically have a thickness of about 25 to 1000 microns, preferably in the region of 100 to 700 microns An intermediate layer 12 of this thickness will withstand any initial sublimation of the layer during the initial stages of bulk crystal growth of the second bulk single crystal semiconductor material. The material will have a structure similar to that of both the first and second bulk single crystal semiconductor materials 100, 300 In this case, the intermediate layer 12 may be CdS which has a lattice parametera=5.82A.

After depositing the intermediate layer 12, a second transition region 214 is formed The second transition region 214 will have a thickness of between about 10 and 200 microns, preferably up to about 500, to achieve lattice and thermal matching. The region may comprise a number of layers y1, Y2, y3 etc of different materials or properties to complete the transition from the intermediate layer 12 to the second bulk single crystal semiconductor material 300. In the particular example, the second transition layer 214 may comprise a single layer of CdSe having a lattice parameter a=6 05A.

After forming the second transition layer 214, the second bulk single crystal semiconductor material 300 can be deposited by changing the source material. One example of a second bulk single crystal semiconductor material 300 may be cadmium telluride which has a lattice parameter a6.481A.

Where the structure of the present invention is used as a detector of x-rays or the like, the second bulk single crystal semiconductor material 300 may be deposited to a thickness of about 700 microns. This thickness enables the material to ensure effective absorption of high energy radiation, It has been found that to absorb 90% of x-rays at 100 KeV, a thickness of 11mm of cadmium telluride is required.

Examples of possible first and second bulk single crystal semiconductor materials an intermediate layer are set out below.

Empie 1st Material Interfacial 2nd Material Overall Structure Layer + trace elements & dopants 1 Si CdTe CdTe Si: CdTe. CdTe 2 Si CZT CZT Si: CZT: CZT 3 Si CZT CdTe Si: CZT: CdTe 4 Si CdTe CZT Si: CdTe. CZT GaAs CdTe CdTe GaAs CdTe: CdTe 6 GaAs CZT CZT GaAs: CZT. CZT -i f CZT CdTe GaAs: CZT: CdTe 8 GaAs CdTe CZT GaAs: CdTe: CZT 9 -Ge CdTe CdTe Ge: CdTe: CdTe Ge CZT CZT Ge:CZT:CZT 11 -Ge CZT CdTe Ge: CZT: CdTe 12 Ge CdTe CZT Ge: CdTe: CZT 13 Silicon CdTe CdTe Silicon Carbide: CdTe Carbide: CdTe 14 Silicon CZT CZT Silicon Carbide: CZT: Carbide CZT Silicon CZT CdTe Silicon Carbide: CZT.

Carbide CdTe 16 Silicon CdTe CZT Silicon Carbide: CdTe Carbide: CZT 17 Si ZnTe ZnTe Si.ZnTe:ZnTe 18 GaAs ZnTe ZnTe GaAs:ZnTe:ZnTe 19 Si ZnTe ZnSe Si:ZnTe:ZnSe GaAs ZnTe ZnSe GaAs: ZnTe ZnSe 21 Si CdS CdS Si:CdS:CdS Th 22 GaAs CdS CdS GaAs: CdS: CdS 23 SiC CdS CdTe SiC: CdS: CdTe 24 SiC CdS CZT SiC: CdS: CZT Si GaN GaN Si:GaN:GaN GaN GaN _JGaAs:GaN:GaN As shown in Figure 5, a further metal layer 18 may be formed on the side of the second semiconductor material 300 opposite to the first semiconductor material 100. The resulting metal -semiconductor structure will result in high energy electrons being injected over or tunnelling through the layer. As also shown in Figure 5, electrical terminals or pads 16 can be formed on the side of the substrate 10 opposite that on which the interfacial region and second semiconductor material 300 is formed for electrical connection. The metal layers 18 and/or connections may be formed by conventional techniques such as printing, sputtering or lithography.

In one example, an electronic circuit can be formed in one or more of the single crystal semiconductor materials This can be formed by conventional semiconductor fabrication techniques, including ion implantation and doping techniques. Where electronic circuits are formed in a substrate of the first semiconductor material, these may be formed either before, during or after the formation of the interface region and/or the second semiconductor material.

A particular use of the structure of the present invention is as a detector, in which an electrical circuit is formed in the first bulk single crystal semiconductor material, and in which the second bulk single crystal semiconductor material is a material able to absorb photons and generate electrical signals in response. In this case, the electric circuit formed in the first semiconductor material will be designed so that electrical signals generated as a result of the absorption of photons in a crystal material can be suitably processed, for example to provide an indication of the number or energy level of the photons absorbed, or to provide other information relating to the detected photons. The circuit may include pre-amplification, filtering, shaping, thresholding and/or discriminating elements.

In use, when radiation is incident upon the second bulk single crystal semiconductor material 300, which generally has a thickness of at least 300 microns, and normally of at least 500 microns and most preferably at least 700 microns, the photons from the radiation will be absorbed by the dense crystal material. The absorbed photons are converted into electrical signals which pass through the interfacial region 200 to the underlying semiconductor material 100 where it is detected. The electrical signals are processed by the integrated circuit formed within the semiconductor substrate 10.

Claims

CLAIMS

1 A semiconductor device structure comprising a first bulk single crystal semiconductor material, an interfacial region provided on the first bulk single crystal semiconductor material, and a second bulk single crystal semiconductor material, the second bulk single crystal semiconductor material being dissimilar to the first bulk single crystal semiconductor material.

2. The semiconductor device structure according to Claim 1, in which the interfacial region provides an interface between the two dissimilar single crystal semiconductor materials which may enable electron passage between the two different single crystal semiconductor materials, and/or allow efficient heat or other transfer between the two materials.

3 The semiconductor device structure according to Claim 1 or Claim 2, in which the first and second bulk single crystal semiconductor materials comprise silicon (Si), gallium arsenide (GaAs) cadmium telluride (CdTe), cadmium zinc telluride (CZT), zinc selenide (ZnSe), cadmium sulphide (CdS), lead iodide (Pbl2), mercury iodide (Hg12), zinc telluride (ZnTe), gallium nitride (GaN), silicon carbide (SiC) or zinc sulphide (ZnS).

4 The semiconductor device structure according to Claim 3, in which the first bulk single crystal semiconductor material comprises silicon (Si) or gallium arsenide (GaAs), and in which the second semiconductor material comprises cadmium telluride (CdTe), cadmium zinc telluride (CZT), zinc selenide (ZnSe), cadmium sulphide (CdS), lead iodide (Pb12), mercury iodide (Hg 12), zinc telluride (ZnTe), gallium nitride (GaN), silicon carbide (SiC) or zinc sulphide (ZnS).

5. The semiconductor device structure according to any one of the preceding claim, in which the interfacial region comprises an interfacial thin-film layer.

6. The semiconductor device structure according to Claim 5, in which the interfacjal region comprises a plurality of interfacial thin-film layers.

7. The semiconductor device structure according to Claim 5 or Claim 6, in which the or at least one inter-facial layer comprises one of the two dissimilar semiconductor materials of the semiconductor device.

8. The semiconductor device structure according to any one of the preceding claims, in which the interfacial region includes one or more transition regions in which there is a gradual or stepwise transition of material.

9. The semiconductor device structure according to Claim 8, including a first transition region from the first bulk single crystal semiconductor material to an interfacial layer, with a second first transition region provided between the interfacial layer and the second bulk single crystal semiconductor material.

The semiconductor device structure according to Claim 9, in which the first transition region comprises one or more layers.

11 The semiconductor device structure according to Claim 9 or Claim 10, in which the second transition region comprises one or more layers.

12 The semiconductor device structure according to any one of the preceding claims, including additional interfacial regions and further single crystal semiconductor materials formed on the additional interfacial regions.

13. The semiconductor device structure according to any one of the preceding claims, further comprising one or more of a dielectric layer, a metal layer, a metallic layer or an intermetallic alloy layer 14. The semiconductor device structure according to claim 13, in which the dielectric, metal, metallic or intermetallic alloy layer has a desired geometric shape and is provided on at least one side or surface of one or both bulk single crystal semiconductor material.

The semiconductor device structure according to any one of the preceding claims, including a metal layer such as a layer of indium, platinum, gold or aluminium.

16. A CMOS, ASIC, FET, radiation detector, energy selective gating radiation detector or CCD device including a semiconductor device structure according to any one of the preceding claims.