GB2430510A

GB2430510A - Preventing the occurrence of unwanted bit patterns in scrambled data

Info

Publication number: GB2430510A
Application number: GB0519677A
Authority: GB
Inventors: David Lyon
Original assignee: Snell and Wilcox Ltd
Current assignee: Snell Advanced Media Ltd
Priority date: 2005-09-27
Filing date: 2005-09-27
Publication date: 2007-03-28
Anticipated expiration: 2025-09-27
Also published as: GB2430510B; GB0519677D0

Abstract

The apparatus provides for removal of undesirable data sequences for scrambled data prior to transmission to prevent the scrambled data being the same as timing reference signals. Data input is scrambled by a first scrambler 3 and simultaneously passed to data modifier 13 to be modified and then scrambled by a second scrambler 15. The output from the first scrambler is analysed by analysis module 9 to compare it to forbidden data patterns and the result of this analysis is used by control module 11 to select between the output from the first and second scramblers for transmission. The first scrambler output will normally be used for transmission except where the data output from the first scrambler equals a reserved word, such as synchronising pattern, when the output from the second scrambler will be selected for transmission.

Description

IMPROVED SCRAMBLING

FIELD OF INVENTION

This invention relates generally to the communication of digital video data over a transmission medium. The invention relates in particular to an improved scrambling technique for the transmission of digital video data.

BACKGROUND TO THE INVENTION

Digital interfaces between professional-user video equipments have been in use since the 1980s. The first such interface to be standardised used separate twisted pairs in parallel for eight data bits and a clock signal; however technological advances soon made a bit-serial interface possible.

This had the great advantage of requiring only a single coaxial cable for transmission and offered the possibility of transmission over optical fibre.

Today bit-serial interfaces for component digital television, both standard definition and high-definition, are widely used and their characteristics are defined in standards such as SMPTE 292M, SMPTE 259M and ITU-R BT.656.

In a single-wire, serial binary-digital interface some means of conveying the bit- and word-rate clocks is required, and, as in any cable transmission system, the effects of the increase in cable attenuation with increasing signal frequency must be mitigated. In the interfaces defined in the above standards the problem of bit-rate clock transmission is solved by "scrambling" the serial data so as ensure that the data sent over the cable contains sufficient clock- frequency energy for a very narrow bandwidth filter (in practice, usually, a phase-locked loop) in the interface receiver to recover a clock having a fixed phase relationship with the serially-transmitted bits. The scrambling process generally may involve inputting the serial data into a shift register which has exclusive-OR gates at defined points in the chain of registers. These gates are fed with data from other points in the register chain so that the serial data at the output of the register has extra data transitions (as compared to the input serial data) and therefore more energy at the bit-clock frequency.

This scrambling process has the additional benefit of reducing the lowfrequency content of the serial data, enabling AC coupling to be used and making the task of equalising the high-frequency loss of the cable easier by, effectively, reducing the bandwidth.

The recovery of the word-rate clock is achieved by including "timing reference signals" (TRS5) in the data. These are typically defined, fouror five-word-long data sequences which are forbidden to appear in the video data. These sequences can be uniquely recognised and used to identify the phase of the word-clock relative to the bit-clock. There are usually two TRSs on each television line: one at the start of the active video information (SAy); and, one at the end of active video (EAV). The TRSs are also used to convey line, field and picture rate synchronising information.

The choice of scrambling algorithm is a compromise between complexity and performance. The effectiveness of scrambling can be rated by the maximum run-length of scrambled, output bits of the same sense (either one or zero), and the frequency of occurrence of such runs. The algorithm used in the above mentioned standards uses a ten-bit-long shift-register with feedback (via exclusive-OR gates) over one, four and five stages. The longest run-length is 19 bit periods. For video data which is largely uncorrelated (at least in the low significance bits), such as that from cameras or telecines, the probability of this run occurring is very low. However, for electronically- generated images, such as the outputs of character or matte generators, fixed sequences of video data may be output for extended periods and this may cause the scrambler to output a repeating sequence of long-run-length data words. This is known as a "pathological" condition, in which the scrambled data contains an unusually-high low-frequency content.

The occurrence of the TRSs usually limits the duration of pathological outputs to a period of less than one television line. However, the pathological condition sets a limit to the distance over which a particular combination of interface implementation and cable type can be used. If the frequency spectrum of the received pathological data is such that the receiver cannot recover the data without bit errors it is likely that the interface will fail under some conditions.

SUMMARY OF THE INVENTION

The inventor has appreciated that there is a novel method of improving the performance of digital video interfaces by reducing the occurrence of pathological conditions.

In accordance with one aspect of the invention there is provided a method of reducing or avoiding the occurance of unwanted bit patterns in scrambled video data comprising the step of using video data modified prior to scrambling, in dependence upon the result of scrambling unmodified video data.

In accordance with a second aspect of the invention there is provided apparatus for scrambling video data to reduce or avoid the occurance of unwanted bit patterns in the scrambled data, comprising: modifying means for modifying the video data; scrambling means for scrambling the video data and for scrambling the modified video data; detection means for detecting unwanted bit patterns in the output of the scrambled video data; and control means enabling output of scrambled modified video data in dependence on detection of an unwanted bit pattern in the output of the scrambled video data.

In one form of the invention, the bit patterns of pairs of scrambled data words are analysed and data is modified prior to scrambling if no more than one bit of the pair is of opposite sense to the other bits of the pair.

In another form of the invention, unscrambled data is modified if all or part of a pathological scrambled data sequence is detected.

Suitably, data words are selected for modification in dependence upon their position relative to the video scanning raster.

Advantageously, one or more timing reference signal words are selected for modification.

In a further aspect of the invention, the modification comprises changing the state of either of the two least significant bits of a word.

In a yet further aspect, the modification can be corrected by the use of unmodified data bits in the said video data.

BRIEF DESCRIPTION OF THE DRAWINGS

Examples of the invention will be described with reference to the accompanying drawings in which: Figure 1 shows a video scrambler system in accordance with an embodiment of the invention.

Figure 2 shows a sequence of operations carried out by the system of Figure 1.

Figure 3 shows an alternative sequence of operations carried out by the system of Figure 1.

DETAILED DESCRIPTION OF THE INVENTION

Figure 1 shows an examplary embodiment of the invention in which parallel input data (1) is processed to create scrambled parallel data (20).

Typically the data (1) would be ten-bit component video data in accordance with one of the above mentioned standards. A sequence of luminance and colour difference component words describing a digital active line are transmitted between TRS words marking the start and end of the digital active line; and, optionally ancillary data (such as digital audio) is present outside the active line time.

An appropriate scrambling algorithm is implemented in the block (2).

This algorithm modifies each input data word (1) in dependence upon a previously-scrambled word (3). The resulting modified word passes via a multiplexer (5) to the input of a delay register (6), which delays the word (4) for one word-clock period to form the previously scrambled word (3). It can thus be seen that the output of the register (6) comprises a scrambled sequence of data words which can be unscrambled in a descrambler containing a one word delay and performing the inverse of the process (2).

The scrambled sequence of words (3) from the register (6) are input to a delay (7) and output via a multiplexer (8). Typically this output would be converted from parallel to serial format and transmitted over a coaxial cable or an optical fibre.

The invention seeks to avoid the occurrence of undesirable output words or sequences of output words in the scrambled data (20). Such undesirable words or sequences may include words having large numbers of adjacent bits of the same sense or the pathological data sequences mentioned previously.

A data analysis block (9) examines the scrambler output word (4) and the preceding scrambler output word (3). When undesirable words or sequences are found, a warning signal (10) is output by the block (9). This warning signal indicates the existence of an unwanted data condition and may also give information about the nature of the unwanted condition.

The warning signal (10) is input to a correction control block (II) which controls a process in which the data is modified so as to avoid the unwanted A timing signal (12) identifies a point or points on the television line at which it is acceptable to modify a word for this purpose. Typically this will be outside the digital active line and ancillary data times. The time of the SAV TRS word is particularly suitable, as will be explained later. The timing signal (12) can be derived from the input data (1) by identifying synchronising information in the data, such as TRS words or synchronising pulses, and marking the timing of words having a defined position relative to the scanning raster.

A data modifier (13) receives a parallel feed of the input data (1) and modifies the word or words identified by the timing signal (12), typically by changing the sense of the least-significant bit. The modified data (14) is passed to a second scrambler (15) which, with an associated delay register (16), scrambles the modified data (14) with exactly the same algorithm as used in the scrambler (2). The resulting scrambled, modified data (17) is routed by the multiplexer (18) to the delay register (16) and thence via a delay (19) to the multiplexer (8).

If the correction control block (11) receives a warning signal (10) during a defined time interval after the timing signal (12), it sends a control signal to the multiplexer (8) which switches the signal from the delay (19) to the output (20), in place of the signal from the delay (7). The delays (7) and (19) are of equal length, but are no shorter than the defined time interval during which the block (11) monitors the warning signal (10). Therefore, the two inputs to the multiplexer (8) will be identical at the time the control signal from the controller (11) is received; at this time the delay (19) will be outputting data from the scrambler (15) which predates the modification introduced by the block (13).

After a time equal to that of the delays (7) and (19), the output data (20) will include the effect of the modification introduced by the block (13). This scrambled data will be different from the undesirable data detected at the output of the scrambler (2).

It is desirable to return the multiplexer to its former condition, in which the scrambler (2) provides the output (20). As soon as the scrambled version of the modified data word is output from the scrambler (15) the control block (11) causes the multiplexer (5) to input this scrambled word to the delay register (6) associated with the scrambler (2). This ensures that, up until the next time signal (12), the subsequent output from the scrambler (2) is identical to that from the scrambler (15). Once this identical output reaches the output of the delay (7), the control block (11) switches the output (20) back to the data from the scrambler (2), received via the delay (7).

This process repeats at the next time point defined by the signal (12). If no warning signal (10) is received in the defined interval following this time point, it is necessary to return the scrambler (15) to synchronism with the scrambler (2); i.e. to remove the effect of the data modification introduced by the block (13). This is achieved by the multiplexer (18) which inputs the output from the scrambler (2) to the delay register (16), in response to a signal from the control block (11).

The time sequence of these processes is illustrated in Figures 2 and 3.

Figure 2 shows the sequence of events which occurs when undesirable data is detected in the defined interval; and, Figure 3 shows what happens if no undesirable data is detected. In these Figures the defined interval during which the data is monitored for undesirable words is ten wordclock periods long, and the delays at the scrambler outputs are also ten clocks. The reference numerals in the text in these Figures refer to Figure 1.

It is beneficial to make the defined time interval as long as possible so that as much data as possible can be corrected. However, as the delays (7) and (19) of Figure 1 have to be at least as long as this interval, the propagation delay of the process is also increased; and this is generally undesirable. There is also a limit as to how close to the next time signal (12), at which a data word is modified, the defined interval can end. The two scramblers must be synchronised and the two delay outputs must be equal before this time. Figure 3 show that this time between the end of the defined interval and the next time signal (12) must be at least the length of the delays (7) and (19).

It is generally unacceptable to modify video or ancillary data, though in some situations it may be more acceptable to introduce an error in a least- significant bit than to have a link failure due to a pathological condition. The only points on the line where video or ancillary data can be guaranteed to be absent are the timing reference signals. The content of the TRS words is precisely defined in the interface standards. The TRS words containing field- phase, vertical and horizontal timing information (F, V and H) have the two LSBs defined as zero, and the FVH information is protected by a Hamming error correction code, which can correct single-bit errors. It is therefore possible to change any one of: the two LSBs, the FVH bits or the Hamming bits, without affecting the ability of an interface receiver to decode the video information without error. The only disadvantage is that an interface receiver may register the data modification as an error and cause the operator to seek to repair a non-existent fault. This problem could be circumvented for new equipment if the use of one of these methods is permitted in the relevant standards.

By definition the SAV TRS immediately precedes the active line and so if it is chosen for modification, the portion of the active line which is protected against unwanted words is maximised for a given processing delay.

In component (as opposed to composite) interfaces the data outside the digital active line may undefined, unless used for ancillary data. This data may therefore be modified with less risk of introducing compatibility problems.

As ancillary data is identified by a special preamble, it would be possible to identify a non-ancillary data word immediately prior to the SAV TRS and modify it to avoid unwanted bit patterns.

The invention has been described by way of example and variations will be apparent to the person of ordinary skill from the above description. For

example:

- the processing could be done in the serial domain; - more or less than one timing signal (12) per line may be used; - the content of the input data may influence the timing of the signal (12), i.e. it may depend on the video format or the presence or type of ancillary data present; and, the nature of the unwanted scrambled data may be used to decide what type of data modification is acceptable, and where on the line the modification is made.

Claims

Claims 1. A method of reducing or avoiding the occurance of unwanted bit

patterns in scrambled video data comprising the step of using video data modified prior to scrambling, in dependence upon the result of scrambling unmodified video data.
2. The method according to claim I comprising the step of analysing the bit patterns of one or more scrambled data words, wherein video data modified prior to scrambling is used if an unwanted bit pattern is detected.
3. The method according to claim 2 further comprising the step of selecting between scrambled unmodified video data and scrambled modified video data in dependence on the step of analysing.
4. The method according to claim 2 or 3 wherein an unwanted bit pattern is detected if no more than one bit of a pair of scrambled data words is of opposite sense to the other bits of the pair of scrambled data words.
5. The method according to claim 2, 3 or 4 in which an unwanted bit pattern is detected if all or part of a pathological scrambled data sequence is detected.
6. The method according to any preceding claim also comprising the step of selecting data words for modification in dependence upon their position relative to the video scanning raster.
7. The method according to any preceding claim where one or more timing reference signal words are selected for modification.
8. The method according to any preceding claim in which the modification comprises changing the state of either of the two least significant bits of a
9. The method according to any preceding claim in which the modification can be corrected by the use of unmodified data bits in the said video data.
IO.Apparatus for scrambling video data to reduce or avoid the occurance of unwanted bit patterns in the scrambled data, comprising: modifying means for modifying the video data; scrambling means for scrambling the video data and for scrambling the modified video data; detection means for detecting unwanted bit patterns in the output of the scrambled video data; and control means enabling output of scrambled modified video data in dependence on detection of an unwanted bit pattern in the output of the scrambled video data.
11.The apparatus according to Claim 10 in which the detection means determines whether more than one bit of one or more adjacent scrambled words is of opposite sense to the other bits of the one or more words.
12.The apparatus according to Claims 10 or 11 in which the detection means detects part of a pathological scrambled data sequence.
13.The apparatus according to any of Claims 10 to 12 in which words are selected for modification in dependence upon their position relative the video scanning raster.
14. The apparatus according to any of Claims 10 to 13 in which one or more timing reference signal words are modified.
15.The apparatus according to any of Claims 10 to 14 in which the data modification comprises changing the state of either of the two least significant bits of an unscrambled word.
16.The apparatus according to any of Claims 10 to 15 in which the modification can be corrected by the use of unmodified data in the unscrambled data.
17.Apparatus for scrambling data to reduce or avoid the occurance of unwanted bit patterns in the scrambled data, comprising: a data modifier for selectively modifying input data; a first scrambling path for scrambling input data and a second, parallel scrambling path for scrambling modified input data from said data modifier; a detector for detecting unwanted bit patterns in the output of the first scrambling path; and an output selector for selecting between the output of said first and second scrambling paths in dependence upon detection of unwanted bit patterns.
18.Apparatus according to Claim 17, wherein said data modifier modifies said input data periodically.
19.Apparatus according to Claim 17 or Claim 18, wherein said data modifier modifies said input data independently of said detection of unwanted bit patterns.
20.Apparatus according to any one of Claims 17 to 19, wherein said data IS video data, and said data modifier modifies said input data in dependence upon its position relative to the video scanning raster.
21.Apparatus according to any one of Claims 17 to 20, wherein said ouput selector switches from said first to said second scrambling path on detection of unwanted bit patterns in said first scrambling path.
22.Apparatus according to any one of Claims 17 to 21, wherein said output selector acts to synchronise outputs from said first and second scrambling paths within each predetermined interval.
23.Apparatus according to Claim 22, wherein said scrambling paths include a delay greater than or equal to said predetermined interval.
24.Apparatus according to any one of Claims 17 to 22, wherein said output selector acts to synchronise outputs from said first and second scrambling paths after detection of an unwanted bit pattern.