GB2416255A - CMOS current mode logic circuits using subthreshold conduction for low power operation - Google Patents

Abstract

The switching transistors in a low-power CMOS current-mode logic circuit are biased to operate in weak inversion. The current-switching structure reduces noise and sensitivity to the process, voltage and temperature (PVT) variations which affect conventional subthreshold CMOS logic circuits. In retinal or cochlear implants analogue circuits operate in weak inversion to achieve low power, and by using current-mode logic satisfactory mixed analogue and digital low-power integrated circuits can be implemented. The logic swing is low and the data rate can be high. The current source Q1 operates in saturated weak inversion. The symmetry of the current-steering branches reduces input pattern sensitivity. A full adder is illustrated.

Description

24 1 6255 Current Mode Logic Diaital Circuits

Field of the Invention

The present invention relates to current mode logic digital circuits and in particular, though not necessarily, to CMOS current mode logic digital circuits.

Backaround to the Invention

Today, almost all digital circuits are constructed using complimentary metal oxide semiconductor (CMOS) field effect transistor (FET) technology. Figure 1 illustrates schematically a CMOS inverter. A fundamental principle underlying the use of CMOS is that no current flows through the CMOS transistors when a given circuit is in the quiescent state. Current only flows during switching of the circuit. Power consumption in CMOS circuits is therefore extremely low. In practice, even in the quiescent state, leakage currents will flow through the transistors. These leakage currents are relatively small for large scale devices.

For example, for transistors using micron level CMOS technologies, the leakage current through a transistor in the quiescent state will be of the order of picoamps.

The operating frequency of a CMOS circuit is determined to a large extent by the gate capacitance of a transistor. To enable a circuit to operate at very high frequencies, the gate capacitance, and hence gate size, must be made as small as possible. This means that the channel length must be as short as possible.

Current fabrication methods allow channel lengths to be deep in the submicron range At sub-micron channel lengths, the switching voltage which can be applied to the MOSFET gate must be reduced in order to avoid damaging the device.

Typically, for 0.13 to 0.18 Am technologies, the switching voltage must be of the order of 1.8V or less. The switching voltage therefore starts to approach the conventional MOSFET threshold voltage. Device designs are therefore modified to reduce the threshold voltage. This however results in the need for a large negative gate-source voltage in order to completely switch off the device, hence a higher sub-threshold leakage current exists when an off voltage of close to zero volts is used. CMOS circuits therefore start to become power hungry, and in addition begin to suffer from reduced switching noise immunity and supply voltage fluctuation related problems.

An alternative to CMOS technology Is that known as current mode logic (CML).

(When implemented using bipolar transistors as opposed to MOSFETs, CML is sometimes known as emitter couple logic (ECL).) CML is based upon the differential pair illustrated schematically in Figure 2 and draws a substantially constant current from the power supply. By applying a suitable voltage swing on the differential input, the constant current can be steered from one branch of the circuit to the other. The impact of leakage currents is of minor importance in CML, since these currents are a part of the constant current source supply.

Due to this constant current flow from supply to ground, the switching noise is reduced and since the operation of CML is based on the differential pair, problems due to supply voltage fluctuations are reduced as well.

CML is preferred for mixed analogue-digital signal environments in order to reduce the digital interference between the analogue and the digital blocks.

The constant current source used in CML is the reason for constant static power consumption, which is independent from the frequency of operation or gate activity. Adaptive pipelining techniques can be applied to sense the required speed of operation and reduce the power dissipation of the CML.

However, in applications where low-power, low frequencies are required, CML has not been preferred due to its constant static power consumption.

In medical applications such as vision chips implants, hearing chips implants etc., processing may be performed with CMOS based analogue techniques, where the MOSFET transistors are operated in the weak inversion region. In the weak inversion region the circuits can operate only up to some kHz, (not more than 1 MHz) whilst the power consumption can be very low, e.g. some Nano- Watts. Any digital processing which is required in these micropower regimes is implemented using Sub-threshold Static CMOS. Sub-threshold Static CMOS however is very sensitive to process, temperature variation, power supply variations (robustness problems), and modifications of the simple static CMOS logic have had to be developed to overcome these problems. In the Variable Threshold Sub-Threshold CMOS technique, the leakage current is monitored by control circuits and an appropriate bias is applied to the substrate of the transistors to prevent any change in current due to temperature, process, power supply and other variations. However leakage currents are not eliminated and extra circuitry is needed for robustness. Some other circuits use the Pseudo- NMOS subthreshold logic, which is another modification of sub-threshold Static CMOS in order to operate the circuits in ultra-low power whilst achieving some improvement in operating speed. However the robustness problems are very comparable to normal subthreshold CMOS logic.

Summary of the Invention

It is an object of the present invention to reduce the power consumption of current mode logic circuits to facilitate their use in low power applications.

According to a first aspect of the present invention there is provided a digital circuit comprising a pair of metal oxide semiconductor field effect transistors configured in a current mode logic configuration, and biasing means for biasing the transistors to operate in their weak inversion regions.

In the case of deep sub-micron devices, the leakage currents of the MOSFETs can provide all or a substantial part of the switching currents of the current mode logic (CML) configuration. Total power consumption may be reduced as compared with CMOS based circuits which, in addition to power consumption associated with the leakage currents, consume power as a result of the charging and discharging of transistor output capacitances during switching.

Embodiments of the invention are particularly suited to applications with high gate switching activity, and suffer from relatively low noise as a result of the inherent properties of CIVIL.

In certain embodiments of the invention, the channel lengths of the metal oxide semiconductor field effect transistors are less than 0.15 microns, and more preferably less than 0.13 microns.

The pair of metal oxide semiconductor field effect transistors are arranged as a differential pair, in series with a current source. Preferably, the current source is provided by a metal oxide semiconductor field effect transistors biased in the weak inversion and saturation regions. More preferably, this metal oxide semiconductor field effect transistors forms part of a current mirror.

Preferably, the digital circuit comprises load resistances coupled between each metal oxide semiconductor field effect transistor and the supply voltage, each load resistance being provided by a metal oxide semiconductor field effect transistor biased in the weak inversion region.

An integrated circuit comprising a plurality of digital circuits according to the above first aspect of the present invention.

According to a second aspect of the present invention there is provided a method of computing a logical function, the method comprising biasing a pair of metal oxide semiconductor field effect transistors, configured in a current mode logic configuration, to operate in the weak inversion region, and applying an input signal to the gates of the metal oxide semiconductor field effect transistors.

Brief Description of the Drawings

Figure 1 illustrates schematically a CMOS inverter; Figure 2 illustrates schematically a differential pair as used in an ECL circuit, Figure 3 illustrates the drain current versus gate-source voltage characteristics for a MOSFET; Figure 4 illustrates schematically an XOR3 circuit of a CML full adder; and Figure 5 illustrates schematically a carry circuit of a CML full adder.

Detailed Descriction of Certain Embodiments of the Invention In order to fully understand the embodiments of the invention to be described here, an understanding of the weak inversion mode of operation of MOSFET devices is required. In weak inversion, the transistor is characterized by the exponential behaviour of the weak inversion current Iweak with respect to the gate-source voltage ( V;s) and this behaviour is modelled by: IWeak = L IM exp (;S)LLI-CXP:- VDsJ] (1) for V(JS < VM VGS IS the gate-source voltage of the transistor and VM IS the value of Vcs for which "moderate" inversion begins. This can be seen in the MOSFET current vs voltage plots of Figure 3, where for V;s > VM the exponential relationship between V,js and /W6'ak ends. For a drain-source voltage (Vats) more than a few ,, (,=-25mV at room temperature) the transistor is q operating in saturation region. W/L is the width to length ratio of the transistor, and IM and n are process dependent factors (where n is usually between 1-2).

The speed of operation of the circuits depends on the transconductance of the transistors: g = Skiwear (2) dVc;,.

Using equations (1) and (2), the transconductance in weak inversion is: g Iweak (3) n, which is fixed as soon as Iweak is fixed, either in saturation or non-saturation.

This is a result of the exponential dependency Of Iweak on V;s. Also gm = I (4) ID n, The delay time of COIL circuits is given by, DCML I (5) weak where C is the Load Capacitance, AVis the signal voltage swing and weak is the constant current source current given by equation (1). The power dissipation is given by, PCM/ = V(/WeakN (6) where N is the number of CML blocks used for the CML circuit. The Energy Delay product can then be obtained: EDMos = N (7) weak The energy delay product can be reduced by reducing AV or/and 1 0 increasing /weak To illustrate the present invention, the example of a full adder implemented using CMOS CML in weak inversion mode will now be considered. The building blocks of a CML full adder are the XOR3 and a Carry circuit shown in Figures 4 and 5 respectively.

Region of Weak Inversion: The region of weak inversion for a given process is determined during process characterization measurements. Once a process has been characterized and accurate simulation models are available, the region of weak inversion can be found from simulations, and it is the linear part on the log-plot of thefts V;,. characteristic of the transistor (as highlighted in the upper plot of Figure 3). In the case of UMC (United Microelectronics Corporation) 0.18um technology, for equation (1) to hold, V;s ' VM _ 300m V. Suitable Voltage Swing: The input voltage swing ( AN) has to be sizable enough to avoid influence from thermal noise and device mismatch (> lOOmV). If the speed performance has to be pushed to the limits of the speed of weak inversion circuits, AV has to be as small as possible as explained above. Thus in the examples demonstrated here, AN = lOOmV was used. In circuits where a balance between speed and power is required, other larger values of AT can be used accordingly.

Load Impedance: The bias current generated by Q1 is 'steered' through a given branch to the PMOS transistor load depending on the input voltages at A, B and C. The magnitude of the output voltage swing AV should remain constant regardless of which steering branch is selected; thus the impedance of each steering branch should appear the same to the PMOS loads Q12 and Q13. This is why transistors Q10 and Q11 are present in Figure 4. (See "A GHz MOS Adaptive Pipeline Technique Using MOS Current- Mode Logic"; Masayuki Mizuno, Masakazu Yamashina, Koichiro Furuta, Hiroyuki Igura, Hitoshi Abiko, Kazuhiro Okabe, Atsuki Ono and Hachiro Yamada) Minimum SuPpiv Voltage: The supply VoltageV,, has to be chosen such that the current source of the CML circuit is working in saturation so that the current through it can be mainly determined by Vcsource. Thus, to ensure saturation, the current source drain-source voltage (its a) should be a few ,, typically 65mVOr above. Thus (with reference to Figure 2) V,, = max(V,,s sa' + VM, D ADS Sal + AV) (8) where D is the depth (i.e. the number of vertically stacked transistors) of the CML circuits, below the PMOS load. The inputs at the gates of the transistors should be the same, to ensure that they are all biased in their weak inversion regions: V,n = Vies sa' + VM Current Source Biasing: The biasing of the gates of the current sources in Figures 4 and 5 is obtained by mirroring a current reference source through the current source of the CML circuits (transistors Q1 and Q14). This current should be such that the voltage at the gate of Q1 is less than VM. In the case where the voltage at the gate of Q1 is equal to VM' the V;s Of the switching transistors Q2 to Q11 would be smaller than Vcsource, and due to the exponential dependency of current to Vcs, the V,, ,. of the switching transistors should be greatly increased (exponentially) to maintain the same amount of current through the current source. Alternatively, the areas of the transistor should be increased (exponentially). Thus a maximum current of 16.7nA ( Vcy'urce 260mV) can be used in the examples of Figures 4 and 5 for the current source to be biased in saturation. Increasing the current reference source to 32nA to bias the current source at VC5UUrCe=VM 300mV would still allow the circuits to work properly, but the current source would not be in saturation. This however is not a major problem in the weak inversion region, since the influence of v/ys on the current is not as strong as in strong inversion, but rather to is much less due to the negative exponential dependence of Vnson weak as shown in equation (1).

In strong inversion the transistor is characterized by a square law behaviour with respect to V,s and this behaviour is modelled by equations (10) and (11) for IS the non-saturation and saturation regions respectively.

Ill = K[(VGS - V7)V/)S - 2 vest] (10) ID = 2 (his - VT) ( 1 1) for, V,js > V,1,where VH IS the gate-source voltage for which moderate inversion ends and strong inversion begins, as can be seen in Figure 5. VT IS defined as the threshold voltage of a transistor, and is the linearly extrapolated value of V;s as shown in figure 5 (lower graph). K, a, and k are transistors parameters, and process factors.

In non-saturation, gm = KV,,s ( 12) gm = ADS I (13) (V<;S VT)V/)S --[XV,,S2 VGS V! In saturation, gin = k(VGS -V/. ) = I; V, s VT ( 1 4) In (Kis -v' (15) It is clear that in strong inversion the transconductance gm is higher than the transconductance in weak inversion, which explains why the speed of operation of circuits working in weak inversion is much less than that of the circuits working in strong inversion. The power dissipation of circuits in weak inversion is much lower since they work at much lower supply voltages and at much smaller current quantities. However the value of gm is higher in weak inversion and this is due to the exponential behaviour of the transistor in weak inversion.

Thus it can be expected that by using more weak inversion mode circuits in parallel in order to operate at the same frequencies as a circuit in strong inversion, less power would be consumed. Chip area is obviously an issue here.

In medical applications such as retina or cochlea implants, circuits are operating in the weak inversion region for ultra-low power consumption. Analogue signal processing circuits can operate very well in these cases. In contrast, conventional digital circuits operating in this region are very sensitive to process, temperature, power supply and other variations. Furthermore, leakage currents are noticeably increased. In order to support mixed analogue and reprogrammable digital signal processing in weak inversion, CMOS Current Mode Logic (CML) in weak inversion can be used.

It Will be appreciated by the person of skill in the art that various modifications may be made to the above described embodiment without departing from the scope of the present invention.

Claims (9)

1. CLAIMS: 1. A digital circuit comprising a pair of metal oxide

   semiconductor field effect transistors configured in a current mode logic configuration, and biasing means for biasing the transistors to operate in their weak inversion regions.
2. 2. A circuit according to claim 1, the pair of metal oxide semiconductor field effect transistors being arranged as a differential pair, in series with a current source.
3. 3. A circuit according to claim 2, the current source being provided by a metal oxide semiconductor field effect transistors biased in the weak inversion and saturation regions.
4. 4. A circuit according to claim 3, the metal oxide semiconductor field effect transistors of the current source forming part of a current mirror.
5. 5. A circuit according to any one of the preceding claims, the digital circuit comprising load resistances coupled between each metal oxide semiconductor field effect transistor and the supply voltage, each load resistance being provided by a metal oxide semiconductor field effect transistor biased in the weak inversion region.
6. 6 A circuit according to any one of the preceding claims, the channel lengths of the metal oxide semiconductor field effect transistors being less than 0.15 microns.
7. 7. A circuit according to claim 6, the channel lengths of the metal oxide semiconductor field effect transistors being less than 0.13 microns.
8. 8. An integrated circuit comprising a plurality of digital circuits according to any one of the preceding claims.
9. 9. A method of computing a logical function, the method comprising biasing a pair of metal oxide semiconductor field effect transistors, configured in a current mode logic configuration, to operate in the weak inversion region, and applying an input signal to the gates of the metal oxide semiconductor field effect transistors.