GB2415271A

GB2415271A - Computing device with watchdog timer

Info

Publication number: GB2415271A
Application number: GB0413455A
Authority: GB
Inventors: John Peasegood
Original assignee: Sendo International Ltd
Current assignee: Sendo International Ltd
Priority date: 2004-06-16
Filing date: 2004-06-16
Publication date: 2005-12-21
Also published as: GB0413455D0

Abstract

A computing device comprising a timer for generating a counter value; and a processor arranged to operate in a first operation mode that allows the timer counter value to be periodically reset; wherein upon the processor operating in a second operational mode in which the timer counter value is not periodically reset the timer is arranged to provide an interrupt signal to the processor upon the counter value reaching a predetermined value to allow the processor to stop operating in the second operational mode.

Description

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COMPUTING DEVICE

Field of the Invention

This invention relates to a computing device.

Background of the Invention

Hardware watchdogs are used in computing devices to prevent 0 processing loops from continuing for longer than a predetermined time period. This allows a hardware watchdog to detect a processor software 'lock up' condition (i.e. a condition the processor is in when the processor is in an operation mode that prevents the processor servicing activities other than the one that is causing the continuous processing loop).

A hardware watchdog typically includes a timer function that in a normal operational mode is reset by a reoccurring activity, for example an idle thread. However, if the processor is placed in an operation mode that prevents the processor from servicing other activities (for example, a continuous processing loop) the hardware watchdog timer will not be reset, thereby causing the timer to expire.

If the hardware watchdog timer expires the hardware watchdog initiates a hardware reset of the processor, for example by the hardware watchdog driving a dedicated reset signal to the processor to its reset condition, thereby preventing the continuous processing loop from continuing.

However, although the provision of a hardware watchdog prevents continuous processing loops from continuing the ea.e ate e.. a - - 2 hardware watchdog is unable to determine the cause of a continuous processing loop or other information associated with how the continuous processing loop developed.

It is desirable to improve this situation.

Statement of Invention

In accordance with a first aspect of the present invention, 0 there is provided a computer device according to claim 1.

This provides the advantage of allowing a processor to perform processing tasks to assist in analysing data associated with a processor lock up condition prior to a processor being reinitialized following a software lock-up condition.

Brief Description of the Drawings

Exemplary embodiments of the present invention will now be described, with reference to the accompanying drawings, in which: Figure l shows a computer device according to an embodiment of the present invention; Figure 2 illustrates a flow diagram of activities for a computing device according to an embodiment of the present invention.

Description of Preferred Embodiments . .

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For illustration purposes figure 1 shows a functional block diagram of a computer device 100.

The computer device 100 has a hardware timer 101 and a processor 102. The processor 102 is arranged to execute application software 103 and an operating system 104, where the operating system 104 incorporates a plurality of system operations, for example system initialization 105, null or idle thread 106, and scheduled kernel activities 107, as is 0 well known to a person skilled in the art. Additionally, the operating system includes software code 108 for assisting in the analysis of the cause of a continuous processor loop, as described below.

The computer device 100 will typically be part of an embedded circuit within a known device, for example a radiotelephone or a personal digital assistant, and will include standard features, for example a display (not shown) and keyboard (not shown), as is well known to a person skilled in the art. However, as these features are not essential to the present invention they will not be described within this description in any further detail.

The hardware timer 101 is arranged to be initialised by the system initialization 105 routine running as part of the operating system 104. The initialization of the hardware timer 101 will typically include setting of an initial counter value to which the timer counter will be reset, the setting of a timer expiry counter value and the resetting of the timer counter to the initial count value.

The values selected for the initial counter value and the timer expiry counter value are chosen to provide a . . ' 2: : . . . , . . - 4 predetermined time expiry period based upon whether the selected timer is a count up or count down timer and the rate of the hardware timer counter.

Typically the timer expiry period will be in the region of a few seconds up to several minutes, however values outside this range may also be required. The timer expiry period is determined by the expected behaviour characteristics of the software being executed on the device.

When the timer counter value reaches the timer expiry counter value the hardware timer lOl is said to have expired.

The timer count value is arranged to be reset using a control signal from a reoccurring event, for example a null/idle thread code or a scheduled activity running in the operating system 104, where the schedule period of the activity is less than the timer expiry period. Examples of schedule activities include a battery monitoring driver, screen update, inter-processor communications, however any scheduled activity that is designed to occur periodically at a period less than that of the chosen watchdog timer period and is executed with a priority that is higher than user application software can be utilised.

The process of resetting the timer count value using a control signal is commonly known as a 'tickle' operation.

so If the hardware timer lOl expires (i.e. the timer counter value reaches the timer expiry counter value) the hardware timer lOl is arrange to provide a high priority interrupt to the processor 102, where the priority level chosen is : .'. . ., ideally higher than that assigned to any other application to be executed by the processor 102.

As the timer is a separate component to the processor the high priority interrupt is in the form of a hardware signal, which even in a software lock-up condition causes the processor to stop following its current execution path and restart execution from a pre-defined address (the interrupt vector).

During normal operational mode of the processor the processor 102 will either enter an idle/null mode or execute an application software programme 103 loaded in memory (not shown) on the computer device 100, for example a word processing application or a video play back application. During the normal operational mode the operating system 104 will operate in the back ground to support the control of the computing device 100.

Additionally, when the processor is in the normal operational mode the system null/idle thread 106 or a scheduled activity 107 will be arranged to periodically tickle' the hardware timer 101 before the timer counter has reached the expiry counter value, thereby resetting the hardware timer 101 and preventing the timer expiring.

However, if the processor 102 enters an operational mode in which a continuous processing loop (i.e. a software lock up) occurs that prevents the processor 102 from servicing other activities because the continuous processing loop is consuming all of the processor 102 time this will prevent the null/idle thread 106 or a scheduled activity 107 from tickling' the hardware timer 101 and consequently will result in the timer expiring.

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If a software lock up occurs, resulting in the timer expiring, the hardware timer 101 will provide a high priority interrupt to the processor 102 upon the expiry of the hardware timer 101.

As the high priority interrupt originates from a hardware signal from the timer and will have a higher priority than that assigned to the application in which software lock up has occurred the processor 102 will stop the execution of the continuous processing loop and service the timer interrupt request.

On receipt of the high priority interrupt request from the hardware timer 101 the processor 102 stops the execution of the application in which a continuous processing loop has occurred and commences, via the interrupt vector associated with the high priority interrupt, execution of the operating system software code 108 that is arranged to assist in the diagnostic of the cause of the software lock up, for example saving and/or outputting system context and state information, finishing with the re-initialisation of the processor to place it back into the normal operation mode to allow execution of application programmer stored on the computing device (e.g. shut down the 'locked-up' application and then return control to the operating system), thereby avoiding a hardware reset of the processor 102.

However, the operating system software code 108 could be arranged to just perform a software re-initialisation of the processor.

1 eee e e e e e e e e e e I - 7 The above embodiment describes the use of a hardware timer 101 that in conjunction with an interrupt signal to a processor 102 can be used to perform a software watchdog function, thereby avoiding the need for a hardware reset of a processor 102 when in a software lock-up condition and additionally being able to provide additional information on how the software lock-up occurred.

By way of illustration, the operation of the software watchdog will be described, with reference to figure 2.

Step 201 involves the switching on, and consequently the booting up, of the computing device 100.

In step 202 the computing device system hardware and software will be initialized, which will include the loading of the operating system.

In step 203 the hardware timer 101 is initialized, which includes the setting of an initial counter value to which the timer counter will be reset, the setting of a timer expiry counter value and the resetting of the timer counter to the initial count value.

In step 204 the software watchdog timer is started, which involves the starting of the hardware timer counter counting from the initial counter value.

In step 205 the operating system kernel is started in which scheduled activities are run, for example battery management code, as described above.

e ë I ëe eve r d As stated above, any reoccurring event that has a scheduled period less than the chosen hardware timer expiry period can be used to 'tickle' the hardware timer 101, which in this embodiment can either be the idle/null thread or a scheduled kernel activity. Accordingly, within this description the hardware timer 101 can be arranged to be tickled' by one of two different mechanisms.

Steps 206 to 209 illustrate the operation of the software watchdog in which a scheduled kernel activity is used to tickle' the hardware timer 101, while steps 210 to 215 illustrate the operation of the software watchdog in which the idle thread is used to 'tickle' the hardware timer 101.

One or other of these mechanisms would typically be used.

In step 206 if a scheduled activity is running it will periodically tickle the hardware timer 101.

In step 207 and 216 a determination is made as to whether the hardware timer has been reset. If the hardware timer has been reset (i.e. the processor 102 is not in a continuous processing loop) then step 208 is started, which in this embodiment the scheduled kernel activity is the battery monitoring system. The battery monitoring is scheduled periodically. Each time the battery monitoring is scheduled the kernel software is arranged to 'tickle' the hardware timer 101, the kernel software then executes the battery monitoring software for monitoring the battery.

If the hardware timer has not been reset (i.e. the processor 102 is running a continuous processing loop and is unable to serve any other activities) then step 217 illustrates the timer expiry and the providing of the high sea 688 e 8 8 8 8. a 8 . 8 8 8 . . - 9 priority interrupt from the hardware timer 101 to the processor 102.

In step 218 the processor 102 stops the operational mode in which the continuous processor loop is being run and executes software code 108, which is arranged to assist in the diagnostic of the cause of the software lock up, for example saving and/or outputting system context and state information.

In step 219 the processor 102 is re-initialised to place the processor 102 back into a normal operation mode to allow execution of application programmed stored on the computing device 100.

In step 210 a kernel scheduler is run, where the kernel scheduler is part of the operating system and is responsible for determining which parts of software are executed at any given time, as is well known to a person skilled in the art.

In step 211 code for an application program stored on the computer device 100 is selected by a user to be executed by the processor 102.

Steps 210, 211 and 212 illustrate the control of the execution of the selected code.

If a continuous processor loop has been entered the steps 210, 211 and 212 will continue to be repeated.

Step 213 illustrates the idle thread, which is software that is executed by the kernel scheduler when no other software is ready to be executed, that is entered upon the successful completion of the execution of an application program on the processor 102.

Step 214 illustrates the resetting of the hardware timer 101 if step 213 is reached.

If the hardware timer 101 has been reset step 215 is entered in which the processor 102 enters a sleep mode. For example, this could consist of a set number of loops in order to pass time or where no instructions are executed by the processor 102 for a pre-programmed time period, where this period can be broken by an external hardware signal, for example an interrupt.

If the hardware timer has not been reset (i.e. the processor 102 is running a continuous processing loop and is unable to serve any other activities) then step 217 illustrates the timer expiry and the providing of the high priority interrupt from the hardware timer 101 to the processor 102.

8 8 a 8 8 8 sea 8 848 8 8 8 8 8 8 8 8 e 8 18 * a a ' It will be apparent to those skilled in the art that the disclosed subject matter may be modified in numerous ways and may assume embodiments other than the preferred form specifically set out as described above, for example the computing device described above would additionally include a hardware watchdog as a back up to the described software watchdog. . . .

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Claims

Claims 1. A computing device comprising a timer for generating a counter

value; and a processor arranged to operate in a first operation mode that allows the timer counter value to be periodically reset; wherein upon the processor operating in a second operational mode in which the timer counter value is not periodically reset the timer is arranged to provide an interrupt signal to the processor upon the counter value reaching a predetermined value to allow the processor to stop operating in the second operational mode.
2. A computing device according to claim 1, wherein the counter value is reset based upon the generation of a system idle thread.
3. A computer device according to claim 1, wherein the counter value is reset based upon a scheduled kernel action.
4. A computer device according to claim 3, wherein the scheduled kernel action is a battery monitoring action.
5. A computer device according to any preceding claim, wherein the time taken for the timer to count from the timer reset count value to the predetermined value is a predetermined time period.
6. A computer device according to any preceding claim, wherein the priority of the interrupt signal sent from the timer to the processor is higher than the priority of the tasks running on the processor when in the second operation mode. . .

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7. A computer device according to any preceding claim, wherein upon the processor stopping operating in the second operational mode the processor is arranged to save system data associated with the second operational mode.
8. A computer device according to any preceding claim, wherein upon the processor stopping operating in the second operational mode the processor is arranged to save processor state information associated with the second operational mode.
9. A computer device according to any preceding claim, wherein upon the processor stopping operating in the second operational mode the processor is arranged to display system data associated with the second operational mode.
10. A computer device according to any preceding claim, wherein upon the processor stopping operating in the second operational mode the processor is arranged to display processor state information associated with the second operational mode.
11. A computer device according to any preceding claim, wherein upon the processor stopping operating in the second operational mode the processor is arranged to operate in the first operational mode.

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