GB2411013A

GB2411013A - Electronic device and methods of interrupting a processor

Info

Publication number: GB2411013A
Application number: GB0402879A
Authority: GB
Inventors: Arnaud Lenoir; Kirem Dominic Rahmani
Original assignee: Sendo International Ltd
Current assignee: Sendo International Ltd
Priority date: 2004-02-10
Filing date: 2004-02-10
Publication date: 2005-08-17
Anticipated expiration: 2024-02-10
Also published as: GB0402879D0; WO2005076144A3; GB2411013B; WO2005076144A2

Abstract

A method of reading data from a peripheral device (126) via a 1-Wire interface (128) using a GPIO pin (202) connected to an interrupt pin (204) on a signal processor (108) comprises initialising the GPIO pin (202) as an input and initiating an interrupt timer in response to identifying an interrupt event. The method further comprises monitoring the timer to identify a start-bit rime (404); and reading data (402) from the 1-Wire interface (128) once the start-bit time (404) has been reached. A method of writing data on such a 1-wire interface and an electronic device comprising the 1-wire interface are also described. In this manner, by provision of a GPIO pin coupled to an interrupt pin (say an FIQ power fail interrupt pin), a 1-wire interface can be used in both a read and write mode of operation by linking the timer to the interrupt mechanism and controlling polarity levels on the 1-wire interface.

Description

-- .

ELECTRONIC DEVICE AND METHODS OF INTERRUPTING A PROCESSOR

THEREIN

Field of the Invention

The present invention relates to an electronic device with a processor and methods of interrupting the processor. The invention is applicable to, but not limited to, interrupting a processor in a wireless communication unit such as a mobile phone.

Background of the Invention

Wireless communication devices, such as mobile phone handsets, require a very high level of integration of hardware, firmware and/or software in order to achieve the necessary density of functionality, i.e. to realise the necessary functionality in a minimum device volume and at a minimum cost. An optimal mobile device design must also minimise power consumption in order to maximise the battery call time and/or stand-by time. In order to achieve such integration, such devices are increasingly designed to use highly integrated processor/controller integrated circuits.

The l-wire interface from Dallas-Semiconductor_ is a low cost data interface that can be used to route data to/from processor/controller integrated circuits. This l-wire interface is used in embedded devices, such as the Dallas iButton device as well as battery charge measurement devices, such as the bq26200 from Texas Instruments_ (TI). The functioning of the l-wire interface is described in detail in the TI application : cr.

: . . ee. he : l note for the aforementioned device, which is available from the TI web site. The l-wire interface is commonly used to communicate between a master device and a slave or peripheral device and can be used as a communications means between a microprocessor and any component with a suitable communications interface.

The l-wire interface is a common standard interface on a microprocessor system. If the microprocessor does not support the interface natively, then an external interface chip can be used (see Dallas Semiconductor Application note 145, "Interfacing the l-Wire master to an ARM7 Processor") or the interface can be simulated with an WART. A problem with such an approach is that the addition of an external interface chip as a bus- master device adds cost and increases power consumption.

These different modes are specified in the previously mentioned documentation.

Thus, a need exists for a method and means of incorporating a peripheral device, such as a battery charge measurement device, utilising a standard l-Wire interface, within a wireless communication unit, without incurring the cost and complexity associated with the above mentioned solutions and thus alleviating the associated problems.

Statement of Invention

In accordance with a first aspect of the present invention, there is provided a method of reading data from a peripheral device via a l-Wire interface using a r e I . / I / . 3 general purpose input output pin (GPIO) of a signal processor, as claimed in Claim 1.

In accordance with a second aspect of the present invention, there is provided an electronic device, as claimed in Claim S. In accordance with a third aspect of the present invention, there is provided an electronic device, as claimed in Claim 9.

In accordance with a fourth aspect of the present invention, there is provided a method of writing data to a peripheral device via a 1-Wire interface using a general purpose input output pin (GPIO) of a signal processor or to the signal processor from the peripheral device, as claimed in Claim 10.

In accordance with a fifth aspect of the present invention, there is provided an electronic device, as claimed in Claim 16.

In accordance with a sixth aspect of the present invention, there is provided an electronic device, as claimed in Claim 17.

Further features of the present invention are as defined in the appended Claims.

In summary, an electronic device such as a wireless communication unit incorporates a signal processor and one or more peripheral devices utilising the 1-Wire communication bus is described, whereby the signal e : : e: . _ - 4 processor is interfaced to the one l-wire interface using only standard functions of the sTynal processor such as one or more general purpose input-output (GPIO) pin(s), interrupt(s) and hardware timer(s).

In this manner, all resources of the wireless communication device that support the l-Wire interface can be accessed by the signal processor without the additional cost of an external bus master chip or UART or similar device.

In the context of a mobile phone, the provision of a simple l-wire interface mechanism allows a reduction in volume, cost and power consumption of the wireless communication unit, thus providing significant advantage to its manufacturer.

The expression 'peripheral device', in the context of the present invention, encompasses or extends to any functional unit of the wireless communication unit such as the display, signal processor, soundgeneration system, wireless interface, battery charge measurement unit, keypad, etc. or any part thereof which does or may support a l-Wire interface.

Brief Description of the Drawings

Exemplary embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which: . e e e e e _ _ 5 FIG. l illustrates a block diagram of a wireless communication unit adapted in accordance with the preferred embodiment of the present invention; FIG. 2 illustrates a schematic of the signal processing unit and peripheral device of a wireless communication unit linked by a l-wire interface, in accordance with a preferred embodiment of the present invention; FlG's 3, 4, and 5 illustrate schematically the marshalling of data on the l-wire interface, and the timing of the data, in accordance with a preferred embodiment of the present invention; FIG's 6, 7, and 8 illustrates schematically preferred methods of reading data from a l-wire interface; and FIG. 9 and FIG. lO illustrate schematically preferred methods of writing data to a l- wire interface.

Description of Preferred Embodiments

The preferred embodiment of the present invention will be described in terms of a mobile telephone. The preferred application is with the Perseus-l micro-controller manufactured by TIN, which does not support a l-wire interface, per se. However, it will be appreciated that the inventive concepts may be embodied in any other type of resourceconstrained device that incorporates embedded intelligence (microcontroller, micro-processor or digital signal processor (DSP), etc.) that may be required to interface to a l-wire interface, for example a personal digital assistant (PDA). It is also envisaged e that the inventive concepts of the present invention are not limited to wireless communication units, as fixed communication units, such as business/home telephone devices that connect to the public services telephone network (PSTN), car, weather station, global positioning system (GPS) device, etc. also often utilise embedded microprocessor intelligence and include active peripheral devices.

Referring first to PIG. 1, there is shown a block diagram of part of a communication unit 100, adapted to support the inventive concepts of the preferred embodiments of the present invention. The communication unit 100, in the context of the preferred embodiment of the invention, is a mobile phone. As such, the communication unit 100 contains an antenna 102 preferably coupled to a duplex filter or antenna switch 104 that provides isolation between receive and transmit chains within the wireless communication unit 100. The receiver chain, as known in the art, includes receiver front-end circuitry 106 (effectively providing reception, filtering and intermediate or baseband frequency conversion). The front-end circuit is serially coupled to a signal processing and/or microprocessor controller function 108.

The signal processing and/or microprocessor controller function 108 is often realized by a digital signal processor (DSP) and controls operations of, and communication between, elements within the communication unit 100. An output from the signal processing and/or microprocessor controller function 108 is provided to a suitable output device 110, such as a display or a loudspeaker.

. . ee. : .. :. ::.

. . - - 7 The signal processing and/or micro-processor controller function 108 is also coupled to a memory device 116 that stores operating regimes, such as decoding/encoding functions and the like and may be realised in a variety of technologies such as a volatile random access memory (RAM), nor--volatile read only memory (ROM), flash memory or any combination of these. A timer 118 is typically coupled to the signal processing and/or microprocessor controller function 108 to control the timing of operations (transmission or reception of time-dependent signals) within the communication unit 100.

As regards the transmit chain, this essentially includes an input device 120, such as a microphone and/or keypad, coupled in series through transmitter/modulation circuitry 122 and a power amplifier 124 to the antenna 102. The transmitter/ modulation circuitry 122 and the power amplifier 124 are operationally responsive to the signal processing and/or microprocessor controller function 108.

In accordance with the preferred embodiment of the present invention, the signal processing and/or microprocessor controller function 108 has at least one 1-wire interface with a device, such as a battery 126 of the communication unit 100. The signal processing and/or micro-processor controller function 108 is modified such that a general purpose input/output (GPIO) pin of the signal processing and/or micro-processor controller function 108 is connected directly to a second input pin of the function capable of triggering an interrupt in the signal processing and/or micro-processor controller function 108. Thus, a peripheral device such as a . e: a. :. .:.

- . - - 8 battery 126 of the mobile wireless communication unit 100 is able to communicate directly with the signal processing and/or micro-processor controller function 108 via a 1-wire interface 128 to both a GPIO pin and a further interrupt pin of the signal processing and/or micro-processor controller function 108.

Advantageously, as will become apparent in the foregoing

description, this interface realization requires a

minimum of hardware resources and results in a lower cost and more powerefficient design.

The preferred embodiment of the present invention is further described with reference to FIG. 2, which illustrates a schematic diagram 200 of the signal processing and/or microprocessor controller function 108 of FIG. l, operably coupled to a peripheral device 126.

The coupling is performed using a 1-wire interface 128, with the input pin to the signal processing and/or micro processor controller function 108 preferably being a Fast Interrupt request (FIG) power fail interrupt pin 204.

Notably, a GPIO pin 202 is also connected to the 1-Wire interface 128 of the peripheral device 126, with which the signal processing function must communicate.

Furthermore, the 1-Wire interface 128 is also preferably connected to a positive logic voltage supply of the wireless cornmunicatiorl unit via a pul-up resistor 206.

The firmware of the signal processing and/or micro processor controller function 108 is also preferably modified to include a driver (not shown) for the 1-wire interface 128, in accordance with the present invention, : :e:: l where the driver is capable of interpreting and reacting correctly to signals carried on the 1-wire interface 128.

Thus, in this manner, a 1-Wire interface 128 has been provided on a wireless communication unit incorporating a signal processing and/or microprocessor controller function 108 by means of a GPIO pin 202, an interrupt pin 204, and an internal (or in alternative embodiments an external) timer resource 218. In particular, the GPIO pin 202 is tied to the positive logic voltage supply 206 of the signal processing and/or microprocessor controller function 108 and is configured as either an input or an output. The interrupt pin 204 is preferably used in a read' mode to flag the arrival of a data bit, and the internal timer 218 is preferably used to determine the bus timing for both 'reading' and 'writing' modes of operatior-.

In an advantageous embodiment of the present invention, the power fail interrupt pin (FIQ) 204 is used in order to circumvent the de-bounce filtering at the input of the GPIO pin 202, which delays the recognition of the falling edge of the input signal on the pin, i.e. the start-bit is not accurately detected and this makes accurate bus timing difficult or in some cases impossible.

The inventive concepts associated with the above operations are further described with respect to the illustrations in FIG's 3 to 10.

Referring now to FIG's 3, 4, and 5, schematic diagrams 300, 400, 500 are shown that illustrate the marshalling of data and the timing of the data on the 1-wire #ce e ' ' *a: - 10 interface, in accordance with preferred embodiments of the present invention. The basic functionality of the 1- wire interface can itself be better understood with reference to the schematic timing diagram 300 of FIG.3 which is not to scale. Let us assume, for example, that there are always 8-bits of command data 310, with the 8th bit included in time period 310 used to indicate if the device accessing the 1-wire interface wishes to be in a writing '1' or a reading '0' mode. A time period 304 corresponds to a time between the command and the byte required to read or write data. In a reading mode, the time period 304 allows a micro-controller enough time to receive an answer from the peripheral device. Thus, in effect, time period 304 provides a timeout function in a reading mode. This is followed by a further eight data bits 302 (for writing or reading data), to make up one complete bus transaction 306.

In operation, a signal processor, say signal processing and/or microprocessor controller function 108 of FIG. 1 or FIG. 2, is able to write data to, or read data from, the peripheral device. In a writing mode, (where the last bit is set 'high' within period 310), the writing of command data on the 1-wire interface bus on a GPIO pin, such as GPIO pin 202 of FIG. 2, is preferably dictated by the internal timer 218 of FIG. 2. In a reading mode, (where the last bit is set 'low' within period 310) a time-out system is preferably implemented, in case the peripheral device (say peripheral device 126 of FIG. 1 or FIG. 2) fails to respond in time period 304. In a preferred embodiment, an interrupt signal, for example a signal applied to FIQ Power Fail interrupt pin 204 in FIG. 2, is used in the 'reading' mode to detect any . . ... A- :. ë response from the peripheral device connected to the 1 wire interface bus. Preferably, the FIG Power Fail interrupt 204 is used only in a 'reading' mode, whereas the rest of the time this interrupt is disabled.

Thus, a first part of a transaction 310 is ended with a data direction determining bit at the end of period 310 (not shown), which dictates whether the following 8 data bits 302 of the transaction are to be read or written.

Referring now to FIG. 4, a more detailed timing diagram 400 is shown, for a single data-bit, on the 1-Wire interface. In this regard, a data bit 402, having a start time instant 404 and a stop time instant 412, delimited by start bit/data bit 414 and data bit/stop bit 406, follows a 'low' start bit 404. A 'stop' bit 412 follows the data bit 402. In the example shown, the total time for one bit is at least 190uS, which preferably breaks down approximately as follows: (i) 32us to 50us for 'start' bit 404 (when the data' bit = 'l'); (ii) 100,us to 145us for 'start' bit + 'data' bit 402 (when the 'data' bit = '0', i.e. the data bit 402 and the start bit 404 have the same value '0')i and (iii) Stop bit 412 is the remaining time between the 'data' bit 402 and the next 'start' bit 404.

Consequently, the timing of the 'stop' bit will effectively vary, as a minimum in this particular case, between 45gs to >90Jsec.

Once the 190usec has elapsed, there is preferably no fixed time for the next 'start' bit to be applied.

. . : .. :. ::..

. ' - : . Referring next to FIG.5, a schematic timing diagram 500 illustrates the difficulties associated with performing a successful 'read' or 'write' operation on a 1-Wire interface bus. A first timing diagram 500 illustrates a read' operation, which comprises a 'low' start bit 502.

It can be seen that, the determination of whether a data bit 504 is a '1' or a '0' is somewhat dependent upon the value of the stop bit 506, for example a high' value of the stop bit 506 in a 'read' mode of operation. Thus, if the data bit 504 is a '1', and the data bit's value is sampled late, the stop bit will be sampled and this is also a value of '1'. Hence, the correct value will be obtained, albeit that the wrong bit is sampled. However, if the data bit 504 is a '0', and its value is sampled late, the stop bit 506 will be sampled and therefore an incorrect value will be obtained by sampling the wrong bit in a read mode of operation.

Similarly, a second timing diagram 520 illustrates a write' operation, which comprises a 'high' stop bit 522.

It can be seen that, the determination of whether a data bit 526 is a '1' or a '0' is somewhat dependent upon the time spent by the start bit 524 and the data bit 526 at a '0' level. For example, a 'low' data bit value means that start bit 524 and data bit 526 are at a '0' level longer than it would have been if the data bit was at a high' data bit value, i.e. as only start bit 524 would be at a 'O' level in this 'write' mode.

Thus, if the start bit 524 is longer than expected in a case of a '1', the 1-wire interface within battery 126 is able to sample and interpret it as a 'O' in a write mode I::. .::. -..e - 13 of operation. It is important in a 'write' mode of operation to control the timing of the 'O' levels on the 1-wire interface 128.

Thus, in summary, in a read mode of operation, a primary problem exists in reading the data bit at the precise instant in time. In a write mode of operation, a primary problem exists in writing a start bit and a data bit (if it is 'O') for an appropriate duration.

Referring now to FIG. 6, a preferred embodiment of the present invention is shown in which the 1-wire interface is being 'read' by, say, the signal processing and/or micro-processor controller function 108 of FIG. 1 or FIG. 2 (i.e. the first reading process). A last command bit 602 of a command string is set 'low', thereby indicating that a bus 'read' operation is to be performed. As soon as the next negative edge 604 is detected on the interrupt pin (i.e. FIQ Power Fail pin 204 of FIG. 2) by the signal processing and/or microprocessor controller function, an Interrupt Service Routine (ISR), such as a FIQ Power Fail ISR is executed.

At that point the FIQ power-fail interrupt routine is disabled and cleared and a hardware timer is started 606.

The hardware timer is preferably loaded with a value that corresponds to a time 612 at which the data bit 608 is expected to be on the bus. When the timer decrements to a value of 'zero', the data bit is read inside the reading data bit window 608. Notably, it is also possible to perform the data 'read' operation from within the SR of the FIQ timer interrupt 608. Advantageously, this prevents the read operation from being interrupted.

: c: Ace: . :- : - 14 l As soon as the data bit 608 is read, the FIQ power Fail ISR is activated for the next bit to be read, and so on.

Thus, in summary, when the data bit is read, the FIQ power-fail ISR is activated for the next bit.

Thereafter, when each of the eight bits has been read, the interrupts are disabled until another transaction is commenced. Notably, prior to the writing of the last bit of the command and the first bit to be read, a timer is used for the detection of a timeout.

Advantageously, this 'read' methodology could be used if the time to transmit a bit is important, for example where the time to transmit a start bit is, say, 500,usec or more. Furthermore, the methodology ensures that the read' operation will not be interrupted, for example when a FIQ ISR is befog used without any risk of the FIQ interrupts being disabled. Additionally, there is no significant delay in a treatment of an interrupt and, as such, the interrupt latency times are constant.

In effect, when in an FIQ Power fail case, it is possible to set a timer for the next timer interrupt to read the data. The timer is set for, say, 'x' seconds, which corresponds to the time needed to wait before the data can be read.

FIG. 7 illustrates a schematic 700 of a mechanism of reading' data from a l-wire interface, in accordance with an alternative embodiment of the present invention (i.e. a second reading process). A hardware timer is preferably loaded with a value that corresponds to a maximum time that is allowable for a transmission of l ee. t: e. :. A:..

. . .

-

eight bits of data; say a maximum time (corresponding to a time period exceeding periods 302 and 304 in FIG. 3).

Preferably, the signal processor maintains a look-up table of timervalues, where the timer-values correspond to the instants 710 at which each of the successive eight bits of data on the bus should be valid. The look-up table values are compared periodically with the current timer value, in order to generate an instant, such as instant 710, at which the data can be validly read from the bus.

At the end of the 8th bit of command the signal processor and/or controller function is set to receive data over the 1-wire interface. The FIQ Power Fail interrupt, i.e. the state of the interrupt on the 1-Wire interface bus, is enabled at the start of the byte transmission, and triggered by each start bit 704. In effect, a timer is linked to the interrupt to synchronize 702 to the bit reading 710.

The use of the timer is preferably twofold: (i) First, it defines and verifies the reading data bit window, to make sure the data bit is read at the right time instant 710; and (ii) Secondly, it facilitates a timeout for the transaction. Thus, when the interrupt is linked to the timer and all the bits to be read are not received, the transaction has failed. The cause could be that no bits were received, for example the 1-wire interface malfunctioned, or the communication link was broken during the time the peripheral device was sending the data. With this timeout method, it is always possible to recover the data in the case of a communication failure, . e: - e-e - 16 as the occurrence of a timer interrupt indicates the 8 bits of data were not received - on receipt of the 8th data bit the timer is stopped and the next transaction is executed.

After each trigger, a data bit 706 must be read. This is carried out preferably in the ISR of the FIQ Power Fail interrupt routine 708, where each data bit 706 is sampled within a sampling window 710. The timer defines the sampling window 710 and the corresponding bit value in the look-up table. In this preferred embodiment, it is impossible for the signal processor to be further interrupted, which would cause the timing to be incorrect. Thus, and advantageously, all data bits can be read in the reading data bit window in this manner.

The timer is loaded, in this example, with a value that corresponds to the eight-bit transmission time. Thus, if the timer has timed-out and generated an interrupt, and eight bits of data have not been read from the bus, then it is possible to identify that a maximum byte transmission time has over-run and the process is stopped. Thus, the embodiment illustrated in FIG. 7 ensures that it is always possible to recover elegantly in the case of any bus failure.

In summary, when the data bit is read, the FIQ power-fail interrupt routine is activated for the next bit.

Thereafter, when the eight bits are read, the interrupts are disabled until another transaction is commenced.

Notably, prior to the writing of the last bit of the command and the first bit to be read, a timer is used for the detection of a timeout (to limit the time of the I. I. c: i. . c:

- - -

reading operation in case all of the bits are not received), whilst at the same time ensuring that eight data bits are read at the right time within time period 710.

Advantageously, this 'read' mechanism could be used if the time to transmit a bit is not very important, for example where the time to transmit a start bit is, say, 50usec to lOOusec. This ensures that there will be no interruptions during the 'read' operation. Additionally, there is no significant delay in a treatment of an interrupt and, as such, the interrupt latency times are constant.

The process of performing a bus read operation could be better understood by reference to FIG. 8, which shows a detailed view of a l-bit bus-read operation 800 according to the second embodiment of reading the data in the present invention. The timer is assumed to be decrementing (or incrementing) during time 804, where the origin or reference point is at some time in the past 812. When a falling edge 806 occurs on the l-wire interface an interrupt signal, such as an FIQ Power Fail interrupt for the Perseus-l IC (or an equivalent system employing an IRQ or FIQ for another microcontroller), is generated.

When this interrupt is entered, the timer register is read and compared with a value in a look-up table (a predefined table containing all the valid data bit reading windows 808. For each of the 8 bits, both a start of window 800 and an end of window value 802 are t. :e..... .

stored, in order to clearly identify a data bit reading window.

Once in the read-window 808, the data bit is sampled, say three times to ensure a correct read operation, e.g. a 000 or 111 result that means the reading of the data bit was successful. If the result of the read operations is 001 or 011, i.e. the bit values are not all the same, and then the read is declared to be false. In this case the transaction will be completed but subsequently declared as false and repeated.

After the data bit has been read, the timer is read once more to ensure that the maximum read time has not been exceeded 802. If, for any reason, any one of the data bits is read outside of its defined read-window 808, then the transaction is declared as false. In this case, at the end of the transaction, the break command is executed; and the transaction is repeated. A time period 810 represents the time spent in the FIG Power fail interrupt ISR, which corresponds to a time covering the start bit and data bit 814.

Referring now to FIG. 9, a preferred mechanism 900 for writing data (1St writing method) is illustrated. A series of bits are written from the signal processor and/or controller function to the 1-wire interface peripheral device. For example when the second bit is written, a timer interrupt occurs after the first bit.

Notably the timer interrupt is applied such that the minimum required time has elapsed from the first bit. At that time 1-Wire interface bus is set to a '0' for the start bit. Furthermore, the next timer interrupt is ::e see.e:: . 1 ' _ / 8 - 19 programmed to instigate the stop bit. The time for the next timer interrupt depends on the data bit to transmit.

If it is a '1', the time corresponds to the start bit (i.e. it is less than 50usec). If it is a 'O' the time for the next timer interrupt is set to the sum of the start bit + data bit (i.e. between lOO, usec and 145usec) in the preferred application.

When the 1-Wire interface bus is set at a '1' for the stop bit, the next timer interrupt is programmed to generate the next start bit (i.e. the time is calculated to be at least 190us). When we reach the 8th bit of the command is reached, the mode of operation is transferred from a writing mode to a reading mode, where the 1-Wire interface bus is set to be aninput.

Advantageously, this 'write' methodology can be used if the time to transmit a bit is important, for example where the time to transmit a start bit is, say, 500usec.

Furthermore, the methodology ensures that the 'read' operation will not be interrupted, for example when a FIQ ISR is being used without any risk of the FIQ interrupts being disabled. Additionally, there is no significant delay in a treatment of an interrupt and, as such, the interrupt latency times are constant.

Referring now to FIG 10, a method of performing a bus write (1St writing method) according to an alternative embodiment the present invention, is illustrated.

Circles 1000 indicate the output bit times, when the 1 wire interface line (128 of FIG. 1) is at a '0' level.

Advantageously, only a hardware timer is required to perform the data write operation, where the FIQ Power e e e e e e e e e e e e e e e e e - 20 Fail interrupt is disabled, thereby reducing the time required for the bus transaction.

First, the timer is forced to overflow to cause the ISR to be entered 1002 and its code executed 1000. The timer interrupt used to generate time instant 1002 is disabled and the timer is utilised to generate the timing required for generating the start-bits and data bit. The time spent in the interrupt 1000 encompasses the start bit and the data bit. Time periods 1004 correspond to a start bit followed by a data bit = '0', whereas time periods 1006 correspond to a start bit, when the data following data bit is a '1'. The timer is loaded with a value corresponding to the data to be transmitted. For example, in the case where data bit = '1', the timer is loaded with just the start bit time; and in the case of data bit = '0', the timer is loaded with both the start bit and the data bit. The timer is preferably polled until it reaches zero (in the decrementing case), at which point the 1-Wire interface value is set back to 1' . The timer is then re-set with a value large enough to ensure that the minimum required data bit transmission time is maintained (minimum is l90,us in this example) and the timer interrupt is enabled.

This process is repeated for all 8 bits of command or data (write). During the 8th bit of the command, the wire can be set to indicate a read operation from, or a write operation to, the peripheral device connected to the 1-wire interface interface.

J/ :: ce ee Ale: :: . .. :e - 21 In the context of a 'writing' mode of operation, for example with reference to the circuitry of FIG. 2, the pull up resistor maintains the voltage level on the 1- wire interface as always high '1', such that an open collector is simulated on the GPIO line. In order to achieve this, the GPIO bit in an associated register is initially programmed to have always the output at '0'.

Thereafter, to generate a '1' on the 1-Wire interface, the GPIO line is set as an input (by default the signal processor and/or controller function is always listening the 1-wire interface). In this mode, the 1wire interface line is in its idle state. To generate a 'O' on the 1-wire interface, the GPIO line is set as an output similar to an open collector output.

The advantage of this method is to avoid several accesses to the GPIO registers to change the status of the line (input-to-output and vice versa). In effect, all that is needed to change the direction of the 1-wire interface line is to simulate a 'O' or a '1' on the line.

Thus, the present invention provides a number of advantages over current wireless devices incorporating 1 Wire interfaces such as mobile phones, PDA's etc. The inventive concepts described herein find particular applicability when it is necessary for reasons of cost, power consumption or PCB space to interface signal processor hardware to a peripheral device via a 1-Wire interface when the processor hardware does not natively support the interface. .

.e.:e ce. .:e eeee. ë - 22 As an example, a l-Wire based battery charge measurement peripheral may be interfaced to the system host processor/DSP of a wireless device via one of the host's GPIO lines, thus allowing such peripherals to be added to the wireless device at a late stage in the development without requiring that the hardware of the signal processor or its interface logic be modified.

Whilst the specific and preferred implementations of the embodiments of the present invention are described above, it is clear that one skilled in the art could readily apply variations and modifications of such inventive concepts.

Thus, methods and apparatus for incorporating a peripheral device such as a battery charge measurement device utilizing a standard l-Wire interface, within a wireless communications device have been described, where

the aforementioned disadvantages with prior art

arrangements have been substantially alleviated. .

Claims

ë :. ë : .e. ec. - 23

Claims 1. A method of reading data from a peripheral device (126) via a 1-wire interface (128) using a general purpose input output pin (GPIO) (202) of a signal processor (108), wherein the method is characterized by the following steps: initializing the GPIO pin (202) to which the 1 wire interface (128) is connected as an input or an output; identifying an interrupt event; initiating an interrupt timer associated with the signal processor (108) in response to the interrupt event; monitoring the timer in order to identify a start-bit time (404); and reading data (402) from the 1-wire interface (128) once the start-bit time (404) has been reached.
2. A method of reading data from a peripheral device (126) according to Claim 1, further characterized by the step of connecting the GPIO pin (202) to an interrupt pin (204) of the signal processor (108);
3. A method of reading data from a peripheral device (126) according to Claim 1 or Claim 2, further characterized by the step of clearing an interrupt state after having read data (402) from the 1- Wire interface (128).
4. A method of reading data from a peripheral device (126) according to any preceding Claim, wherein the step of reading reads one data bit at a time, the method / ë.:: e.e e:e .e Bec. - 24

further characterized by the step of repeating steps of monitoring, reading and clearing until each data bit from a transmission or part of a transmission has been read.
5. A method of reading data from a peripheral device (126) according to any preceding Claim further characterized in that the interrupt used is a power fail interrupt associated with the peripheral device.
6. A method of reading data from a peripheral device (126) according to any preceding Claim, further characterized by the step of: loading the timer with a data value corresponding to substantially a maximum allowable 1-wire byte transmission time of the peripheral device (126), the timer being started on receipt of the start bit (404) corresponding to the first data bit (402).
7. A method of reading data from a peripheral device (126) according to any preceding Claim, wherein the step of reading a data bit (402) comprises over-sampling in the reading process, the method further characterized by the step of: stopping a data transfer upon determination of an erroneous sample or a timer time-out.
8. An electronic device (100) comprising a signal processor (108) having a general purpose input output pin (GPIO) (202) and an interrupt pin (204) operably coupled to a peripheral device (126), wherein the electronic device is adapted to perform the method steps of any of the preceding Claims.

:: e. ee. :: :.

: : :: Ic: - 25
9. An electronic device (100) comprising: a signal processor (108) having a general purpose input output pin (GPIO) (202) and an interrupt pin (204) i a peripheral device (126), operably coupled to the signal processor (108) for the signal processor to read data from the peripheral device or for writing data to the peripheral device (126) by the signal processor (108)i a 1-Wire interface (128), arranged to operably couple the peripheral device to the GPIO pin (202); and a programmable timer operably coupled to the signal processor (108); wherein the electronic device (100) is characterized such that the signal processor (108) identifies an interrupt event and initiates a timer to identify a start- bit time (404) for data to be read from the 1-Wire interface (128).
10. An electronic device (100) according to Claim 9 further characterized in that the GPIO pin (202) is operably coupled to the interrupt pin (204).
11. A method of writing data to a peripheral device (126) via a 1-wire interface (128) using a general purpose input output pin (GPIO) (202) of a signal processor (108) or to the signal processor (108) from the peripheral device (126), wherein the method is characterized by the following steps: linking a timer to an interrupt on the 1-wire interface (128); setting a logic level on the GPIO pin (202) to perform a start bits e e - 26 loading the timer with a value to enable start bit and data bit to be written on the GPIO pin (202) of the 1-wire interface (128); and identifying an interrupt and disabling the timer in response thereto.
12. A method of writing data to a peripheral device (126) or to a signal processor (108) via a 1-Wire interface (128) according to Claim 11, further characterized by the steps of: re-setting the data on the GPIO pin (202) to a logic level to perform a start bit; and re-loading the timer with a value corresponding to the required transmission time for a stop bit (404).
13. A method of writing data to a peripheral device (126) or to a signal processor (108) via a 1-Wire interface (128) according to Claim 11 or Claim 12, further characterized by the step of: disabling an interrupt associated with an interrupt pin (204) attached to the 1-Wire interface (128) prior to writing data.
14. A method of writing data to a peripheral device (126) or to a signal processor (108) via a 1-Wire interface (128) according to any of preceding Claims 11 to 13, further characterized by the step of: repeating the steps of disabling, re-loading and setting until all data bits have been written to the peripheral device (126) or to the signal processor (108).
15. A method of writing data to a peripheral device (126) or to a signal processor (108) via a 1-Wire

J

'.. e:: cece :e etece.e - 27 interface (128) according to any of preceding Claims 11 to 14, further characterized by the step of: polling the timer until a timer threshold is detected.
16. An electronic device (100) comprising a signal processor (108) having a general purpose input output pin (GPIO) (202) and an interrupt pin (204) operably coupled to a peripheral device (126), wherein the electronic device is adapted to perform the method steps of any of preceding Claims 11 to 15.
17. An electronic device (100) comprising: a signal processor (108) having a general purpose input output pin (GPIO) (202) and an interrupt pin (204); a peripheral device (126), operably coupled to the signal processor (108) for the signal processor to read data from the peripheral device or for writing data to the peripheral device (126) by the signal processor (108); a 1-Wire interface (128), arranged to operably couple the peripheral device to the GPIO pin (202); and a programmable timer operably coupled to the signal processor (108); wherein the electronic device (100) is characterized in that the GPIO pin (202) is operably coupled to the interrupt pin (204) such that the signal processor (108) identifies an interrupt event and initiates a timer to identify a start- bit time (404) for data to be read from the 1-Wire interface (128).
18. An electronic device (100) according to Claim 8 or Claim 9 or Claim 16 or Claim 17, wherein the te' c:: '.e c:e ë Ited - 28 electronic device is a wireless communication device, such as a mobile phone.
19. A wireless communications device (100) substantially as hereinbefore described with reference to, and/or as illustrated by, FIG. 1 and FIG. 2 of the accompanying drawings.
20. A method for writing data to a 1-Wire interface substantially as hereinbefore described with reference to, and/or as illustrated by, FIG. 9 or FIG. 10 of the accompanying drawings.
21. A method for reading data from a 1-Wire interface substantially as hereinbefore described with reference to, and/or as illustrated by, FIG.6 or FIG.7 and FIG.8 of the accompanying drawings.