WO2005076144B1 - Electronic device and methods of implementing the 1-wire protocol using an interrupt - Google Patents
Electronic device and methods of implementing the 1-wire protocol using an interruptInfo
- Publication number
- WO2005076144B1 WO2005076144B1 PCT/EP2005/050594 EP2005050594W WO2005076144B1 WO 2005076144 B1 WO2005076144 B1 WO 2005076144B1 EP 2005050594 W EP2005050594 W EP 2005050594W WO 2005076144 B1 WO2005076144 B1 WO 2005076144B1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- pin
- interrupt
- peripheral device
- signal processor
- data
- Prior art date
Links
- 230000002093 peripheral Effects 0.000 claims abstract 26
- 230000000977 initiatory Effects 0.000 claims abstract 2
- 230000005540 biological transmission Effects 0.000 claims 4
- 230000000875 corresponding Effects 0.000 claims 3
- 238000000034 method Methods 0.000 claims 1
- 238000005070 sampling Methods 0.000 claims 1
Abstract
A method of reading data from a peripheral device (126) via a 1-Wire interface (128) using a GPIO pin (202) connected to an interrupt pin (204) on a signal processor (108) comprises initialising the GPIO pin (202) as an input and initiating an interrupt timer in response to identifying an interrupt event. The method further comprises monitoring the timer to identify a start-bit interface (128) once the start-bit time (404) has been reached. A method of writing data on such a 1-wire interface and an electronic device comprising the 1-wire interface are also described. In this manner, by provision of a GPIO pin coupled to an interrupt pin (say an,FIQ power fail interrupt pin), a 1wire interface can be used in both a read and write mode of operation by linking the timer to the interrupt mechanism and controlling polarity levels on the 1-wire interface.
Claims
1. A method of reading data from a peripheral device (126) via a 1-wire interface (128) using a general purpose input output (GPIO) pin (202) of a signal processor (108) that supports debounce of signals, wherein the method is characterised by the following steps: initialising the GPIO pin (202) to which the 1- wire interface (128) is connected as an input or an output; connecting the GPIO pin (202) to an interrupt pin (204) of the signal processor (108) that does not support debounce of signals; identifying an interrupt event on the GPIO tpin
(202) by identifying an interrupt signal on the interrupt pin (204); initiating an interrupt timer associated with the signal processor (108) in response to the interrupt event; monitoring the timer in order to identify a start-bit time (404); and reading data (402) from the 1-wire interface (128) once the start-bit time (404) has been reached.
2. A method of reading data from a peripheral device (126) according to Claim 1, further characterised by the step of clearing an interrupt state after having read data (402) from the 1-Wire interface (128) .
3. A method of reading data from a peripheral device (126) according to any preceding Claim, wherein the step of reading reads one data bit at a time, the method further characterised by the step of repeating steps of monitoring, reading and clearing until each data bit from a transmission or part of a transmission has been read.
4. A method of reading data from a peripheral device (126) according to any preceding Claim further characterised in that the interrupt pin used is a power fail interrupt pin associated with the peripheral device.
5. A method of reading data from a peripheral device
(126) according to any preceding Claim further characterised by the step of: loading the timer with a data value corresponding to substantially a maximum allowable 1-wire byte transmission time of the peripheral device (126), the timer being started on receipt of the start bit (404) corresponding to the first data bit (402) .
6. A method of reading data from a peripheral device (126) according to any preceding Claim, wherein the step of reading a data bit (402) comprises over-sampling in the reading process, the method further characterised by the step of stopping a data transfer upon determination of an erroneous sample or a timer time-out.
7. An electronic device (100) comprising a signal processor (108) having a general purpose input output pin
(GPIO) (202) that supports debounce of signals and an interrupt pin (204) operably coupled to the GPIO pin (202) that does not support debounce of signals, both being coupled to a peripheral device (126), wherein the electronic device is adapted to perform the method steps of any of the preceding Claims.
8. An electronic device (100) comprising: a signal processor (108) having a general purpose input output pin (GPIO) (202) that supports debounce of signals operably coupled to an interrupt pin (204) that does not support debounce of signals; a peripheral device (126), operably coupled to the signal processor (108) for the signal processor to read data from the peripheral device or for writing data to the peripheral device (126) ; a 1-Wire interface (128), arranged to operably couple the peripheral device to the GPIO pin (202) ; and a programmable timer operably coupled to the signal processor (108); wherein the electronic device (100) is characterised such that the signal processor (108) identifies an interrupt event on the GPIO pin (202) by identifying an interrupt signal on the interrupt pin (204) and initiates a timer to identify a start-bit time (404) for data to be read from the 1-Wire interface (128) .
9. A method of writing data to a peripheral device (126) via a 1-wire interface (128) using a general purpose input output pin (GPIO) (202) of a signal processor (108) or to the signal processor (108) from the peripheral device (126), wherein the method is characterised by the following steps: linking a single timer to 'an interrupt on the 1- wire interface (128); setting a logic level on the GPIO pin (202) to perform a start bit; 31
loading the single timer with a value to enable start bit and data bit to be written on the GPIO pin (202) of the 1-wire interface (128); and identifying an interrupt and disabling the single timer in response thereto.
10. A method of writing data to a peripheral device (126) or to a signal processor (108) via a 1-Wire interface (128) according to Claim 9, further characterised by the steps of: re-setting the data on the GPIO pin (202) to a logic level to perform a start bit; and re-loading the single timer with a value corresponding to the required transmission time for a stop bit (404) .
11. A method of writing data to a peripheral device (126) or to a signal processor (108) via a 1-Wire interface (128) according to Claim 9 or Claim 10, further characterised by the step of: disabling an interrupt associated with an interrupt pin (204) attached to the 1-Wire interface (128) prior to writing data.
12. A method of writing data to a peripheral device (126) or to a signal processor (108) via a 1-Wire interface (128) according to Claim 11, further characterised by the step of: repeating the steps of disabling, re-loading and setting until all data bits have been written to the peripheral device. (126) or to the signal processor (108) . 32
13. A method of writing data to a peripheral device (126) or to a signal processor (108) via a 1-Wire interface (128) according to any of preceding Claims 9 to 12, further characterised by the step of: polling the timer until a timer threshold is detected.
14. An electronic device (100) comprising a signal processor (108) having a general purpose input output pin (GPIO) (202) and an interrupt pin (204) operably coupled to a peripheral device (126), wherein the electronic device is adapted to perform the method steps of any of preceding Claims 9 to 13.
15. An electronic device (100) comprising: a signal processor (108) having a general purpose input output pin (GPIO) (202) and an interrupt pin (204); a peripheral 'device (126), operably coupled to the signal processor (108) for the signal processor to read data from the peripheral device or for writing data to the peripheral device (126); a 1-Wire interface (128), arranged to operably couple the peripheral device to the GPIO pin (202) ; and a programmable single timer operably coupled to the signal processor (108); wherein the electronic device (100) is characterised in that the GPIO pin (202) is operably coupled to the
■ interrupt pin (204) such that the signal processor (108) identifies an interrupt event and initiates the single timer to identify a start-bit time (404) for data to be read from the 1-Wire interface (128) . 33
16. An electronic device (100) according to Claim 7 or Claim 8 or Claim 14 or Claim 15, wherein the electronic device is a wireless communication device, such as a mobile phone.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB0402879.1 | 2004-02-10 | ||
| GB0402879A GB2411013B (en) | 2004-02-10 | 2004-02-10 | Electronic device and methods of interrupting a processor therein |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| WO2005076144A2 WO2005076144A2 (en) | 2005-08-18 |
| WO2005076144A3 WO2005076144A3 (en) | 2005-11-24 |
| WO2005076144B1 true WO2005076144B1 (en) | 2006-01-26 |
Family
ID=32011614
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/EP2005/050594 WO2005076144A2 (en) | 2004-02-10 | 2005-02-10 | Electronic device and methods of implementing the 1-wire protocol using an interrupt |
Country Status (2)
| Country | Link |
|---|---|
| GB (1) | GB2411013B (en) |
| WO (1) | WO2005076144A2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI398755B (en) * | 2006-12-22 | 2013-06-11 | Hon Hai Prec Ind Co Ltd | Method for restoring an embedded system |
| CN101923525B (en) * | 2010-08-11 | 2012-02-29 | 清华大学 | General purpose in-out circuit with event capturing function |
| US8954628B2 (en) * | 2012-06-05 | 2015-02-10 | Htc Corporation | Portable device and peripheral extension dock |
| US8930586B2 (en) | 2013-04-03 | 2015-01-06 | Lenovo Enterprise Solutions (Singapore) Pte. Ltd. | Identification of electronic devices operating within a computing system |
| CN104460406B (en) * | 2014-10-13 | 2017-04-26 | 深圳市江波龙电子有限公司 | Single-line communication method and single chip microcomputer firmware updating method based on single-line communication |
| CN111858426B (en) * | 2020-06-05 | 2022-03-15 | 深圳市共济科技股份有限公司 | Electronic tag reading and writing system and method |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5862354A (en) * | 1996-03-05 | 1999-01-19 | Dallas Semiconductor Corporation | Universal asynchronous receiver/transmitter (UART) slave device containing an identifier for communication on a one-wire bus |
| US5978927A (en) * | 1996-03-05 | 1999-11-02 | Dallas Semiconductor Corporation | Method and system for measuring a maximum and minimum response time of a plurality of devices on a data bus and adapting the timing of read and write time slots |
| SE520126C2 (en) * | 1997-12-11 | 2003-05-27 | Axis Ab | I / O Processor and method for controlling peripherals |
| US6608571B1 (en) * | 2001-05-16 | 2003-08-19 | Globespanvirata, Inc. | System and method for communicating over a one-wire bus |
-
2004
- 2004-02-10 GB GB0402879A patent/GB2411013B/en not_active Expired - Fee Related
-
2005
- 2005-02-10 WO PCT/EP2005/050594 patent/WO2005076144A2/en active Application Filing
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