WO2005076144A3 - Electronic device and methods of implementing the 1-wire protocol using an interrupt - Google Patents

Electronic device and methods of implementing the 1-wire protocol using an interrupt Download PDF

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Publication number
WO2005076144A3
WO2005076144A3 PCT/EP2005/050594 EP2005050594W WO2005076144A3 WO 2005076144 A3 WO2005076144 A3 WO 2005076144A3 EP 2005050594 W EP2005050594 W EP 2005050594W WO 2005076144 A3 WO2005076144 A3 WO 2005076144A3
Authority
WO
WIPO (PCT)
Prior art keywords
interrupt
wire interface
pin
timer
electronic device
Prior art date
Application number
PCT/EP2005/050594
Other languages
French (fr)
Other versions
WO2005076144A2 (en
WO2005076144B1 (en
Inventor
Arnaud Lenoir
Kirem Rahmani
Original Assignee
Sendo Int Ltd
Arnaud Lenoir
Kirem Rahmani
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sendo Int Ltd, Arnaud Lenoir, Kirem Rahmani filed Critical Sendo Int Ltd
Publication of WO2005076144A2 publication Critical patent/WO2005076144A2/en
Publication of WO2005076144A3 publication Critical patent/WO2005076144A3/en
Publication of WO2005076144B1 publication Critical patent/WO2005076144B1/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4213Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with asynchronous protocol
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method of reading data from a peripheral device (126) via a 1-Wire interface (128) using a GPIO pin (202) connected to an interrupt pin (204) on a signal processor (108) comprises initialising the GPIO pin (202) as an input and initiating an interrupt timer in response to identifying an interrupt event. The method further comprises monitoring the timer to identify a start-bit interface (128) once the start-bit time (404) has been reached. A method of writing data on such a 1-wire interface and an electronic device comprising the 1-wire interface are also described. In this manner, by provision of a GPIO pin coupled to an interrupt pin (say an,FIQ power fail interrupt pin), a 1­wire interface can be used in both a read and write mode of operation by linking the timer to the interrupt mechanism and controlling polarity levels on the 1-wire interface.
PCT/EP2005/050594 2004-02-10 2005-02-10 Electronic device and methods of implementing the 1-wire protocol using an interrupt WO2005076144A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0402879A GB2411013B (en) 2004-02-10 2004-02-10 Electronic device and methods of interrupting a processor therein
GB0402879.1 2004-02-10

Publications (3)

Publication Number Publication Date
WO2005076144A2 WO2005076144A2 (en) 2005-08-18
WO2005076144A3 true WO2005076144A3 (en) 2005-11-24
WO2005076144B1 WO2005076144B1 (en) 2006-01-26

Family

ID=32011614

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2005/050594 WO2005076144A2 (en) 2004-02-10 2005-02-10 Electronic device and methods of implementing the 1-wire protocol using an interrupt

Country Status (2)

Country Link
GB (1) GB2411013B (en)
WO (1) WO2005076144A2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI398755B (en) * 2006-12-22 2013-06-11 Hon Hai Prec Ind Co Ltd Method for restoring an embedded system
CN101923525B (en) * 2010-08-11 2012-02-29 清华大学 General purpose in-out circuit with event capturing function
US8954628B2 (en) * 2012-06-05 2015-02-10 Htc Corporation Portable device and peripheral extension dock
US8930586B2 (en) 2013-04-03 2015-01-06 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Identification of electronic devices operating within a computing system
CN104460406B (en) * 2014-10-13 2017-04-26 深圳市江波龙电子有限公司 Single-line communication method and single chip microcomputer firmware updating method based on single-line communication
CN111858426B (en) * 2020-06-05 2022-03-15 深圳市共济科技股份有限公司 Electronic tag reading and writing system and method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5862354A (en) * 1996-03-05 1999-01-19 Dallas Semiconductor Corporation Universal asynchronous receiver/transmitter (UART) slave device containing an identifier for communication on a one-wire bus
US5978927A (en) * 1996-03-05 1999-11-02 Dallas Semiconductor Corporation Method and system for measuring a maximum and minimum response time of a plurality of devices on a data bus and adapting the timing of read and write time slots

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE520126C2 (en) * 1997-12-11 2003-05-27 Axis Ab I / O Processor and method for controlling peripherals
US6608571B1 (en) * 2001-05-16 2003-08-19 Globespanvirata, Inc. System and method for communicating over a one-wire bus

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5862354A (en) * 1996-03-05 1999-01-19 Dallas Semiconductor Corporation Universal asynchronous receiver/transmitter (UART) slave device containing an identifier for communication on a one-wire bus
US5978927A (en) * 1996-03-05 1999-11-02 Dallas Semiconductor Corporation Method and system for measuring a maximum and minimum response time of a plurality of devices on a data bus and adapting the timing of read and write time slots

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
ANONYMOUS: "1-wire communication with a Mircochip PICmicro Mircocontroller", DALLAS APPLICATION NOTE 2420, 8 September 2003 (2003-09-08), XP002341161, Retrieved from the Internet <URL:http://pdfserv.maxim-ic.com/en/an/AN2420.pdf> [retrieved on 20050818] *
DALLAS SEMICONDUCTOR, MAXIM: "APP Note 126: 1-wire communication through software", INTERNET ARTICLE, 6 July 2000 (2000-07-06), XP002341163, Retrieved from the Internet <URL:http://www.maxim-ic.com/appnotes.cfm/appnote_number/126> [retrieved on 20050817] *
DOWNS R: "Using 1-Wire I/O for distributed system monitoring", WESCON/98 ANAHEIM, CA, USA 15-17 SEPT. 1998, NEW YORK, NY, USA,IEEE, US, 15 September 1998 (1998-09-15), pages 161 - 168, XP010305393, ISBN: 0-7803-5078-2 *
TEXAS INSTRUMENTS: "HDQ Communication Basics for TI's Battery Monitor ICs", 31 May 2001 (2001-05-31), XP002341162, Retrieved from the Internet <URL:http://focus.ti.com/lit/an/slva101/slva101.pdf> [retrieved on 20050818] *

Also Published As

Publication number Publication date
WO2005076144A2 (en) 2005-08-18
GB2411013B (en) 2006-05-31
GB0402879D0 (en) 2004-03-17
GB2411013A (en) 2005-08-17

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