GB2400995A

GB2400995A - Linear amplifiers with distortion correction by current comparison

Info

Publication number: GB2400995A
Application number: GB0307204A
Authority: GB
Inventors: Gary Miller
Original assignee: Individual
Current assignee: Individual
Priority date: 2003-03-28
Filing date: 2003-03-28
Publication date: 2004-10-27
Anticipated expiration: 2023-03-28
Also published as: GB0307204D0; GB2400995B

Abstract

A linear amplifier arrangement for driving a load which operates by converting the input voltage drive into a current and comparing this current with a second current that is a linear function of the output voltage. The difference in these two currents is used to provide an additional drive to the input of the amplifier, pre-distorting the total drive to the amplifier. The resultant amplifier, having substantially increased linearity and bandwidth with very low open loop gain. A number of embodiments are presented using current conveyors to provide the functions of voltage to current conversion, current sampling and current amplification.

Description

LINEAR AMPLIFIERS.

This invention relates to non-linearity correction of an amplifier by the use of an additional circuit means which operates by converting the input voltage drive into a current and comparing this current with a second current that is a linear function of the output voltage. The difference in these two currents is used to provide an additional drive to the input of the amplifier, pre-distorting the total drive to the amplifier. The resultant amplifier having substantially improved linearity with less closed loop signal distortion and very low open loop gain. This invention avoids the use of feedback around a very high open loop gain amplifier as this method of distortion reduction has a number of drawbacks.

Figs 1, 2, 3 and 4 are circuit arrangements for prior art series and shunt amplifiers with voltage or current outputs, figs land 3 being shunt type and figs 2 and 4 being series types. These amplifiers have very high open loop gain so that under closed loop conditions the amplifiers exhibit acceptably low harmonic and intermodulation distortion. Designing the amplifiers to have high gain results in reduced bandwidth, typically for an operational amplifier, say a classic 741, a value of 1 8.9KHz BEFORE frequency compensation is added. Amplifiers will have multiple poles in their responses so in the case of a 741 an additional pole will be at approximately 328Khz with additional complex poles. If feedback is now applied to these amplifiers they will oscillate due to the combined phase shift of the multiple poles. Frequency compensation therefore must be applied so that the open-loop gain falls to unity at a frequency below the second most dominant pole for adequate phase margin. In the case of the 741 using the technique of pole spitting, the first pole moves to 5Hz and the second beyond the complex poles. Fig 5 illustrates the open loop frequency response with and without frequency compensation. It can be seen that this method of error reduction (i.e. distortion) by negative feedback around a high gain amplifier results in a trade off, higher frequency loop bandwidth is reduced so that lower frequency loop gain (40dB 20khz) is high enough to reduce errors internally generated in the amplifier.

Therefore the arrangement of feedback around a high gain amplifier has a number of problems. By taking greater gain in the amplifiers internal gain stages results in reduction of their pole frequencies, this in turn results in greater amounts of compensation to reduce the high frequency open loop gain for adequate phase margin. The result is a trade-off between reduced errors at the lower frequencies for higher errors at higher frequencies.

Also the addition of the frequency compensation capacitor, in the case of a 741, a value of 30pF, results in slew rate induced distortion. A further potential problem occurs with series feedback amplifiers, due to common mode gain non-linearity, which cannot be reduced by the overall negative feedback loop and can possibly be a limiting factor as regard to error reduction.

Fig 7 is a block diagram ofthe present invention. Fig 7 consists ofthe following, a load, this may be driven at one end as per fig 7 or can be bridged connected by the addition of a second drive amplifier.

an output amplifier, which provides voltage, current or power amplification and drives the load. This can be operated in all modes ie class A, B. D etc. This amplifier has the dominant distortion of the linear amplifier.

a first and second impedance means, these two means define the transfer gain of the said invention along with the, signal comparator, this has a 5 terminals. Terminal 1 is the input for the said linear amplifier. Terminal 2 is connected externally to the signal common of the said linear amplifier or provides a second input. Terminal 3 is a connection for the first impedance means, this first impedance being designated R1 in the prior art amplifiers. Terminal 4 provides a connection to the non-inverting of the output amplifier. Terminal 5 provides a connection to the inverting input of the output amplifier, an output signal sensing means which provides a output voltage to the second impedance means that is a function of the output signal. The output signal being in the form of a current drive or voltage drive to the load.

Fig 8 is based on fig 7 with the general output signal sensing means that consists of a short-circuit, as the output amplifier is a voltage output type and therefore the output signal drive to the load is a voltage drive and the output signal can be sensed directly by connecting the second impedance means to the load. Fig 7 also has a single ended input. Fig 9 is based on fig 7 with the output amplifier being a current output type.

A number of embodiments are presented, of all of which have a common mode of operation that provides an drive current to the inverting input of the output amplifier. This drive current is used to pre-distort the total drive signal to the output amplifier so resulting in a non-distorted output signal at the load. The input voltage is converted into a current by at least one resistor or in the general case an impedance, and is compared to an additional current whose magnitude is the same as the current in the first impedance means. The difference is the drive current to the inverting input of the output amplifier.

First and fifth embodiments according to the invention (see figures 7&8) In the first and fifth embodiments terminals I and 3 are connected together by internal links and 4 to 2. Input signal drive is to terminal 2 of the first impedance means, with the non-inverting terminal of the output amplifier grounded. In this mode the current in the first impedance means is sensed indirectly by terminals 3 and 5 of the signal comparator, the resultant voltage drop across the first impedance means being converted into a current by at least one internal impedance. If in the case of the first impedance means being a resistor then the internal impedance would also be a resistor to give a frequency independent ratio. This sampled current is compared to a second current that is a function of the input voltage present at terminal 1 of the signal comparator, the voltage to current conversion being achieved by at least one internal impedance within the signal comparator. The difference between these two currents resulting in a signal current from terminal 5 ofthe signal comparator, which pre- distorts the drive to the output amplifier. The first embodiment being a voltage output amplifier.

Second and sixth embodiments according to the invention (see figures 7&8! In the second and sixth embodiments terminals 1 to 4 are connected by internal links also terminals 3 to 2. Input signal drive is to the noninverting input of the output amplifier. In this mode the current in the first impedance means is sensed indirectly by terminals 3 and 5 of the signal comparator, the resultant voltage drop across the first impedance means being converted into a current by at least one internal impedance. If in the case ofthe first impedance means being a resistor then the internal impedance would also be a resistor to give a frequency independent ratio.

This sampled current is compared to a second current that is a function of the input voltage present at terminal 1 of the signal comparator, the voltage to current conversion being achieved by at least one internal impedance within the signal comparator. The difference between these two currents resulting in a signal current from terminal 5 ofthe signal comparator, which pre-distorts the drive to the output amplifier. The second embodiment being a voltage output amplifier, terminal 2 being grounded.

Third and seventh embodiments according to the invention (see figures 7&8! In the third and seventh embodiments terminals 4 to 2 are connected by an internal link. Input signal drive is to terminal 2 of the first impedance means, with the non-inverting terminal of the output amplifier grounded.

In this mode of operation the current in the first impedance means is sensed directly by terminal 3 of the signal comparator. Ideally the impedance looking into terminal 3 is zero, resulting in an overall gain for the linear amplifier set by the first and second impedance means and the internal circuitry within the signal comparator. If it is not zero it can be taken into account by the adjustment in the value of the first impedance.

The current flowing into terminal 3 is compared to a second current that is a function of the input voltage present at terminal 1 of the signal comparator, the voltage to current conversion being achieved by at least one internal impedance within the signal comparator. The difference between these two currents resulting in a signal current from terminal 5 of the signal comparator, which pre-distorts the drive to the output amplifier.

The third embodiment being a voltage output amplifier.

Fourth and eighth embodiments according to the invention (see figures 7&8! In the fourth and eight embodiments terminals 1 to 4 are connected by an internal link. Input signal drive is to the non-inverting input ofthe output amplifier. In this mode of operation the current in the first impedance means is sensed directly by terminal 3 ofthe signal comparator. Ideally the impedance looking into terminal 3 is zero, resulting in an overall gain for the linear amplifier set by the first and second impedance means and the internal circuitry within the signal comparator. If it is not zero it can be taken into account by the adjustment in the value of the first impedance. The current flowing into terminal 3 is compared to a second current that is a function of the input voltage present at terminal 1 of the signal comparator, the voltage to current conversion being achieved by at least one internal impedance within the signal comparator. The difference between these two currents resulting in a signal current from terminal 5 of the signal comparator, which pre-distorts the drive to the output amplifier.

The fourth embodiment being a voltage output amplifier.

Ninth and tenth embodiments according to the invention In the ninth and tenth embodiments terminals 1 to 3 are connected by an internal link. The linear amplifier responds to the differential signal voltage present between terminals 1 and 2 of the signal comparator. The ninth embodiment being a voltage output amplifier and the tenth embodiment being a current output amplifier.

All ten embodiments correct for signal distortion, noise etc generated in the amplifier by providing a correction signal current from terminal S of the signal comparator. This correction signal pre-distorts the drive to the output amplifier at its inverting input. The input signal voltage present between terminal 1 and 2 of the signal comparator is converted into a current by an internal impedance or resistance. This is summed directly with the current in the first impedance means, or a current that is a linear function of the current in the first impedance means. The resultant difference in current being the correction current. This invention has a number of improved amplifier arrangements that are electronic implementations ofthe ten embodiments. They correct for signal distortion and noise generated by the output amplifier without the use of very high open loop gain. They can connected in series, shunt or differential at their inputs and provide a voltage or current output.

According to the present invention there is provided a linear amplifier comprlsmg: an output amplifier having an inverting input terminal and a non-inverting input terminal and an output terminal for delivering output signal drive to a load; an output signal sensing means with first input terminal and first and second output terminals; a signal comparator means with first, second, third, fourth and fifth terminals; a first impedance means with first and second terminals with the first terminal coupled to the inverting input of the said output amplifier with the second terminal coupled to the third terminal of the said signal comparator means; a second impedance means with first and second terminals with its first terminal coupled to the first output terminal ofthe said output signal sensing means with the second terminal coupled to the inverting input terminal of the said output amplifier; the first output terminal of the said output signal sensing means providing a voltage that is a function ofthe said output signal drive, the first and second terminals of the said signal comparator means forming the inputs of the said linear amplifier, the forth terminal of the said signal comparator coupled to the non-inverting input of the said output amplifier, the fifth terminal of the said signal comparator being coupled to the inverting input of the said output amplifier, the output of the said output amplifier being coupled to the input terminal of the said output signal sensing means, the second output terminal of the said output signal sensing means being coupled to the said load, the action of the said signal comparator means being, to compare an error current to a current that is a function of the input voltage present between the first terminal and second terminal of the said signal comparator, the difference in these two currents being an output current coupled to the inverting input of the said output amplifier from the fifth terminal ofthe said signal comparator, with the said error current being a function of the current in the said first impedance means.

For the linear amplifier to function correctly a number of circuit conditions must be met, these three conditions are as follows.

(1)A positive' current feedback loop A positive, current feedback loop must be formed. The path ofthe loop referring to fig 7,8 & 9 is a combination of a current gain path and a current attenuation path. The input to the current gain path is terminal 1 of the first impedance means. The output of the current gain path is terminal 5 ofthe signal comparator. The input to the current attenuation path is the node comprising terminal 2 of the second impedance means, terminal 1 of the first impedance means and the inverting input of the output amplifier. The output of the current attenuation path is the coupling from the above node to terminal 1 of the first impedance means.

(2) A negative feedback loop A negative feedback loop is required, the path being from the output of the output amplifier, through the second impedance means and back to the inverting input ofthe output amplifier.

(3) A balanced condition The balanced condition for the linear amplifier occurs when the magnitude of gain for the above current gain path is equal to the magnitude of one plus the value of the first impedance means divided by the value ofthe second impedance means. Also the phase shift ofthe current gain path must equal the phase shift of the attenuation path. In the case of the first and second impedance means being resistors, the phase shift of the current gain path is zero, therefore the current gain path is non-inverting, a positive feedback loop. Under this balanced condition all of the error signals generated in or coupled internally to the output amplifier are eliminated from the output signal driving the load. Figs 10 to 15 are block diagrams that are based on figs 7, 8 and 9. These expand the signal comparator and show internal means for sampling the current in the first impedance means (S 1) and the comparison amplifier (Al) to generate the correction current. Fig 10 being a shunt, voltage output type, Fig 11 being a series, voltage output type, fig 12 being a shunt, current output type, fig 13 being a series, current output type, fig 14 being a series, voltage output type and fig 15 being a series, current output type.

These block diagrams can be used to represent an appropriate embodiment according to the following table.

Embodiment 1 Fig 10 Embodiment 2 Fig l] Embodiment 3 Fig 10 Embodiment 4 Fig 14 Embodiment 5 Fig 12 Embodiment 6 Fig 13 Embodiment 7 Fig 12 Embodiment 8 Fig 15 Analysis of Fies 10 & 12 The linear amplifier consist of an output amplifier, A2, which drives the load with substantial power drive, such that the open loop distortion (without any form of negative feedback) is higher than required for the given application. For example a power amplifier for audio applications would require feedback to reduce distortion to inaudible levels.

Additional means are also provided, these are S1 and A1. S1 is a sampling means that samples the input current, in the case of the series input amplifier, and samples the feedback current in the case of the shunt feedback amplifier. The sample being a linear current, which is coupled to the A1 means. This current can be greater or smaller than the said sampled current. Therefore Sl=Is/Il, where Is and It are instantaneous currents, It is the current in the first impedance means and Is is the output current of the sampler. The means A1 is an arrangement that compares the said sample current with an additional current that is a function of the input voltage. Therefore a resistive means is provided within the A1 means to convert the input voltage into a current. The difference between the said two currents is then coupled to the amplifier. The sampling means may also have one or more resistive elements to define its current transfer gain Is/I 1. In the case of the current output linear amplifiers an additional resistive means RLF is provided to define the output current to = vd / RLF, where vd is the differential input voltage of A2 and to is the output current. The two circuit arrangements therefore have additional circuit means, S 1 and A 1 which correct for distortion and other errors generated in A2 by pre-distorting the input drive to A2 inverting input.

This operation of the linear amplifier can best be understood by considering the action of the prior art shunt amplifier.

Here the input voltage sets up an input current that is given by: / ON iRl F'n Fe R. Where Ve is the voltage at the inverting input, which is finite and is a function of the output voltage and the voltage gain of A2, ie He To Aa Therefore: i = V - V In 0

A A2 R.

The current therefore is a measure of the gain of A2. If A2 is infinite then i = Vet n Rl In practice A2 is finite so as the instantaneous gain reduces the current in Rl increases as the gain reduces so the current through increases R1. The current in Rl is proportional to the instantaneous pain of A2.

Therefore the current in Rl, if sensed by some additional circuit means, can be compared to an additional current that is a function of the input voltage. The difference in current can be applied to the A2 amplifiers \ inverting terminal to pre-distort the input voltage such that it compensates for the finite and non-linear gain of A2.

For Fig 10 the sampling means S1 samples the input current flowing through R1 and couples this to first amplifying means A1. The current is compared to a second current that is a function of the input voltage and the difference is coupled to the second amplifying means A2 that drives the load. For the linear amplifier to function correctly a number of conditions must be met.

The first is the current loop from the output ofthe means A1, to the junction of R2 and the sampling means S. 1, through the sampler to the input ofthe A1 means is non-invertinu. Assuming the output current of Al increases, so the voltage at the inverting input of A2 will increase. For any given input voltage, the current from the output ofthe current sampler will reduce. This in turn will increase the output current of Al, a positive current feedback loop results.

The second condition is that the output amplifier A2 has feedback applied by R2 to its inverting input, an inverting voltage feedback loop results, the loop being through A2 to the output, and back to the inverting input via R2.

The third condition is that product of the sampling ratio of S 1 and the current gain of the amplifier Alis stable and fixed at a value that provides a balanced condition within the arrangement. The balanced condition then provides maximum rejection of errors originating in the output amplifier A2.

The transfer function for fig 10 is given by: _AV=A, -S,A, + 1 R3 R. R. 1 ( 1- SIAI+l)+ 1 D R2 R. R1 R2 Where R1 is the input resistor as per the prior art, coupling the input signal voltage to the inverting input of A2, R3is a resistive means which is within the Al amplifying means and converts the input voltage into a current.

Where A1=IF/(IR3-S1 Irl)

N

D is given by: D=R2 (1 +Rs)-RS

L

R2 A2 + Rs Where Rs is the output resistance of the amplifier A2 and RL is the load resistance.

In general S l, Al and A2 are a function of signal frequency and Rs, RL are complex impedances.

Now the purpose of the new arrangements is to eliminate the error contribution of A2 on the output signal. Looking at the denominator of the transfer function it can be seen that if: ( 1- S,A + 1 = 0 Then D, which is a function of AS and its output resistance, is eliminated from the transfer equation. i.e.

S,A, = l + Rl R2 The above balanced condition therefore eliminates A2, and its output resistance from the transfer equation. It should also be noted that the value of R3 does not effect the balanced condition (it will effect the overall transfer gain).

Substituting some values for Sl, Al, Rl and R2.

Rl = lKQ R2= 50KQ If S l is unity current gain then A l current gain = l. 02.

Therefore the overall gain is given by: AV=A, -S,A, + 1

_ _

R3 R. R. l R2 Rearranging gives: -Av =A, ( R2 -SIRS) +R2 R3 R. R1 Setting the value of R3 = R1, with S 1 = unity gain then the overall gain is given by: -A = R2 R. The current gain of A1 only needs to be 1.02, or an overall gain of -50.

If the overall gain is set to -1 then R1 = R2, and the gain of A1 is 2.

Therefore the gain range of Al oftypically 1.02 to 2 will ensure the maximum bandwidth for A1.

The gain of A2 is determined by the required stability gain margin of the amplifier. For a gain margin of lOdB and overall gain of-50, the gain of A2 would be 110.27. This new amplifier arrangement therefore provides the lowest possible signal distortion, with low internal gain requirements.

The low gains will maximise the bandwidths of A1 and A2. The output amplifier only needs a small increase in gain above the overall closed loop gain to provide sufficient gain margin for the linear amplifier. This reduced gain will maximise the bandwidth of the output amplifier and also reduce the open loop non-linear ofthe output amplifier due to increased series current feedback within each stage making up the output amplifier. The output amplifier will also have a minimum number of gain stages due to the very low gain requirements. A1 again only needs a \ maximum current gain of 2, in the case of a unity gain buffer, so this will maximise bandwidth. Al can be operated in a current mode, with the best active element to do this being a current conveyor. Current conveyors make best use of active devices by operating them in a current mode ie the signal is in the form of a current with maximum voltage swings being delta vbe's, typically lOOmV, slew rate limiting is not a problem. No frequency compensation is required within the output amplifier, stability can be controlled by a reduction of bandwidth within the Al amplifier. In general the input offset voltage of the output amplifier will not saturate the output of the linear amplifier for a reasonable balanced output amplifier. Therefore during linear amplifier development, production test or fault finding the linear amplifier can be operated open loop if required as an aid in finding the faulty area. The loop opened at the output ofthe Al amplifier.

The transfer function of the arrangement is generally a function of the complex frequency: T(s) = output Input Therefore the balanced equation is: S,A,(S) = 1 + R. In the steady-state, s = jco e: S,A, (j()) = 1 + Rl ( ) R2 1 For the balance to hold over the required frequency range the magnitude and phase of Sl.Al must match that of I + Rl/R2. With Rl and R2 in the simplest of cases being both purely resistive (no reactive components) then: | S,A | = 1 + R} R2 and SEA, = /0 S 1 and Al must have sufficient bandwidth to ensure that over the frequency range of interest the magnitude and phase meets the above criteria within acceptable limits.

In general poles especially within A l will cause the gain to drop off and unbalance the equation due to magnitude gain drop and increased phase shift.

Analysis of Fins 11 & 13 The linear amplifier for figs l l and 13 is operated in a non-inverting mode, with the input signal drive to the noninverting input of the output amplifier. Operation is the same as figs 10 and 12 but in this case, S 1 now samples the feedback current in R1. Fig 13 is the current output type and has RLF added to sense the output current. The transfer equation is: Av(s) = RLA2AKXR2+AIRLR2 {A2R - 1 l R SKY R3KY (RS R2 J R2KX RL {A2B - 1 l KYL RS R2 \ Where: KX =_+ 1 - A 1_ R. R2 R Ky = 1 + _ + R RS R2 A2A is the non-inverting gain of A2 A2B is the inverting gain of A2 R3 is an internal resistance within Al that converts the input voltage into a current.

A1 is the differential current gain within Al, the difference being the current in R3 and the current in R1.

The output current of A1 being: lout = (Vin/R3)Al-IRlSIA1 Where S 1 is the ratio of current in R1 to the current coupled to A1 i.e. S1 = if/IRl.

The transfer function can be reduced by setting Kx to zero i.e. KX = 1 + 1 - A, = 0 R. R2 R. e.

A, = 1 + R. R2 Then AV(s) = AIRY R3 Now A, = 1 +Rl R2 Therefore V( ) Rim R2 R3 If R3=R1 AV(S)= 1 + R2 R. Analysis of fins 14 and 15 Fig 14 is a series, voltage output type and fig 15 is a series, current output type. A new means is provided, SA, which combines the functions of current sampling and comparator to produce the correcting current to the inverting input of A2. This is possible because the feedback current that flows through R1 can be directly compared to the input current (that is a function ofthe input voltage) by ensuring that the input to SA seen by R1 is a virtual earth or has some fixed input resistance. Fig 14 therefore shows the basic arrangement. Fig 15 is the current output type with RLF added to sense the output current.

The transfer function for fig 14 is given by: Av(S) = RLA2AKXR2+ARLR2 IA2B - 1 RsKy R3Ky RS R2.

R2KX- RL A2B 1 Ky RS R2 Where: Ky = 1 +_ + R RS R2 KX =_+ 1 - A,_ Rl R2 R. A2A is the non-inverting gain of A2 A2B is the inverting gain of A2 R3 is an internal resistance within SA that converts the input voltage into a current Al is the differential current gain within SA, the difference being the current in R3 and the current in R1.

The output current of SA being: tout = (Vin/R3)Al-IRlA1 The transfer function can be reduced by setting Kx to zero i.e., Kx= 1 + 1 -Al =0 R. R2 R. ie A, = 1 +R, R2 The balanced condition Then: AVIS)= A,R2 R3 Now: A, = 1 +R, R2 Therefore: V( ) 2 R3 If R3=Rl: AV(S)= 1 + R2 R. Therefore the transfer function is independent of the gain of A3 under the balanced condition. If the input resistance looking into the input of SA that is coupled to R1 is not zero, then in the above transfer equation the value of Rl = Rt, with Rt = Rl + Rin, where Rin is the input resistance. It also possible for the input, (Vin), to SA to be attenuated. In this case the transfer equation is modified.

Embodiments with a third impedance from the inverting input of the output amplifier to signal common The linear amplifier of figs 7, 8 and 9 can be modified to include a impedance connected from the inverting input of the output amplifier to signal ground. This resistor can be added to figs 13 and 14 and thus modify the transfer gain and also the balanced equation. The balanced equation is now l+Zl/Z2+Zl/Za = A1, where Za is the additional resistor. The gain ofthe amplifier is Vo/Vi = 1 + Z2/Za or lo/Vi = (1 + Z2/Za)/ZLF. A1 is the current gain of A1. The transfer function is: AV(S)= RTA2AKXR2+ (1-AI)RLR2 A2B - 1

_ RSKY RTKY RS R2 R2KX RL /A2B - 1 KY RS R2 Current conveyor implementations

of the linear amplifier Figs 16 to 70 are current conveyor implementations ofthe embodiments of figs 10 to 15. The current conveyor is an ideal active element for implementing the linear amplifier and provides the functions of current sampler and current amplifier. The conveyor implementations provide voltage or current output drive to the load and operate with series or shunt feedback. For each of the circuit arrangements terminations numbered 1 to 5 are present. These correspond with the numbering of the basic block diagrams of the linear amplifier in figs 10 to l 5. Therefore the signal comparator means for the conveyor implementations can clearly be seen for each circuit, with the conveyor circuitry contained within the signal comparator means. In the basic block diagrams in figs 10 to 15, the signal comparator and other means correspond with figs 7, 8, and 9. It can be seen that a large number of possible solutions exist for practical hardware using CCI+, CCT-, CCII+ or CCII- current conveyors. The properties of the four types of conveyors are as follows.

All the conveyors have a Y input, a X input and a Y output. In all cases the output Y has infinite output impedance, so it is a controlled current source. The X input has zero input impedance and the Y input has an infinite input impedance for the CCl1 types and zero for the CI types. CCI+

Ix= Iz, Vx= Vy, Iy= Ix

CCI

Ix= -Iz, Vx= Vy, Iy=lx CCIl+ Ix= Iz, Vx = Vy, Iy = 0

CCII

Ix = Iz, Vx= Vy, Iy = 0 The "standard" conveyor can be seen to have a unity current gain from its X input to its Y output. However it is possible to have a current conveyor with a current gain greater than unity, therefore these types are used in some arrangements.

A number of arrangements will be detailed to help with the general understanding of operation of all the conveyor implementations.

Figs 16 to 46 are linear amplifier arrangements that are represented in their basic form in figs 10 to 13. Arrangements that couple the input signal to the inverting input of the output amplifier being represented by figs 10 and 12 and arrangements that couple Vin to the non-inverting input of the output amplifier being represented by figs 11 or 13. Figs 47 to 70 are linear amplifier arrangements that are represented in their basic form in figs 12 and 14. However the transfer equation detailed on page 13 onwards for fig 14 is not applicable for figs 63 and 65, also for figs 53, 54, 61 and 62 the equation would have to be modified to include the effects of input voltage attenuation of the resistors R4 and R5.

Fie 16 This is a shunt feedback voltage output arrangement. The sampler is comprised of R1, R3 and the CCII-. The sampler operates by coupling an output current that is set by the ratio of R1 and R4, this is because the voltage at the X output follows that of the Y input. Therefore with Rl=R4, the sampled current equals the current through R1. The second conveyor, a CCII+ produces the correction current for the arrangement.

Now the level of X current depends on the difference between the input voltage divided by the value of R4 and the sampled current. Therefore assuming a positive instantaneous input voltage, a current will flow out of the current sampler. Now the current flowing out of the CCII+ is Vin divided by the value of R4 minus the sample current, the sampled current bucks out the current due to the input voltage, i.e. the output of CCII+ is the difference and is a measure of the gain error A3. The error current flows out of Al and pre-distorts the drive to the output amplifier. In practice with the current gain of the two conveyors being unity, R4 would be adjusted to give the required balanced condition. For example if R2=50K and R1=lK then R4 = 980.39Ohms, ie a ratio 1.02. A point to note for this arrangement is that the input voltage drive is assumed to have zero output impedance. If this is not the case then a voltage buffer is required at the input of the arrangement or R1 reduced by a value equal to the source resistance. The shunt arrangements do not suffer from this limitation. The balance equation being R1/R4 = I + R1/R2, with a gain of -R1/R2 if R3 = R1.

Fin 17 This is a voltage output series amplifier. Operation is the same as fig 16 but with the signal drive to the output amplifier and R1, R4 are grounded, with the conveyors swapped in sign to give the current positive feedback loop. With CC 1 and CC2 having unity current gain, the balanced equation is R1/R4 = l+R1/R2. The gain equals l+R2/R1 if R3 = Rl. Fia31

This is a current output version of fig 16. This arrangement differs from fig 16 by having an additional resistor RLF which senses the output current. The action of the arrangement will give a voltage across RLF equal to-R2/R1 The output current is equal to the current through RLF, therefore lout IVin = R2RLF/R1.

Fin 32 Fig 64 operates as per fig 17 but in this case the output voltage across RLF is dependent on the output current so the transconductance for the arrangement is Io/Vin = (l+R2/R1)/RLF if R3 = R1.

Fia 47 This shunt voltage output type is one of the simplest of arrangements.

Here the first conveyor samples directly the current in R1 and compares this current with the current from the second conveyor, this current being set by the value of R3. The current gain required from CC 1 is greater than unity to give the balanced condition, and is equal to l+ R1/R2. R3 would typically be equal to R1. The gain is 1 +R2fRl if R3 = R1.

Fin 51 This arrangement is based on fig 47 but with the CC 1 being a unity current gain type of opposite sign due to the sample drive being coupled to the Y input of CC1. Here the sampling ratio ofthe current in R1 is set by the ratio of R4 and R5, with R4/R5=l+((Rl+R4)/R2) the balanced condition is met. The gain is 1 + R2/R1 if R3 = Rl.

Fig 53 In this arrangement the conveyors can both have unity current gain and also be inverting types. These two factors can help to reduce the inherent distortion of the current conveyors due to fewer active stages in the Z output path. The balanced equation is R6/R3 = l+((R6+R1)/R2) Fin 63 This arrangement is the simplest using only one conveyor and one additional resistor Ra. CC 1 samples directly the current in R1 and via its X input and compares this with the input voltage. CC 1 would typically have a current gain of x2. The balanced equation is given by l+ R1/R2+R1/Ra= iZ/iX. The gain is Vo/Vin= l+R1/Ra. With Ra = infinite in value the gain is unity for any values of Rl or R2.

An Audio Power Amplifier Example Fig 75 is one embodiment of the linear amplifier based on the use of current conveyors, the amplifier being an audio frequency power amplifier used to drive a loudspeaker load. This design is based on the embodiment of fig 53. The semi-block diagram is based on a SIMETRIX computer simulation, the results off which are detailed in figs 72 to 85.

Ql to Q6 are low cost devices, with Q1 and Q2 buffering the voltage amplifier. Th voltage amplifier (not detailed) provides a differential voltage gain of x125 and has a differential DC output voltage that biases Q3 to Q6. This voltage is a function of the temperature of Q4 and Q6. R8 and L l are used to partially cancel the effect of a reactive load that might be present at the output. The two conveyors (not detailed) provide the correction current. These are class II inverting types that are designed to give very low signal distortion, low and stable DC offsets with temperature changes and provide sufficient output current. The conveyors are not based on the standard design for a conveyor that uses supply current sensing of an op-amp, but are open loop designs that have unity voltage gain and unity current gain. The simulations for the conveyors use data from a complementary dielectric process, which provides transistor ft's of 300Mhz, the resultant conveyors having bandwidths of over lOOMhz.

Fig 72 is a plot of the output spectrum of the amplifier with an output of 20V peak lKhz. Q1 gate is grounded so the amplifier is open loop with an approximate gain given by the voltage amplifier. It can be seen that the second harmonic distortion is 0.155% and the third is 0.275%.

Fig 73 is a plot with feedback provided by R2, but without the correction provided by CC1 and CC2. Here the distortion is reduced as expected, the second harmonic being 0.025% and the third 0.056%. Fig 74 is a plot with the correction connected, the second harmonic being 0.000055% and the third being 0.0004%.

Fig 75 plots the result of a Monte Carlo analysis of the amplifier at 1 Khz, varying the values of the loop gain setting resistors, R1 to R4 and the input attenuating resistors R10 and R11. It can be seen that the amplifier is insensitive to resistor change, a resistor long-term drift of + or - 0.25 % the second harmonic degrades to 0.0001% and the second to 0.00045%.

Figs 76 to 78 are the same as figs 72 to 74 but with the frequency changed to lOKhz. Fig 76 indicates a second harmonic distortion of 0.19% and a third of 0.33%. Fig 77 gives a result for the second harmonic of 0.03% and the third of 0.0685%. Fig 78 results in a second harmonic of O.00061% and a third harmonic of 0.00387%.

Fig 79 plots the result of a Monte Carlo analysis of the output spectrum with a lOKhz input. Here, in addition to the resistors matching, the saturation current ofthe transistors making up the two conveyors has a match of + or - 3% and a beta match of + or - 3%. Results again show negligible change in second and third harmonic levels.

Fig 80 and fig 81 are plots of the output square wave response of the amplifier with an 80hm load in parallel load 330nF. Response is fast with a rise time of + or - 9.5V/usec, limited by the output network, + or - 31 V/usec at the R6, R7 junction, the amplifier is not slew limiting.

Fig 82 is a plot of the frequency response of the amplifier showing a gain of +30.5dB, dropping to -3dB, 150Khz at the load or 540Khz at the junction of R6 and R7.

Fig 83 plots the result of a Monte Carlo analysis of the output spectrum with a lKhz input. Here, in addition to the resistors mismatching, the saturation current of the transistors making up the two conveyors have a match of + or - 3% and a beta match of + or - 3%. Results again show a change in second and third harmonic levels up to 0.00035% and 0.0005%. This plot combines the long-term drift in the gain setting resistors and an initial mismatch in the conveyors transistors. In a practical amplifier the two conveyors would be integrated so transistor mismatches could be trimmed out so improving on the initial and long- terrn distortion drift, to values more like fig 75. It will be noted that the effects of resistor mismatch are negligible at lOKHz as compared to lKhz. This is due to the lKhz input being well below the first pole frequency of the CC 1 and CC2 so variation in the gain of the positive current feedback loop results in a change in output distortion level.

Whereas inputs of 1 OKhz and frequencies above are situated on the slope of reducing gain and phase accuracy in the unity gain current feedback loop, these frequencies being not effected by the change in low frequency gain accuracy in the positive current feedback loop.

Fig 84 is a plot ofthe various current gains within the linear amplifier.

The Al current gain input is the current in R11 and an output, which is the current output of CC 1. The A2 current gain path has an input which is the current entering the junction of R11, R2 and the gate of Q1 and an output which is the current in R11. AS is the overall loop gain. Fig 85 is a plot of the current gain phase shifts. Comparing Fig 84 to fig 85 it can be seen that up to about 500Khz the loop phase shift is O degrees. Over this range of frequencies the gain magnitude is -13dB. Therefore the amplifier has a gain margin of at least - 13dB, this being with a load capacitance of 330nF. The loop gain of the amplifier never reaches OdB or greater so the phase margin can not be defined, phase margin being the margin of phase shift less than 180 degrees when the loop gain is OdB.

Stability is thus defined by the gain margin, the value of which is set by the gain of the voltage amplifier. Increasing the gain of the voltage amplifier increases the attenuation of the A2 gain path, in this case 13.8dB at zero frequency. This amplifier exhibits a mild loop gain peaking at around lMhz, which could be reduced to a flat loop gain before roll off by increasing the value of the compensation capacitor.

This example of the linear amplifier therefore provides a linear drive to a load in this case a loudspeaker, at very low distortion levels with wide bandwidth, high speed and at low cost. In general this invention has applications from DC to the Ghz range, with bandwidths far less limited by the speed (i.e. transition frequencies) of the active devices making up the linear amplifier. This invention is well suited to integrated circuit construction, with all the inherent advantages of IC's matching well the requirements of this invention, these being closely matched and trimmable components that are both stable and /or predictable with temperature and stable with time. The linear amplifier requires stable and accurate resistors to define the various gains within the conveyor based embodiments, therefore thin film resistors would be most likely used.

These are trimmable and are both stable with temperature and time. In general the signal comparator means could be integrated, with the output amplifier constructed using other means i.e., thick film, discrete devices etc. Other application however would be better served by integrating the complete linear amplifier.

Claims

1 According to the present invention there is provided a linear amplifier comprising: an output amplifier having an inverting input terminal and a non-inverting input terminal and an output terminal for delivering output signal drive to a load; an output signal sensing means with first input terminal and first and second output terminals; a signal comparator means with first, second, third, forth and fifth terminals; a first impedance means with first and second terminals with the first terminal coupled to the inverting input of the said output amplifier with the second terminal coupled to the third terminal ofthe said signal comparator means; a second impedance means with first and second terminals with its first terminal coupled to the first output terminal of the said output signal sensing means with the second terminal coupled to the inverting input terminal of the said output amplifier; the first output terminal of the said output signal sensing means providing a voltage that is a function of the said output signal drive, the first and second terminals ofthe said signal comparator means forming the inputs of the said linear amplifier, the forth terminal of the said signal comparator coupled to the non-inverting input of the said output amplifier, the fifth terminal of the said signal comparator being coupled to the inverting input of the said output amplifier, the output of the said output amplifier being coupled to the input terminal of the said output signal sensing means, the second output terminal of the said output signal sensing means being coupled to the said load, the action of the said signal comparator means being to compare an error current to a current that is a function of the input voltage present between the first terminal and second terminal ofthe said signal comparator, the difference in these two currents being an output current coupled to the inverting input of the said output amplifier from the fifth terminal of the said signal comparator, with the said error current being a function of the current in the said first impedance means.

2 A linear amplifier as claimed in claim 1 wherein the said output signal drive is from source that has an output impedance that is relatively high compared to the load impedance and thus can be described a output signal current source, with the output signal being in the form of a current.

3 A linear amplifier as claimed in claim 1 wherein the said output signal drive is from a source that has an output impedance that is relatively low compared to the load impedance and thus can be described as a output signal voltage source, with the output signal being in the form of a voltage.

4 A linear amplifier as claimed in claim 2 wherein the said output signal sensing means provides an output voltage that is a function ofthe output current ofthe said output signal current source.

A linear amplifier as claimed in claim 3 wherein the output signal sensing means is comprised a of short circuit between its input and both outputs.

6 A linear amplifier as claimed in claims 4 and 5 wherein the said signal comparator has internal first and second links, with the first said link short circuiting terminals 1 to 3, the said second link short circuiting terminals 4 to 2, the said error current being a function of the voltage drop between terminals 3 and 5 of the said signal comparator, terminal 2 of the said signal comparator being coupled to the signal common of the said linear amplifier.

7 A linear amplifier as claimed in claims 4 and 5 wherein the said signal comparator has internal first and second links, with the said first link short circuiting terminals 3 to 2 of the said signal comparator, the said second link short-circuiting terminals 1 to 4 ofthe said signal comparator, the said error current being a function of the voltage drop between terminals 3 and 5 of the said signal comparator, terminal 2 of the said signal comparator being coupled to the signal common of the said linear amplifier.

8 A linear amplifier as claimed in claims 4 and 5 wherein the said signal comparator has an internal first link, with the said first link shortcircuiting terminals 4 to 2 of the said signal comparator, the said error current being the current into terminal 3 of the said signal comparator means, terminal 2 of the said signal comparator being coupled to the signal common of the said linear amplifier.

9 A linear amplifier as claimed in claims 4 and 5 wherein the said signal comparator has an internal first link, with the said first link shortcircuiting terminals 1 to 4 of the said signal comparator, the said error current being the current into terminal 3 of the said signal comparator means, terminal 2 of the said signal comparator being coupled to the signal common of the said linear amplifier.

A linear amplifier as claimed in claims 4 and 5 wherein the said signal comparator has an internal link, the said internal link short-circuiting terminals 1 to 3 ofthe said signal comparator.

11 A linear amplifier as claimed in claim 6 wherein a non-inverting, positive current feedback loop is formed comprising a current gain path and a current attenuation path, the said current gain path whose input is terminal 1 ofthe said first impedance means and whose output is terminal 5 of the said signal comparator with the gain being obtained within the said signal comparator, the said current attenuation path whose input is the node comprising terminal 2 of the said second impedance means, terminal 1 of the said first impedance means and the inverting input of the said output amplifier, and whose output is the coupling from the said node to terminal 1 of the said first impedance means.

12 A linear amplifier as claimed in claim 7 wherein a non-inverting, positive current feedback loop is formed comprising a current gain path and a current attenuation path, the said current gain path whose input is terminal 1 of the said first impedance means and whose output is terminal 5 of the said signal comparator with the gain being obtained within the said signal comparator, the said current attenuation path whose input is the node comprising terminal 2 of the said second impedance means with terminal 1 of the said first impedance means and the inverting input ofthe said output amplifier, and whose output is the coupling from the said node to terminal 1 of the said first impedance means.

13 A linear amplifier as claimed in claim 8 wherein a non-inverting, positive current feedback loop is formed comprising a current gain path and a current attenuation path, the said current gain path whose input is terminal 1 ofthe said first impedance means and whose output is terminal 5 of the said signal comparator with the gain being obtained within the said signal comparator, the said current attenuation path whose input is the node comprising terminal 2 ofthe said second impedance means with terminal I of the said first impedance means and the inverting input of the said output amplifier, and whose output is the coupling from the said node to terminal 1 of the said first impedance means.

14 A linear amplifier as claimed in claim 9 wherein a non-inverting, positive current feedback loop is formed comprising a current gain path and a current attenuation path, the said current gain path whose input is terminal I of the said first impedance means and whose output is terminal 5 of the said signal comparator with the gain being obtained within the said signal comparator, the said current attenuation path whose input is the node comprising terminal 2 of the said second impedance means with terminal 1 of the said first impedance means and the inverting input of the said output amplifier, and whose output is the coupling from the said node to terminal l of the said first impedance means.

A linear amplifier as claimed in claim 10 wherein a non-inverting, positive current feedback loop is formed comprising a current gain path and a current attenuation path, the said current gain path whose input is terminal l of the said first impedance means and whose output is terminal 5 ofthe said signal comparator with the gain being obtained within the said signal comparator, the said current attenuation path whose input is the node comprising terminal 2 of the said second impedance means with terminal 1 of the said first impedance means and the inverting input of the said output amplifier, and whose output is the coupling from the said node to terminal l of the said first impedance means.

16 A linear amplifier as claimed in claim 11 wherein the said signal gain path has a magnitude of gain equal to the gain magnitude of l + Z1/Z2, the said non-inverting positive current feedback loop having zero loop phase shift.

17 A linear amplifier as claimed in claim 12 wherein the said signal gain path has a magnitude of gain equal to the gain magnitude of l + Z l /Z2, the said non-inverting positive current feedback loop having zero loop phase shift.

18 A linear amplifier as claimed in claim 13 wherein the said signal gain path has a magnitude of gain equal to the gain magnitude of l + Zl/Z2, the said non-inverting positive current feedback loop having zero loop phase shift.

19 A linear amplifier as claimed in claim 14 wherein the said signal gain path has a magnitude of gain equal to the gain magnitude of l + Z1/Z2, the said non-inverting positive current feedback loop having zero loop phase shift.

A linear amplifier as claimed in claim 15 wherein the said signal gain path has a magnitude of gain equal to the gain magnitude of 1 + Zl /Z2, the said non-inverting positive current feedback loop having zero loop phase shift.

21 A linear amplifier as claimed in claim 16 wherein the said first impedance is a resistor and the said second impedance is a resistor.

22 A linear amplifier as claimed in claim 17 wherein the said first impedance is a resistor and the said second impedance is a resistor.

23 A linear amplifier as claimed in claim 18 wherein the said first impedance is a resistor and the said second impedance is a resistor.

24 A linear amplifier as claimed in claim 19 wherein the said first impedance is a resistor and the said second impedance is a resistor.

A linear amplifier as claimed in claim 20 wherein the said first impedance is a resistor and the said second impedance is a resistor.

26 A linear amplifier as claimed in claim 21 and 16 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, a fourth impedance means, with the said fourth impedance means connected between terminal 1 of the said signal comparator and to the X input of the said second current conveyor, the Y input of the said second current conveyor connected to terminal 5 of the said signal comparator, the Y input of the said first current conveyor connected to terminal 1 of the said signal comparator, the Z output of the said second current conveyor connected to the X input of the said first current conveyor, the said third impedance connected to the X input of the said first current conveyor and to terminal 2 of the said signal comparator, the Z output of the first said current conveyor connected to terminal S ofthe said signal comparator.

27 A linear amplifier as claimed in claim 27 wherein the said first current conveyor is a class II non-inverting type and the said second current conveyor is a class II inverting type, the said third impedance means is a resistor, the said fourth impedance means is a resistor.

28 A linear amplifier as claimed in claims 17 and 22 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, a fourth impedance means, with the said fourth impedance means connected between terminal 3 ofthe said signal comparator and the X input of the said second current conveyor, the Y input ofthe said second current conveyor connected to terminal 5 of the said signal comparator, the Y input of the said first conveyor current connected to terminal 1 of the said signal comparator, the Z output of the said second current conveyor connected to the X input of the said first conveyor, the third said impedance connected to the X input of the said first conveyor and to terminal 2 of the said signal comparator, the Z output of the first said current conveyor connected to terminal 5 of the said signal comparator.

29 A linear amplifier as claimed in claim 28 wherein the said first current conveyor is a class II inverting type and the said second current conveyor is a class II non-inverting type, the said third impedance means is a resistor, the said fourth impedance means is a resistor.

A linear amplifier as claimed in claims 16 and 21 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, a fourth impedance means, with the said third impedance means connected between terminal l of the said signal comparator and the X input of the said first current conveyor, the Y input of the said first current conveyor connected to terminal 2 of the said signal comparator, the Y input of the said second current conveyor connected to terminal 5 of the said signal comparator, the Z output of the said second current conveyor connected to the X input of the said first conveyor, the said fourth impedance connected to the X input of the said second current conveyor and to terminal 1 of the said signal comparator, the Z output of the said first current conveyor connected to terminal S of the said signal comparator.

31 A linear amplifier as claimed in claim 30 wherein the said first current conveyor is a class IT inverting type and the said second current conveyor is a class II non-inverting type, the said third impedance means is a resistor, the said fourth impedance means is a resistor.

32 A linear amplifier as claimed in claims 17 and 22 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, a fourth impedance means, with the said third impedance means connected between terminal 1 ofthe said signal comparator and the X input of the said first current conveyor, the Y input of the said first current conveyor connected to terminal 2 of the said signal comparator, the Y input ofthe said second current conveyor connected to terminal 5 of the said signal comparator, the Z output of the said second current conveyor connected to the X input of the said first conveyor, the said fourth impedance connected to the X input ofthe said second conveyor and to terminal 2 of the said signal comparator, the Z output of the first said current conveyor connected to terminal 5 of the said signal comparator.

33 A linear amplifier as claimed in claim 32 wherein the said first current so conveyor is a class II non-inverting type and the said second current conveyor is a class II inverting type, the said third impedance means is a resistor, the said fourth impedance means is a resistor.

34 A linear amplifier as claimed in claims 18 and 23 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, the Y input of the said first current conveyor connected to terminal 2 of the said signal comparator, the Y input of the said second current conveyor connected to terminal 1 of the said signal comparator, the Z output of the said second current conveyor connected to the X input of the said first conveyor, the Z output of the said first current conveyor connected to terminal 5 of the said signal comparator, the said third impedance means connected to the X input of the said first current conveyor and to terminal l of the said signal comparator, the X input of the said second first current conveyor connected to terminal 3 of the said signal comparator.

A linear amplifier as claimed in claim 34 wherein the said first current conveyor is a class II inverting type and the said second current conveyor is a class II inverting type, the third impedance means is a resistor.

36 A linear amplifier as claimed in claims 19 and 24 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, the Y input of the said first current conveyor connected to terminal 2 ofthe said signal comparator, the Y input of the said second current conveyor connected to terminal 2 of the said signal comparator, the Z output ofthe said second current conveyor connected to the X input of the said first conveyor, the Z output of the said first current conveyor connected to terminal 5 of the said signal comparator, the said third impedance means connected to the X input of the said first current conveyor and to terminal 1 of the said signal comparator, the X input of the said second current conveyor connected to terminal 3 ofthe said signal comparator

37 A linear amplifier as claimed in claim 36 wherein the said first current conveyor is a class It non-inverting type and the said second current conveyor is a class II non-inverting type, the said third impedance means is a resistor.

38 A linear amplifier as claimed in claims 18 and 23 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, the Y input of the said first current conveyor connected to terminal l of the said signal comparator, the Y input of the said second current conveyor connected to terminal 1 of the said signal comparator, the Z output ofthe said second current conveyor connected to the X input of the said first conveyor, the Z output of the said first current conveyor connected to terminal 5 of the said signal comparator, the said third impedance means connected to the X input of the said first current conveyor and to terminal 2 of the said signal comparator, the X input of the said first current conveyor connected to terminal 3 of the said signal comparator.

39 A linear amplifier as claimed in claim 38 wherein the said first current conveyor is a class II non-inverting type and the said second current conveyor is a class II non-inverting type, the third impedance means is a resistor.

A linear amplifier as claimed in claims 19 and 24 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, the Y input ofthe said second current conveyor connected to terminal 2 of the said signal comparator, the Y input ofthe said first current conveyor connected to terminal 1 of the said signal comparator, the Z output of the said second current conveyor connected to the X input of the said first current conveyor, the Z output of the said first current conveyor connected to terminal 5 of the said signal comparator, the said third impedance means connected to the X input of the said first current conveyor and to terminal 2 of the said signal comparator, the X input of the said second current conveyor connected to terminal 3 of the said signal comparator.

41 A linear amplifier as claimed in claim 40 wherein the said first current conveyor is a class II inverting type and the said second current conveyor is a class IT inverting type, the third impedance means is a resistor.

42 A linear amplifier as claimed in claims 18 and 23 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third current conveyor, a third impedance means, the Y input of the said second current conveyor connected to X input of the said third conveyor, the Y input of the said first conveyor connected to terminal 1 of the said signal comparator, the Y input of the said third conveyor connected terminal 1 of the said signal comparator, the X input of the said second current conveyor connected to terminal 3 ofthe said signal comparator, the said third impedance means connected to the X input of the said first current conveyor and to terminal 2 of the said signal comparator, the Z output of the said second current conveyor connected to the X input of the said first current conveyor, the Z output of the said third current conveyor connected to terminal 2 of the said signal 3> comparator, the Z output of the said first current conveyor connected to terminal 5 ofthe said signal comparator.

43 A linear amplifier as claimed in claim 42 wherein the said first current conveyor is a class 1I non-inverting type and the said second current conveyor is a class I inverting type, the said third current conveyor is a class I non-inverting type, the third impedance means is a resistor.

44 A linear amplifier as claimed in claims 18 and 23 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third current conveyor, a third impedance means, the Y input of the said second current conveyor connected to X input of the said third conveyor, the Y input of the said third conveyor connected to terminal 1 of the said signal comparator, the Y input of the said first current conveyor connected terminal 2 of the said signal comparator, the X input of the said second current conveyor connected to terminal 3 of the said signal comparator, the said third impedance means connected to the X input of the said first current conveyor and to terminal 1 of the said signal comparator, the Z output of the said second current conveyor connected to terminal 2 of the said signal comparator, the Z output of the said third current conveyor connected to the X input of the said first current conveyor, the Z output of the said first current conveyor connected to terminal 5 ofthe said signal comparator.

A linear amplifier as claimed in claim 44 wherein the said first current conveyor is a class 11 inverting type and the said second current conveyor is a class I non-inverting type, the said third current conveyor is a class I non-inverting type, the third impedance means is a resistor.

46 A linear amplifier as claimed in claims 19 and 24 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third current conveyor, a third impedance means, the Y input of the said second current conveyor connected to X input of the said third conveyor, the Y input of the said third conveyor connected to terminal 2 ofthe said signal comparator, the Y input of the said first conveyor connected terminal 1 of the said signal comparator, the X input of the said second conveyor connected to terminal 3 of the said signal comparator, the said third impedance means connected to the X input of the said first current conveyor and to terminal 2 of the said signal comparator, the Z output of the said second current conveyor connected to terminal 2 of the said signal comparator, the Z output of the said third current conveyor connected to the X input of the said first current conveyor, the Z output of the said first current conveyor connected to terminal 5 of the said signal comparator.

47 A linear amplifier as claimed in claim 46 wherein the said first current conveyor is a class IT inverting type and the said second current conveyor is a class I non-inverting type, the said third current conveyor is a class I non-inverting type, the third impedance means is a resistor.

48 A linear amplifier as claimed in claims 16 and 21 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third current conveyor, a third impedance means, a fourth impedance means, the Y input of the said second current conveyor connected to X input of the said third current conveyor, the Y input of the said first current conveyor connected terminal 2 of the said signal comparator, the X input ofthe said second current conveyor connected to terminal 5 of the said signal comparator, the said third impedance means connected to the X input of the said first current conveyor and to terminal l of the said signal comparator, the said fourth impedance means connected to terminal 1 of the said signal comparator and to the Y input of the said third current conveyor, the Z output of the said second current conveyor connected to terminal 2 of the said signal comparator, the Z output of the said third current conveyor connected to the X input of the said first current conveyor, the Z output of the said first current conveyor connected to terminal 5 of the said signal comparator.

49 A linear amplifier as claimed in claim 48 wherein the said first current conveyor is a class It inverting type and the said second current conveyor is a class I non-inverting type, the said third current conveyor is a class I non-inverting type, the third impedance means is a resistor, the fourth impedance means is a resistor.

SO A linear amplifier as claimed in claims 17 and 22 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third current conveyor, a third impedance means, a fourth impedance means, the Y input of the said second current conveyor connected to X input of the said third current conveyor, the Y input of the said first current conveyor connected terminal 2 of the said signal comparator, the X input of the said second current conveyor connected to terminal 5 of the said signal comparator, the said third impedance means connected to the X input of the said first current conveyor and to terminal 1 of the said signal comparator, the said fourth impedance means connected to terminal 2 of the said signal comparator and to the X input of the said third current conveyor, the Z output of the said second current conveyor connected to the x input of the said first current conveyor, the Z output of the said third current conveyor connected to terminal 2 of the said signal comparator, the Z output of the said first current conveyor connected to terminal 5 of the said signal comparator.

51 A linear amplifier as claimed in claim 50 wherein the said first current conveyor is a class II non-inverting type and the said second conveyor is a class I non-inverting type, the said third current conveyor is a class I non-inverting type, the third impedance means is a resistor, the fourth impedance means is a resistor.

52 A linear amplifier as claimed in claims 16 and 21 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third current conveyor, a third impedance means, a fourth impedance means, the Y input of the said second current conveyor connected to X input of the said third conveyor, the Y input of the said first current conveyor connected terminal 1 of the said signal comparator, the X input of the said second current conveyor connected to terminal 5 ofthe said signal comparator, the said fourth impedance means connected to the Y input of the said third current conveyor and to terminal 1 of the said signal comparator, the said third impedance means connected to terminal 2 of the said signal comparator and to the X input of the said first current conveyor, the Z output of the said second current conveyor connected to the x input of the said first current conveyor, the Z output of the said third current conveyor connected to terminal 2 of the said signal comparator, the Z output of the said first current conveyor connected to terminal 5 ofthe said signal comparator.

53 A linear amplifier as claimed in claim 52 wherein the said first current conveyor is a class II non-inverting type and the said second current conveyor is a class I non-inverting type, the said third current conveyor is a class I non-inverting type, the third impedance means is a resistor, the fourth impedance means is a resistor.

54 A linear amplifier as claimed in claims 17 and 22 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third current conveyor, a third impedance means, a fourth impedance means, the Y input of the said second current conveyor connected to X input of the said third conveyor, the Y input of the said first current conveyor connected terminal 1 ofthe said signal comparator, the X input of the said second current conveyor connected to terminal 5 of the said signal comparator, the said third impedance means connected to the Xinput of the said first current conveyor and to terminal 2 of the said signal comparator, the said fourth impedance means connected to terminal 2 of the said signal comparator and to the Y input of the said third current conveyor, the Z output of the said second current conveyor 3< connected to terminal 2 of the said signal comparator, the Z output of the said third current conveyor connected to the X input of the said first current conveyor, the Z output ofthe said first current conveyor connected to terminal 5 of the said signal comparator.

A linear amplifier as claimed in claim 54 wherein the said first current conveyor is a class 11 inverting type and the said second conveyor is a class I non-inverting type, the said third current conveyor is a class I non- inverting type, the third impedance means is a resistor, the fourth impedance means is a resistor.

56 A linear amplifier as claimed in claims 19 and 24 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, the X input of the said first current conveyor connected to terminal 3 of the said signal comparator, the said third impedance means connected to the X input of the said second current conveyor and to terminal 2 of the said signal comparator, the Y input of the said first current conveyor connected to terminal 2 of the said signal comparator, the Y input ofthe said second current conveyor connected to terminal 1 of the said signal comparator, the Z output of the said first current conveyor connected to the terminal 5 ofthe said signal comparator, the Z output of the said second current conveyor connected to the X input of the said first current conveyor.

57 A linear amplifier as claimed in claim 56 wherein the said first current conveyor is a class II inverting type and the said second current conveyor is a class IT inverting type, the third impedance means is a resistor.

58 A linear amplifier as claimed in claims 19 and 24 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, the X input of the said first current conveyor connected to terminal 3 of the said signal comparator, the said third impedance means connected to the X input of the said second current conveyor and to terminal 1 ofthe said signal comparator, the Y input of the said first current conveyor connected to terminal 2 of the said signal comparator, the Y input of the said second current conveyor connected to terminal 2 of the said signal comparator, the Z output of the said first current conveyor connected to the terminal 5 of the said signal comparator, the Z output of the said second current conveyor connected to the X input of the said first current conveyor.

59 A linear amplifier as claimed in claim 58 wherein the said first current conveyor is a class II inverting type and the said second current conveyor is a class II non-inverting type, the third impedance means is a resistor.

A linear amplifier as claimed in claims 19 and 24 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, a fourth impedance means, a fifth impedance means, the said third impedance means connected to the X input of the said second current conveyor and to terminal 2 of the said signal comparator, the fourth impedance means connected to the X input of the said first current conveyor and to terminal 3 of the said signal comparator, the said fifth impedance means connected to terminal 2 of the said signal comparator and to terminal 3 of the said signal comparator, the Y input of the said first current conveyor connected to terminal 2 of the said signal comparator, the Y input of the said second current conveyor connected to terminal l of the said signal comparator, the Z output of the said first current conveyor connected to the terminal 5 of the said signal comparator, the Z output of the said second current conveyor connected to the X input of the said first current conveyor.

61 A linear amplifier as claimed in claim 60 wherein the said first current conveyor is a class II inverting type and the said second current conveyor is a class II inverting type, the third impedance means is a resistor, the fourth impedance means is a resistor, the fifth impedance means is a resistor.

62 A linear amplifier as claimed in claims 19 and 24 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, a fourth impedance means, a fifth impedance means, the said third impedance means connected to the X input of the said second current conveyor and to terminal 1 of the said signal comparator, the said fourth impedance means connected to the X input of the said first current conveyor and to terminal 3 of the said signal comparator, the said fifth impedance means connected to terminal 2 of the said signal comparator and to terminal 3 of the said signal comparator, the Y input of the said first current conveyor connected to terminal 2 of the said signal comparator, the Y input ofthe said second current conveyor connected to terminal 2 of the said signal comparator, the Z output of the said first current conveyor connected to the terminal 5 of the said signal comparator, the Z output of the said second current conveyor connected to the X input of the said first current conveyor.

63 A linear amplifier as claimed in claim 62 wherein the said first current conveyor is a class II inverting type and the said second current conveyor is a class II non-inverting type, the third impedance means is a resistor, the fourth impedance means is a resistor, the fifth impedance means is a resistor.

J

64 A linear amplifier as claimed in claims 19 and 24 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, a fourth impedance means, a fifth impedance means, the said third impedance means connected to the X input of the said second current conveyor and to terminal 2 of the said signal comparator, said the fourth impedance means connected to terminal 2 of the said signal comparator and to terminal 3 of the said signal comparator, the said fifth impedance means connected to terminal 2 of the said signal comparator and to the X input ofthe said first current conveyor, the Y input of the said first current conveyor connected to terminal 3 of the said signal comparator, the Y input of the said second current conveyor connected to terminal 1 of the said signal comparator, the Z output ofthe said first current conveyor connected to the terminal 5 of the said signal comparator, the Z output of the said second current conveyor connected to the X input of the said first current conveyor.

A linear amplifier as claimed in claim 64 wherein the said first current conveyor is a class II non-inverting type and the said second current conveyor is a class II non-inverting type, the third impedance means is a resistor, the fourth impedance means is a resistor, the fifth impedance means is a resistor.

66 A linear amplifier as claimed in claims 19 and 24 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, a fourth impedance means, a fifth impedance means, the said third impedance means connected to the X input of the said second current conveyor and to terminal 1 of the said signal comparator, the said fourth impedance means connected to terminal 3 ofthe said signal comparator and to terminal 2 ofthe said signal comparator, the said fifth impedance means connected to terminal 2 of the said signal comparator and to the X input of the said first current conveyor, the Y input of the said first current conveyor connected to terminal 3 of the said signal comparator, the Y input of the said second current conveyor connected to terminal 2 ofthe said signal comparator, the Z output of the said first current conveyor connected to the terminal 5 of the said signal comparator, the Z output of the said second current conveyor connected to the X input of the said first current conveyor.

67 A linear amplifier as claimed in claim 66 wherein the said first current conveyor is a class II non-inverting type and the said second current conveyor is a class II inverting type, the third impedance means is a resistor, the fourth impedance means is a resistor, the fifth impedance means Is a resistor. 3t

68 A linear amplifier as claimed in claims 19 and 24 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, a fourth impedance means, a fifth impedance means, a sixth impedance means, the said sixth impedance connected to terminal 3 of the said signal comparator and to terminal 2 of the said signal comparator, the fourth impedance means connected to terminal 1 of the said signal comparator and to the Y input of the said second current conveyor, the said fifth impedance means connected to terminal 2 of the said signal comparator and to the Y input of the said second current conveyor, the said third impedance means connected to the X input of the said second current conveyor and to the X input of the said first current conveyor, the Y input ofthe said first current conveyor connected to terminal 3 of the said signal comparator, the Z output of the said second current conveyor connected to the terminal 5 of the said signal comparator, the Z output of the said first current conveyor connected to terminal 2 ofthe said signal comparator.

69 A linear amplifier as claimed in claim 68 wherein the said first current conveyor is a class II inverting type and the said second current conveyor is a class II inverting type, the third impedance means is a resistor, the fourth impedance means is a resistor, the fifth impedance means is a resistor, the sixth impedance means is a resistor.

A linear amplifier as claimed in claims 19 and 24 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, a fourth impedance means, a fifth impedance means, a sixth impedance means, the said sixth impedance connected to terminal 3 of the said signal comparator and to terminal 2 of the said signal comparator, the fourth impedance means connected to terminal 1 of the said signal comparator and to the Y input of the said second current conveyor, the said fifth impedance means connected to terminal 2 of the said signal comparator and to the Y input of the said second current conveyor, the said third impedance means connected to the X input of the said second current conveyor and to the X input of the said first current conveyor, the Y input of the said first current conveyor connected to terminal 3 of the said signal comparator, the Z output of the said first current conveyor connected to the terminal 5 of the said signal comparator, the Z output of the said second current conveyor connected to terminal 2 of the said signal comparator.

71 A linear amplifier as claimed in claim 70 wherein the said first current conveyor is a class II non-inverting type and the said second conveyor is a class II non-inverting type, the third impedance means is a resistor, the l 3N fourth impedance means is a resistor, the fifth impedance means is a resistor, the sixth impedance means is a resistor.

72 A linear amplifier as claimed in claims 14 wherein the said signal comparator consists of a first current conveyor, a third impedance means, the said third impedance means connected to pin 5 of the said signal comparator and to pin 2 of the said signal comparator, the Y input ofthe said current conveyor connected to terminal 1 of the said signal conveyor, the X input of the said current conveyor connected to terminal 3 of the said signal comparator, the Z output of the said current conveyor connected to terminal 5 of the said signal comparator.

73 A linear amplifier as claimed in claim 72 wherein the said first current conveyor is a class II inverting type.

74 A linear amplifier as claimed in claims 19 and 24 wherein the said signal comparator consists of a first current conveyor, a third impedance means, a fourth impedance means, the Y input of the said first current conveyor connected to terminal 1 of the said first current conveyor, the said third impedance means connected to the X input ofthe said current conveyor and to terminal 3 of the said signal comparator, the said fourth impedance means connected to terminal 3 of the said signal comparator and to terminal 2 of the said signal comparator, the Z output of the said first current conveyor connected to terminal 5 of the said signal comparator.

A linear amplifier as claimed in claim 74 wherein the said first conveyor is a class II inverting type, the third impedance means is a resistor, the fourth impedance means is a resistor.

76 A linear amplifier as claimed in claims 19 and 24 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, the said third impedance means connected to the X input ofthe said second conveyor and to the X input of the said first current conveyor, the Y input of the said first current conveyor connected to terminal 5 of the said signal comparator, the Y input ofthe said second current conveyor connected to terminal 1 ofthe said signal comparator, the Z output of the said second current conveyor connected to the terminal 5 of the said signal comparator, the Z output of the said first current conveyor connected to terminal 2 of the said signal comparator, terminal 3 of the said signal comparator connected to terminal 2 of the said signal comparator.

77 A linear amplifier as claimed in claim 76 wherein the said first current

77 A linear amplifier as claimed in claim 76 wherein the said first current conveyor is a class II inverting type, the said second conveyor is a class II inverting type, the third impedance means is a resistor.

78 A linear amplifier as claimed in claims 19 and 24 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, the said third impedance means connected to the X input of the said second current conveyor and to the X input of the said first current conveyor, the Y input of the said first current conveyor connected to terminal 5 of the said signal comparator, the Y input ofthe said second current conveyor connected to terminal 1 of the said signal comparator, the Z output of the said second current conveyor connected to the terminal 2 of the said signal comparator, the Z output of the said first current conveyor connected to terminal 5 of the said signal comparator, terminal 3 of the said signal comparator connected to terminal 2 ofthe said signal comparator.

79 A linear amplifier as claimed in claim 78 wherein the said first current conveyor is a class II non-inverting type, the said second current conveyor is a class II non-inverting type, the third impedance means is a resistor.

A linear amplifier as claimed in claim 72 wherein the said signal gain path has a magnitude of gain equal to the gain magnitude of 1 + Z1/Z2 + Z1/Za, where Za is the third impedance means, the said non-inverting positive current feedback loop having zero loop phase shift.

81 A linear amplifier as claimed in claim 80 wherein the said first impedance means is a resistor, the said second impedance means is a resistor, the third impedance means is a resistor.

82 A linear amplifier as claimed in claim 25 wherein the said error current is a function of the voltage drop between terminals 3 and 5 of the said signal comparator.

83 A linear amplifier as claimed in claim 25 wherein the said error current is the current into terminal 3 of the said signal comparator means.

84 A linear amplifier substantially as described herein with reference to figures 7 to 71 ofthe accompanying drawings.

Amendments to the claims have been filed as follows by\ 47 A linear amplifier as claimed in claim 46 wherein the said first current conveyor is a class II inverting type and the said second current conveyor is a class I non-inverting type, the said third current conveyor is a class I non-inverting type, the third impedance means is a resistor.

48 A linear amplifier as claimed in claims 16 and 21 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third current conveyor, a third impedance means, a fourth impedance means, the Y input of the said second current conveyor connected to X input ofthe said third current conveyor, the Y input ofthe said first current conveyor connected terminal 2 of the said signal comparator, the X input of the said second current conveyor connected to terminal 5 of the said signal comparator, the said third impedance means connected to the X input of the said first current conveyor and to terminal 1 of the said signal comparator, the said fourth impedance means connected to terminal 1 ofthe said signal comparator and to the Y input of the said third current conveyor, the Z output of the said second current conveyor connected to terminal 2 ofthe said signal comparator, the Z output of the said third current conveyor connected to the X input of the said first current conveyor, the Z output of the said first current conveyor connected to terminal 5 of the said signal comparator.

49 A linear amplifier as claimed in claim 48 wherein the said first current conveyor is a class II inverting type and the said second current conveyor is a class I non-inverting type, the said third current conveyor is a class T non-inverting type, the third impedance means is a resistor, the fourth impedance means is a resistor.

A linear amplifier as claimed in claims 17 and 22 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third current conveyor, a third impedance means, a fourth impedance means, the Y input of the said second current conveyor connected to X input of the said third current conveyor, the Y input of the said first current conveyor connected terminal 2 of the said signal comparator, the X input of the said second current conveyor connected to terminal 5 of the said signal comparator, the said third impedance means connected to the X input ofthe said first current conveyor and to terminal 1 of the said signal comparator, the said fourth impedance means connected to terminal 2 of the said signal comparator and to the Y input of the said third current conveyor, the Z output of the said second current conveyor connected to the x input of the said first current conveyor, the Z output of the said third current conveyor connected to terminal 2 of the -air fourth impedance means is a resistor, the fifth impedance means is a resistor, the sixth impedance means is a resistor.

72 A linear amplifier as claimed in claims 14 wherein the said signal comparator consists of a first current conveyor, a third impedance means, the said third impedance means connected to pin 5 of the said signal comparator and to pin 2 of the said signal comparator, the Y input of the said current conveyor connected to terminal 1 of the said signal comparator, the X input of the said current conveyor connected to terminal 3 of the said signal comparator, the Z output of the said current conveyor connected to terminal S of the said signal comparator.

74 A linear amplifier as claimed in claims 19 and 24 wherein the said signal comparator consists of a first current conveyor, a third impedance means, a fourth impedance means, the Y input of the said first current conveyor connected to terminal 1 of the said first current conveyor, the said third impedance means connected to the X input of the said current conveyor and to terminal 3 of the said signal comparator, the said fourth impedance means connected to terminal 3 of the said signal comparator and to terminal 2 of the said signal comparator, the Z output of the said first current conveyor connected to terminal 5 of the said signal comparator.

76 A linear amplifier as claimed in claims 19 and 24 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, the said third impedance means connected to the X input ofthe said second conveyor and to the X input of the said first current conveyor, the Y input of the said first current conveyor connected to terminal 5 of the said signal comparator, the Y input of the said second current conveyor connected to terminal 1 of the said signal comparator, the Z output of the said second current conveyor connected to the terminal 5 ofthe said signal comparator, the Z output of the said first current conveyor connected to terminal 2 ofthe said signal comparator, terminal 3 of the said signal comparator connected to terminal 2 ofthe said signal comparator.