WO2006030169A1

WO2006030169A1 - Linear amplifiers

Info

Publication number: WO2006030169A1
Application number: PCT/GB2004/003994
Authority: WO
Inventors: Gary Miller
Original assignee: Gary Miller
Priority date: 2004-09-18
Filing date: 2004-09-18
Publication date: 2006-03-23

Abstract

A linear amplifier arrangement for driving a load which operates by converting the input voltage drive into a current and comparing this current with a second current that is a linear function of the output voltage or current. The difference in these two currents is used to provide an additional correction current drive to the input of the amplifier, pre-distorting the total drive to the amplifier. The resultant amplifier, having substantially increased linearity and bandwidth with very low open loop gain. A number of embodiments are presented using current conveyors to provide the functions of voltage to current conversion, current sampling and current amplification.

Description

LINEAR AMPLIFIERS.

Technical Field

This invention relates to amplifier circuits with low distortion. In particular the replacement of high open loop gain amplifiers with substantial lower open loop gain amplifier circuits that utilise error correction. The error correction resultants in amplifiers having substantially improved linearity with less closed loop signal distortion. This invention avoids the use of feedback around a very high open loop gain amplifier as this method of distortion reduction has a number of limitations.

Background Art

Figs 1 and 2 are circuit arrangements for prior art series and shunt amplifiers, fig 1 being a shunt type and fig 2 being a series type. These amplifiers have very high open loop gain so that under closed loop conditions the amplifiers exhibit acceptably low harmonic and intermodulation distortion. Designing the amplifiers to have high gain results in reduced bandwidth, typically for an operational amplifier, say a classic 741, a value of 18.9KHz BEFORE frequency compensation is added. Amplifiers will have multiple poles in their responses so in the case of a 741 an additional pole will be at approximately 300Khz with additional complex poles. If feedback is now applied to these amplifiers they will oscillate due to the combined phase shift of the multiple poles. Frequency compensation therefore must be applied so that the open-loop gain falls to unity at a frequency below the second most dominant pole for adequate phase margin. In the case of the 741 using the technique of pole spitting, the first pole moves to 5Hz and the second beyond the complex poles. Fig 3 illustrates the open loop frequency response with and without frequency compensation. It can be seen that this method of error reduction (i.e. distortion) by negative feedback around a high gain amplifier results in a trade off, higher frequency loop bandwidth is reduced so that lower frequency loop gain (4OdB @ 20khz) is high enough to reduce errors internally generated in the amplifier. Therefore the arrangement of feedback around a high gain amplifier has a number of problems. By taking greater gain in the amplifiers internal gain stages results in reduction of their pole frequencies, this in turn results in greater amounts of compensation to reduce the high frequency open loop gain for adequate phase margin. The result is a trade-off between reduced errors at the lower frequencies for higher errors at higher frequencies. Also the addition of the frequency compensation capacitor, in the case of a 741, a value of 3OpF, results in slew rate induced distortion. A further potential problem occurs with series feedback amplifiers, due to common mode gain non-linearity, which cannot be reduced by the overall negative feedback loop and can possibly be a limiting factor as regard to error reduction. In general then, the application of negative feedback results in a considerable reduction in the available bandwidth of an amplifier compared to a low gain open loop stage. Also the application of negative feedback results in a considerable reduction of loop gain at high frequency due to frequency compensation. Disclosure of the Invention According to the present invention there is provided a linear amplifier comprising: an output amplifier having an inverting input terminal and a non-inverting input terminal and an output for delivering output signal drive to a load ; a signal comparator means; a feedback current that is a function of the said output signal drive which is coupled to the inverting input of the said output amplifier; a first impedance means in which the said feedback current flows; with the action of the said signal comparator means being to generate an output correction current that is a function of the current in the first impedance means and the input voltage present at the input of the said linear amplifier, the said output correction current coupled to the inverting input of the said output amplifier, pre-distorting the total signal drive to the said output amplifier thus resulting in substantially reduced signal distortion in the said linear amplifier. Figs 4 to 9 are block diagrams of the present invention. They consist of the following, a load, this may be driven at one end or can be bridged connected by the addition of a second drive amplifier. an output amplifier, which provides voltage, current or power amplification and drives the load. This can be operated in all modes i.e. class A, B, D etc. This amplifier has the dominant distortion of the linear amplifier. a first impedance means and second impedance, a signal comparator, this has a 5 terminals. Terminal 1 and 2 are the inputs for the linear amplifier, they provide the linear amplifier with a single-ended or differential input. Terminal 3 is a connection for the first impedance means; this first impedance being designated Rl in the prior art amplifiers. Terminal 4 provides a connection to the non-inverting input of the output amplifier. Terminal 5 provides a connection to the inverting input of the output amplifier. Figs 4 to 9 all have a common mode of operation. This is to reduce the signal distortion present at the load by sensing the current in the first impedance means comparing this with a second current that is a function of the input voltage present at terminal 1 and 2 of the signal comparator. The difference being essentially the distortion products generated in the output amplifier. This correction current is then coupled to the inverting input of the output amplifier via terminal 5 output, so pre-distorting the total signal drive to the output amplifier, resulting in a linear amplifier with substantially reduced output distortion. Figs 4 to 9 differ in the way the output signal, be it a voltage or current output is sensed and the connection of the second impedance means. In the case of Fig's 4 to 6 the feedback current passes through the second impedance means to the inverting input of the output amplifier. Where as in Figs' 7 to 9 the feedback current couples directly to the inverting input of the output amplifier. Fig's 7 to 9 therefore provide a feedback current from a high source impedance compared to the node comprising the inverting input of the output amplifier and the first impedance means and Fig's 4 to 6 connect terminal 1 of the second impedance means to a low impedance voltage source. The purpose of the first and second impedance means being to essentially define the overall gain of the linear amplifier. Fig 4 connects the second impedance means directly to the load, the output being a low output impedance (voltage) output. Fig 5 has a current sensing means, which outputs a voltage at terminal 1 of the second impedance means, that is a function of the output current in the load. Fig 6 has a voltage sensing means that outputs a voltage at terminal 1 of the second impedance means which is a function of the differential voltage present across the load.

Fig 7 has a current sensing means that outputs a current to the inverting input of the output amplifier, with the second impedance means having its first terminal coupled to signal common within the linear amplifier. Fig 8 has voltage sensing means that outputs a current to the inverting input of the output amplifier, with the second impedance means having its first terminal coupled to signal common within the linear amplifier. Fig 9 has voltage sensing means that outputs a current to the inverting input of the output amplifier which is a function of the differential voltage present across the load, with the second impedance means having its first terminal coupled to signal common within the linear amplifier. In general the current in the first impedance means can also be sensed by circuitry that is coupled between the first terminal of the first impedance means and the inverting input of the output amplifier. A number of embodiments are presented which provide internal circuitry and couplings within the signal comparator. These embodiments allow the linear amplifier to function with differential or single ended inputs. They also differ in the way the feedback current in the first impedance means is sensed.

First embodiment according to the invention In the first embodiment terminals 1 and 3 are connected together by internal links and 4 to 2. Input signal drive is to terminal 2 of the first impedance means, with the non-inverting terminal of the output amplifier grounded. In this mode the current in the first impedance means is sensed indirectly by terminals 3 and 5 of the signal comparator, the resultant voltage drop across the first impedance means being converted into a current by at least one internal impedance. If in the case of the first impedance means being a resistor then the internal impedance would also be a resistor to give a frequency independent ratio. This sampled current is compared to a second current that is a function of the input voltage present at terminal 1 of the signal comparator, the voltage to current conversion being achieved by at least one internal impedance within the signal comparator. The difference between these two currents resulting in a correction current from terminal 5 of the signal comparator, which pre- distorts the drive to the output amplifier. Second embodiment according to the invention

In the second embodiment terminals 1 to 4 are connected by internal links also terminals 3 to 2. Input signal drive is to the non-inverting input of the output amplifier. In this mode the current in the first impedance means is sensed indirectly by terminals 3 and 5 of the signal comparator, the resultant voltage drop across the first impedance means being converted into a current by at least one internal impedance. If in the case of the first impedance means being a resistor then the internal impedance would also be a resistor to give a frequency independent ratio. This sampled current is compared to a second current that is a function of the input voltage present at terminal 1 of the signal comparator, the voltage to current conversion being achieved by at least one internal impedance within the signal comparator. The difference between these two currents resulting in a correction current from terminal 5 of the signal comparator, which pre- distorts the drive to the output amplifier. Third embodiment according to the invention In the third embodiment terminals 4 to 2 are connected by an internal link. Input signal drive is to terminal 2 of the first impedance means, with the non-inverting terminal of the output amplifier grounded. In this mode of operation the current in the first impedance means is sensed directly by terminal 3 of the signal comparator. Ideally the impedance looking into terminal 3 is zero, resulting in an overall gain for the linear amplifier set by the first and second impedance means and the internal circuitry within the signal comparator. If it is not zero it can be taken into account by the adjustment in the value of the first impedance. The current flowing into terminal 3 is compared to a second current that is a function of the input voltage present at terminal 1 of the signal comparator, the voltage to current conversion being achieved by at least one internal impedance within the signal comparator. The difference between these two currents resulting in a signal current from terminal 5 of the signal comparator, which pre-distorts the drive to the output amplifier. Fourth embodiment according to the invention

In the fourth embodiment terminals 1 to 4 are connected by an internal link. Input signal drive is to the non-inverting input of the output amplifier. In this mode of operation the current in the first impedance means is sensed directly by terminal 3 of the signal comparator. Ideally the impedance looking into terminal 3 is zero, resulting in an overall gain for the linear amplifier set by the first and second impedance means and the internal circuitry within the signal comparator. If it is not zero it can be taken into account by the adjustment in the value of the first impedance. The current flowing into terminal 3 is compared to a second current that is a function of the input voltage present at terminal 1 of the signal comparator, the voltage to current conversion being achieved by at least one internal impedance within the signal comparator. The difference between these two currents resulting in a signal current from terminal 5 of the signal comparator, which pre-distorts the drive to the output amplifier. Fifth embodiment according to the invention

In the fifth embodiment terminals 1 to 3 are connected by an internal link. The linear amplifier responds to the differential signal voltage present between terminals 1 and 2 of the signal comparator.

All five embodiments correct for signal distortion, noise etc generated in the amplifier by providing a correction signal current from terminal 5 of the signal comparator. This correction signal pre-distorts the drive to the output amplifier at its inverting input. The input signal voltage present between terminal 1 and 2 of the signal comparator is converted into a current by an internal impedance or resistance. This is summed directly with the current in the first impedance means, or a current that is a linear function of the current in the first impedance means. The resultant difference in current being the correction current. This invention has a number of improved amplifier arrangements that are electronic implementations of the five embodiments. They correct for signal distortion and noise generated by the output amplifier without the use of very high open loop gain. They can connected in series, shunt or differential at their inputs and provide a voltage or current output. For the linear amplifier to function correctly a number of circuit conditions must be met, these three conditions are as follows. (I)A positive, current feedback loop

A positive, current feedback loop must be formed. The path of the loop referring to fig 4 to 9 is a combination of a current gain path and a current attenuation path. The input to the current gain path is terminal 1 of the first impedance means. The output of the current gain path is terminal 5 of the signal comparator. The input to the current attenuation path is the node comprising terminal 2 of the second impedance means, terminal 1 of the first impedance means and the inverting input of the output amplifier. The output of the current attenuation path is the coupling from the above node to terminal 1 of the first impedance means. (2) A negative feedback loop

A negative feedback loop is required, the path being from the output of the output amplifier, through the second impedance means and back to the inverting input of the output amplifier. (3) A balanced condition

The balanced condition for the linear amplifier occurs when the magnitude of gain for the above current gain path is equal one plus the first impedance means divided by second impedance means plus the first impedance means divided by a shunt impedance means. The shunt impedance means being any impedance present at terminal five of the signal comparator to signal common. If the impedance looking into terminal 3 of the signal comparator is not zero its value must be added to the value of the first impedance to give the correct value for the balanced condition. The phase shift of the current gain path must equal the phase shift of the attenuation path. In the case of the impedance means being resistors, the phase shift of the current gain path is zero, therefore zero loop phase shift results. Under this balanced condition all of the error signals generated in or coupled internally to the output amplifier are eliminated from the output signal driving the load. Figs 10 to 12 are block diagrams that are based on fig 4. These expand the signal comparator and show internal means for sampling the current in the first impedance means (Sl) and the comparison amplifier (Al) to generate the correction current. Fig 10 being a shunt, voltage output type, Fig 11 being a series, voltage output type, Fig 12 being a series, voltage output type. These block diagrams can be used to represent an appropriate embodiment according to the following table. Embodiment 1 Fig 10

Embodiment 2 Fig 11

Embodiment 3 Fig 10

Embodiment 4 Fig 12

Analysis of Figs 10

The linear amplifier consist of an output amplifier, A2, which drives the load with substantial power drive, such that the open loop distortion (without any form of negative feedback) is higher than required for the given application. For example a power amplifier for audio applications would require feedback to reduce distortion to inaudible levels. Additional means are also provided, these are Sl and Al. Sl is a sampling means that samples the input current, in the case of the series input amplifier, and samples the feedback current in the case of the shunt feedback amplifier. The sample being a linear current, which is coupled to the Al means. This current can be greater or smaller than the said sampled current. Therefore Sl=Is/Il, Il is the current in the first impedance means and Is is the output current of the sampler. The means Al is an arrangement that compares the said sample current with an additional current that is a function of the input voltage. Therefore a resistive means is provided within the Al means to convert the input voltage into a current. The difference between the said two currents is then coupled to the amplifier. The sampling means may also have one or more resistive elements to define its current transfer gain Is/11. The two circuit arrangements therefore have additional circuit means, Sl and Al which correct for distortion and other errors generated in A2 by pre- distorting the input drive to A2 inverting input. This operation of the linear amplifier can best be understood by considering the action of the prior art shunt amplifier. Here the input voltage sets up an input current that is given by:

^[R1

R₁

Where Ve is the voltage at the inverting input, which is finite and is a function of the output voltage and the voltage gain of A2, ie Therefore:

* = V_in - V₁ A,

R,

The current therefore is a measure of the gain of A2. If A2 is infinite then

¹ " in

In practice A2 is finite so as the instantaneous gain reduces the current in Rl increases as the gain reduces so the current through increases Rl. The current in Rl is proportional to the instantaneous gain of A2.

Therefore the current in Rl, if sensed by some additional circuit means, can be compared to an additional current that is a function of the input voltage. The difference in current can be applied to the A2 amplifiers inverting terminal to pre-distort the input voltage such that it compensates for the finite and non-linear gain of A2.

For Fig 10 the sampling means Sl samples the input current flowing through Rl and couples this to first amplifying means Al. The current is compared to a second current that is a function of the input voltage and the difference is coupled to the second amplifying means A2 that drives the load. For the linear amplifier to function correctly a number of conditions must be met. The first is the current loop from the output of the means Al, to the junction of R2 and the sampling means Sl, through the sampler to the input of the Al means is non-inverting. Assuming the output current of Al increases, so the voltage at the inverting input of A2 will increase. For any given input voltage, the current from the output of the current sampler will reduce. This in turn will increase the output current of Al, a positive current feedback loop results.

The second condition is that the output amplifier A2 has feedback applied by R2 to its inverting input, an inverting voltage feedback loop results, the loop being through A2 to the output, and back to the inverting input via R2.

The third condition is that product of the sampling ratio of Sl and the current gain of the amplifier Al is stable and fixed at a value that provides a balanced condition within the arrangement. The balanced condition then provides maximum rejection of errors originating in the output amplifier A2.

The transfer function for fig 10 is given by:

S₁A₁ + 1

Where Rl is the input resistor as per the prior art, coupling the input signal voltage to the inverting input of A2, R3 is a resistive means which is within the Al amplifying means and converts the input voltage into a current. Where Al = IF/(TR3-Sllrl)

D is given by:

R L₇₂ A -π.,₂ + R,

Where Rs is the output resistance of the amplifier A2 and RL is the load resistance. In general Sl, Al and A2 are a function of signal frequency and Rs, RL are complex impedance's.

Now the purpose of the new arrangements is to eliminate the error contribution of Al on the output signal. Looking at the denominator of the transfer function it can be seen that if:

S₂ R₁ R₁

Then D, which is a function of A3 and its output resistance, is eliminated from the transfer equation, i.e.

T₂

The above balanced condition therefore eliminates A2, and its output resistance from the transfer equation. It should also be noted that the value of R3 does not effect the balanced condition (it will effect the overall transfer gain).

Substituting some values for Sl, Al, Rl and R2.

Rl = 1KΩ Rl = 50KΩ

If Sl is unity current gain then Al current gain = 1.02.

Therefore the overall gain is given by:

A_v A₁ - S₁A₁ + 1

1

^"E

Rearranging gives:

Setting the value of R3 = Rl, with Sl = unity gain then the overall gain is given by:

- A_^ = R₁ R i

The current gain of Al only needs to be 1.02, for an overall gain of -50. If the overall gain is set to -1 then Rl = R2, and the gain of Al is 2. Therefore the gain range of typically 1.02 to 2 will ensure the maximum bandwidth for Al.

The gain of A2 is determined by the required stability gain margin of the amplifier. For a gain margin of 1OdB and overall gain of -50, the gain of A2 would be 110.27. This new amplifier arrangement therefore provides the lowest possible signal distortion, with low internal gain requirements. The low gains will maximise the bandwidths of Al and A2. The output amplifier only needs a small increase in gain above the overall closed loop gain to provide sufficient gain margin for the linear amplifier. This reduced gain will maximise the bandwidth of the output amplifier and also reduce the open loop non-linear of the output amplifier due to increased series current feedback within each stage making up the output amplifier. The output amplifier will also have a minimum number of gain stages due to the very low gain requirements. Al again only needs a maximum current gain of 2, in the case of a unity gain buffer, so this will maximise bandwidth. Al can be operated in a current mode, with the best active element to do this being a current conveyor. Current conveyors make best use of active devices by operating them in a current mode ie the signal is in the form of a current with maximum voltage swings being delta vbe's, typically 10OmV, therefore slew rate limiting is not a problem. No frequency compensation is required within the output amplifier, stability can be controlled by a reduction of bandwidth within the Al amplifier. In general the input offset voltage of the output amplifier will not saturate the output of the linear amplifier for a reasonable balanced output amplifier. Therefore during linear amplifier development, production test or fault finding the linear amplifier can be operated open loop if required as an aid in finding the faulty area. The loop opened at the output of the Al amplifier. The transfer function of the arrangement is generally a function of the complex frequency:

T[S) = output , v input (^S )

Therefore the balanced equation is:

In the steady-state,

s = jω ie:

For the balance to hold over the required frequency range the magnitude

and phase of SLAl must match that of 1 + R1/R2 . With Rl and R2 in the simplest of cases being both purely resistive (no reactive components) then:

R₂ and ZS₁A₁ = Z0^°

Sl and Al must have sufficient bandwidth to ensure that over the frequency range of interest the magnitude and phase meets the above criteria within acceptable limits.

In general poles especially within Al will cause the gain to drop off and unbalance the equation due to magnitude gain drop and increased phase shift. Analysis of Figs 11

The linear amplifier for figs 11 is operated in a non-inverting mode, with the input signal drive to the non-inverting input of the output amplifier. Operation is the same as figs 10 but in this case, Sl now samples the feedback current in Rl. The transfer equation is:

Λ_v(s ) = R_LA_2AK_XR₂+A_XR_LR₂ ,A_2B - _i_)

ReJK. v R -"-i3K-"-_vY \ \ R , <, XV, I

Where:

R₁ R₂ R₁

K_γ = 1 + R_L + R_L R_s R₂

A2A is the non-inverting gain of A2 A2B is the inverting gain of A2

R3 is an internal resistance within Al that converts the input voltage into a current.

Al is the differential current gain within Al, the difference being the current in R3 and the current in Rl .

The output current of Al being: lout = (Vin/R3)A1-IR1S1A1

Where Sl is the ratio of current in Rl to the current coupled to Al i.e.

Sl = if/IR1.

The transfer function can be reduced by setting Kx to zero i.e.

K_x = I + ! - A₁ = O R₁ R₂ R₁ i.e.

A₁ = 1 + R₁

R₁ Then

R,

Now

A₁ = 1 + ,R₁

T₂

Therefore

Ads ) = R, + R,

R₃

IfR3=Rl

R₁ Analysis of figs 12

Fig 14 is a series voltage output type. A new means is provided, SA, which combines the functions of current sampling and comparator to produce the correcting current to the inverting input of A2. This is possible because the feedback current that flows through Rl can be directly compared to the input current (that is a function of the input voltage) by ensuring that the input to SA seen by Rl is a virtual earth or has some fixed input resistance. Fig 12 therefore shows the basic arrangement.

The transfer function for fig 12 is given by:

Λ_v(s )

Where:

K_γ = 1 + R± + R± R₅ R₂

K_x = J_+ 1_- A₁

A2A is the non-inverting gain of A2 A2B is the inverting gain of A2

R3 is an internal resistance within SA that converts the input voltage into a current.

Al is the differential current gain within SA, the difference being the current in R3 and the current in Rl. The output current of SA being: lout = (Vin/R3)A1-IR1A1

The transfer function can be reduced by setting Kx to zero i.e.

K_x = 1 + 1 - A₁ = 0 J?, R₂ R₁

ie

A₁ = 1 +J^_

~R₂~ The balanced condition Then:

A_γ{s ) = A₁R₂ R₃

Now:

A₁ = 1 + R₁

Therefore:

R₃

IfR3=Rl:

Λ_v(s) = 1 + ^₂

Therefore the transfer function is independent of the gain of A3 under the balanced condition. If the input resistance looking into the input of SA that is coupled to Rl is not zero, then in the above transfer equation the value of Rl = Rt, with Rt = Rl + Rin, where Rin is the input resistance. It also possible for the input, (Vin), to SA to be attenuated. In this case the transfer equation is modified.

The linear amplifier of figs 4 to 6 can be modified to include a impedance connected from the inverting input of the output amplifier to signal ground. This resistor can be added to figs 12 and thus modify the transfer gain and also the balanced equation. The balanced equation is now Kx =1+Z1/Z2+Z1/ZS - Al, where ZS is the additional resistor. The gain of the amplifier is Vo/Vi = 1 + Z2/ZS. The transfer function is:

Λ_v(s )

Figs 13 to 49 are current conveyor implementations of the embodiments of figs 4 to 9. The current conveyor is an ideal active element for implementing the linear amplifier and provides the functions of current sampler and current amplifier. The conveyor implementations provide voltage output drive to the load and operate with series or shunt feedback. For each of the circuit arrangements terminations numbered 1 to 5 are present. These correspond with the numbering of the basic block diagrams of the linear amplifier in figs 4 to 9. Therefore the signal comparator means for the conveyor implementations can clearly be seen for each circuit, with the conveyor circuitry contained within the signal comparator means. In the basic block diagrams in figs 10 to 12, the signal comparator and other means correspond with figs 4 to 9. It can be seen that a large number of possible solutions exist for practical hardware using CCI+, CCI-, CCII+ or CCII- current conveyors. The properties of the four types of conveyors are as follows.

All the conveyors have a Y input, a X input and a Z output. In all cases the output Z has infinite output impedance, so it is a controlled current source. The X input has zero input impedance and the Y input has an infinite input impedance for the CCII types and zero for the CI types. CCI+ Ix = Iz, Vx = Vy, Iy = Ix CCI-

Ix = -Iz, Vx = Vy, Iy = Ix CCH+

Ix = Iz, Vx = Vy, Iy = O CCII-

Ix= -Iz, Vx = Vy, Iy = O

The "standard" conveyor can be seen to have a unity current gain from its X input to its Z output. However it is possible to have a current conveyor with a current gain greater than unity, therefore these types are used in some arrangements. Fig 13

This is a shunt feedback voltage output arrangement. The sampler is comprised of Rl, R3 and the CCII-. The sampler operates by coupling an output current that is set by the ratio of Rl and R4, this is because the voltage at the X output follows that of the Y input. Therefore with

R1=R4, the sampled current equals the current through Rl. The second conveyor, a CCII+ produces the correction current for the arrangement. Now the level of X current depends on the difference between the input voltage divided by the value of R4 and the sampled current. Therefore assuming a positive instantaneous input voltage, a current will flow out of the current sampler. Now the current flowing out of the CCII+ is Vin divided by the value of R4 minus the sample current, the sampled current bucks out the current due to the input voltage, i.e. the output of CCII+ is the difference and is a measure of the gain error A3. The error current flows out of Al and pre-distorts the drive to the output amplifier. In practice with the current gain of the two conveyors being unity, R4 would be adjusted to give the required balanced condition. For example if R2=50K and Rl=IK then R4 = 980.39ohms, ie a ratio 1.02. A point to note for this arrangement is that the input voltage drive is assumed to have zero output impedance. If this is not the case then a voltage buffer is required at the input of the arrangement or Rl reduced by a value equal to the source resistance. The shunt arrangements do not suffer from this limitation. The balance equation being R1/R4 = 1 + R1/R2, with a gain of -R2/Rl ifR3 = Rl. Fig 14

This is a voltage output series amplifier. Operation is the same as fig 16 but with the signal drive to the output amplifier and Rl, R4 are grounded, with the conveyors swapped in sign to give the current positive feedback loop. With CCl and CC2 having unity current gain, the balanced equation is R1/R4 = 1+R1/R2. The gain equals 1+R2/R1 if R3 = Rl. Fig 28

This shunt voltage output type is one of the simplest of arrangements. Here the first conveyor samples directly the current in Rl and compares this current with the current from the second conveyor, this current being set by the value of R3. The current gain required from CCl is greater than unity to give the balanced condition, and is equal to 1+R1/R2. R3 would typically be equal to Rl. The gain is 1 +R2/R1 if R3 = Rl. Fig 32 This arrangement is based on fig 47 but with the CCl being a unity current gain type of opposite sign due to the sample drive being coupled to the Y input of CCl. Here the sampling ratio of the current in Rl is set by the ratio of R4 and R5, with R4/R5=1+((R1+R4)/R2) the balanced condition is met. The gain is 1 + R2/R1 if R3 - Rl. Fig 34 In this arrangement the conveyors can both have unity current gain and also be inverting types. These two factors can help to reduce the inherent distortion of the current conveyors due to fewer active stages in the Z output path. The balanced equation is R6/R3 = 1+((R6+R1)/R2) Fig 38 This arrangement is the simplest using only one conveyor and one additional resistor R3. CCl samples directly the current in Rl and via its X input and compares this with the input voltage. CCl would typically have a current gain of x2. The balanced equation is given by 1+R1/R2+R1/RS = iZ/iX. The gain is Vo/Vin = 1+Rl/RS. With RS = infinite in value the gain is unity for any values of Rl or R2.

In general this invention has applications from DC to the Ghz range, with bandwidths far less limited by the speed (i.e. transition frequencies) of the active devices making up the linear amplifier. This invention is well suited to integrated circuit construction, with all the inherent advantages of ICs matching well the requirements of this invention, these being closely matched components that are both stable and /or predictable with temperature and stable with time. The linear amplifier requires stable and accurate resistors to define the various gains within the conveyor based embodiments, therefore thin film resistors would be most likely used. In general the signal comparator means could be integrated, with the output amplifier constructed using other means i.e., thick film, discrete devices etc. Other application however would be better served by integrating the complete linear amplifier.

Claims

1 According to the present invention there is provided a linear amplifier comprising: an output amplifier having an inverting input terminal and a non-inverting input terminal and an output for delivering output signal drive to a load ; a signal comparator means; a feedback current that is a function of the said output signal drive which is coupled to the inverting input of the said output amplifier; a first impedance means in which the said feedback current flows; with the action of the said signal comparator means being to generate an output correction current that is a function of the current in the first impedance means and the input voltage present at the input of the said linear amplifier, the said output correction current coupled to the inverting input of the said output amplifier, pre-distorting the total signal drive to the said output amplifier thus resulting in substantially reduced signal distortion in the said linear amplifier.

2 A linear amplifier as claimed in claim 1 wherein the said output signal drive is from source that has an output impedance that is relatively high compared to the load impedance and thus can be described a output signal current source, with the output signal being in the form of a current, the feedback current being a function of the said output current.

3 A linear amplifier as claimed in claim 1 wherein the said output signal drive is from a source that has an output impedance that is relatively low compared to the load impedance and thus can be described as a output signal voltage source, with the output signal being in the form of a voltage, the said feedback current being a function of the voltage across the load.

4 A linear amplifier as claimed in claim 2 wherein a second impedance means is provided having first and second terminals, with the second terminal coupled to the inverting input of the said output amplifier and the first terminal coupled to a signal common, the said signal comparator has first, second, third, forth and fifth terminals, the voltage difference between the first and second terminals of the said signal comparator forming the input of the said linear amplifier, the third terminal of the said signal comparator means coupled to the second terminal of the said first impedance means, the forth terminal of the said signal comparator coupled to the non-inverting input of the said output amplifier, the fifth terminal of the said signal comparator means coupled to the inverting input of the said output amplifier providing the said output correction current. 5 A linear amplifier as claimed in claim 3 wherein the said feedback current is provided by a second impedance means having first and second terminals, with the second terminal coupled to the inverting input of the said output amplifier and the first terminal coupled to a voltage that is a function of the voltage across the load ,the said signal comparator having first, second, third, forth and fifth terminals, the voltage difference between the first and second terminals of the said signal comparator forming the input of the said linear amplifier, the third terminal of the said signal comparator means coupled to the second terminal of the said first impedance means, the forth terminal of the said signal comparator coupled to the non-inverting input of the said output amplifier, the fifth terminal of the said signal comparator means coupled to the inverting input of the said output amplifier providing the said output correction current. 6 A linear amplifier as claimed in claims 4 and 5 wherein the said signal comparator has internal first and second links, with the first said link short circuiting terminals 1 to 3, the said second link short circuiting terminals 4 to 2, the said error current being a function of the voltage drop between terminals 3 and 5 of the said signal comparator, terminal 2 of the said signal comparator being coupled to the signal common of the said linear amplifier.

7 A linear amplifier as claimed in claims 4 and 5 wherein the said signal comparator has internal first and second links, with the said first link short circuiting terminals 3 to 2 of the said signal comparator, the said second link short-circuiting terminals 1 to 4 of the said signal comparator, the said error current being a function of the voltage drop between terminals 3 and 5 of the said signal comparator, terminal 2 of the said signal comparator being coupled to the signal common of the said linear amplifier. 8 A linear amplifier as claimed in claims 4 and 5 wherein the said signal comparator has an internal first link, with the said first link short- circuiting terminals 4 to 2 of the said signal comparator, the said error current being the current into terminal 3 of the said signal comparator means, terminal 2 of the said signal comparator being coupled to the signal common of the said linear amplifier.

9 A linear amplifier as claimed in claims 4 and 5 wherein the said signal comparator has an internal first link, with the said first link short- circuiting terminals 1 to 4 of the said signal comparator, the said error current being the current into terminal 3 of the said signal comparator means, terminal 2 of the said signal comparator being coupled to the signal common of the said linear amplifier. 10 A linear amplifier as claimed in claims 4 and 5 wherein the said signal comparator has an internal link, the said internal link short-circuiting terminals 1 to 3 of the said signal comparator.

11 A linear amplifier as claimed in claim 6 wherein a non-inverting, positive current feedback loop is formed comprising a current gain path and a current attenuation path, the said current gain path whose input is terminal 1 of the said first impedance means and whose output is terminal 5 of the said signal comparator with the gain being obtained within the said signal comparator , the said current attenuation path whose input is the node comprising terminal 2 of the said second impedance means, terminal 1 of the said first impedance means and the inverting input of the said output amplifier, and whose output is the coupling from the said node to terminal 1 of the said first impedance means. 12 A linear amplifier as claimed in claim 7 wherein a non-inverting, positive current feedback loop is formed comprising a current gain path and a current attenuation path, the said current gain path whose input is terminal 1 of the said first impedance means and whose output is terminal 5 of the said signal comparator with the gain being obtained within the said signal comparator , the said current attenuation path whose input is the node comprising terminal 2 of the said second impedance means with terminal 1 of the said first impedance means and the inverting input of the said output amplifier, and whose output is the coupling from the said node to terminal 1 of the said first impedance means.

13 A linear amplifier as claimed in claim 8 wherein a non-inverting, positive current feedback loop is formed comprising a current gain path and a current attenuation path, the said current gain path whose input is terminal 1 of the said first impedance means and whose output is terminal 5 of the said signal comparator with the gain being obtained within the said signal comparator , the said current attenuation path whose input is the node comprising terminal 2 of the said second impedance means with terminal 1 of the said first impedance means and the inverting input of the said output amplifier, and whose output is the coupling from the said node to terminal 1 of the said first impedance means.

14 A linear amplifier as claimed in claim 9 wherein a non-inverting, positive current feedback loop is formed comprising a current gain path and a current attenuation path, the said current gain path whose input is terminal 1 of the said first impedance means and whose output is terminal 5 of the said signal comparator with the gain being obtained within the said signal comparator , the said current attenuation path whose input is the node comprising terminal 2 of the said second impedance means with terminal 1 of the said first impedance means and the inverting input of the said output amplifier, and whose output is the coupling from the said node to terminal 1 of the said first impedance means.

15 A linear amplifier as claimed in claim 10 wherein a non-inverting, positive current feedback loop is formed comprising a current gain path and a current attenuation path, the said current gain path whose input is terminal 1 of the said first impedance means and whose output is terminal 5 of the said signal comparator with the gain being obtained within the said signal comparator , the said current attenuation path whose input is the node comprising terminal 2 of the said second impedance means with terminal 1 of the said first impedance means and the inverting input of the said output amplifier, and whose output is the coupling from the said node to terminal 1 of the said first impedance means.

16 A linear amplifier as claimed in claim 11 wherein the said signal gain path has a magnitude of gain equal to the gain magnitude of 1 + Z1/Z2, the said non-inverting positive current feedback loop having zero loop phase shift.

17 A linear amplifier as claimed in claim 12 wherein the said signal gain path has a magnitude of gain equal to the gain magnitude of 1 + Z1/Z2, the said non-inverting positive current feedback loop having zero loop phase shift.

18 A linear amplifier as claimed in claim 13 wherein the said signal gain path has a magnitude of gain equal to the gain magnitude of 1 + Z1/Z2, the said non-inverting positive current feedback loop having zero loop phase shift. 19 A linear amplifier as claimed in claim 14 wherein the said signal gain path has a magnitude of gain equal to the gain magnitude of 1 + Z1/Z2, the said non-inverting positive current feedback loop having zero loop phase shift.

20 A linear amplifier as claimed in claim 15 wherein the said signal gain path has a magnitude of gain equal to the gain magnitude of 1 + Z1/Z2, the said non-inverting positive current feedback loop having zero loop phase shift.

21 A linear amplifier as claimed in claim 16 wherein the said first impedance is a resistor and the said second impedance is a resistor. 22 A linear amplifier as claimed in claim 17 wherein the said first impedance is a resistor and the said second impedance is a resistor. 23 A linear amplifier as claimed in claim 18 wherein the said first impedance is a resistor and the said second impedance is a resistor.

24 A linear amplifier as claimed in claim 19 wherein the said first impedance is a resistor and the said second impedance is a resistor. 25 A linear amplifier as claimed in claim 20 wherein the said first impedance is a resistor and the said second impedance is a resistor. 26 A linear amplifier as claimed in claim 21 and 16 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, a fourth impedance means, with the said fourth impedance means connected between terminal 1 of the said signal comparator and to the X input of the said second current conveyor, the Y input of the said second current conveyor connected to terminal 5 of the said signal comparator, the Y input of the said first current conveyor connected to terminal 1 of the said signal comparator, the Z output of the said second current conveyor connected to the X input of the said first current conveyor, the said third impedance connected to the X input of the said first current conveyor and to terminal 2 of the said signal comparator, the Z output of the first said current conveyor connected to terminal 5 of the said signal comparator. 27 A linear amplifier as claimed in claim 27 wherein the said first current conveyor is a class II non-inverting type and the said second current conveyor is a class II inverting type, the said third impedance means is a resistor, the said fourth impedance means is a resistor.

28 A linear amplifier as claimed in claims 17 and 22 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, a fourth impedance means, with the said fourth impedance means connected between terminal 3 of the said signal comparator and the X input of the said second current conveyor, the Y input of the said second current conveyor connected to terminal 5 of the said signal comparator, the Y input of the said first conveyor current connected to terminal 1 of the said signal comparator, the Z output of the said second current conveyor connected to the X input of the said first conveyor, the third said impedance connected to the X input of the said first conveyor and to terminal 2 of the said signal comparator, the Z output of the first said current conveyor connected to terminal 5 of the said signal comparator.

29 A linear amplifier as claimed in claim 28 wherein the said first current conveyor is a class II inverting type and the said second current conveyor is a class Et non-inverting type, the said third impedance means is a resistor, the said fourth impedance means is a resistor.

30 A linear amplifier as claimed in claims 16 and 21 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, a fourth impedance means, with the said third impedance means connected between terminal 1 of the said signal comparator and the X input of the said first current conveyor, the Y input of the said first current conveyor connected to terminal 2 of the said signal comparator, the Y input of the said second current conveyor connected to terminal 5 of the said signal comparator, the Z output of the said second current conveyor connected to the X input of the said first conveyor, the said fourth impedance connected to the X input of the said second current conveyor and to terminal 1 of the said signal comparator, the Z output of the said first current conveyor connected to terminal 5 of the said signal comparator.

31 A linear amplifier as claimed in claim 30 wherein the said first current conveyor is a class II inverting type and the said second current conveyor is a class II non-inverting type, the said third impedance means is a resistor, the said fourth impedance means is a resistor.

32 A linear amplifier as claimed in claims 17 and 22 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, a fourth impedance means, with the said third impedance means connected between terminal 1 of the said signal comparator and the X input of the said first current conveyor, the Y input of the said first current conveyor connected to terminal 2 of the said signal comparator, the Y input of the said second current conveyor connected to terminal 5 of the said signal comparator, the Z output of the said second current conveyor connected to the X input of the said first conveyor, the said fourth impedance connected to the X input of the said second conveyor and to terminal 2 of the said signal comparator, the Z output of the first said current conveyor connected to terminal 5 of the said signal comparator. 33 A linear amplifier as claimed in claim 32 wherein the said first current conveyor is a class II non-inverting type and the said second current conveyor is a class II inverting type, the said third impedance means is a resistor, the said fourth impedance means is a resistor. 34 A linear amplifier as claimed in claims 18 and 23 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, the Y input of the said first current conveyor connected to terminal 2 of the said signal comparator, the Y input of the said second current conveyor connected to terminal 1 of the said signal comparator, the Z output of the said second current conveyor connected to the X input of the said first conveyor, the Z output of the said first current conveyor connected to terminal 5 of the said signal comparator, the said third impedance means connected to the X input of the said first current conveyor and to terminal 1 of the said signal comparator, the X input of the said second first current conveyor connected to terminal 3 of the said signal comparator. 35 A linear amplifier as claimed in claim 34 wherein the said first current conveyor is a class II inverting type and the said second current conveyor is a class II inverting type, the third impedance means is a resistor. 36 A linear amplifier as claimed in claims 19 and 24 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, the Y input of the said first current conveyor connected to terminal 2 of the said signal comparator, the Y input of the said second current conveyor connected to terminal 2 of the said signal comparator, the Z output of the said second current conveyor connected to the X input of the said first conveyor, the Z output of the said first current conveyor connected to terminal 5 of the said signal comparator, the said third impedance means connected to the X input of the said first current conveyor and to terminal 1 of the said signal comparator, the X input of the said second current conveyor connected to terminal 3 of the said signal comparator 37 A linear amplifier as claimed in claim 36 wherein the said first current conveyor is a class II non-inverting type and the said second current conveyor is a class II non-inverting type, the said third impedance means is a resistor.

38 A linear amplifier as claimed in claims 18 and 23 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, the Y input of the said first current conveyor connected to terminal 1 of the said signal comparator, the Y input of the said second current conveyor connected to terminal 1 of the said signal comparator, the Z output of the said second current conveyor connected to the X input of the said first conveyor, the Z output of the said first current conveyor connected to terminal 5 of the said signal comparator, the said third impedance means connected to the X input of the said first current conveyor and to terminal 2 of the said signal comparator, the X input of the said first current conveyor connected to terminal 3 of the said signal comparator.

39 A linear amplifier as claimed in claim 38 wherein the said first current conveyor is a class II non-inverting type and the said second current conveyor is a class II non-inverting type, the third impedance means is a resistor. 40 A linear amplifier as claimed in claims 19 and 24 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, the Y input of the said second current conveyor connected to terminal 2 of the said signal comparator, the Y input of the said first current conveyor connected to terminal 1 of the said signal comparator, the Z output of the said second current conveyor connected to the X input of the said first current conveyor, the Z output of the said first current conveyor connected to terminal 5 of the said signal comparator, the said third impedance means connected to the X input of the said first current conveyor and to terminal 2 of the said signal comparator, the X input of the said second current conveyor connected to terminal 3 of the said signal comparator. 41 A linear amplifier as claimed in claim 40 wherein the said first current conveyor is a class II inverting type and the said second current conveyor is a class II inverting type, the third impedance means is a resistor. 42 A linear amplifier as claimed in claims 18 and 23 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third current conveyor, a third impedance means, the Y input of the said second current conveyor connected to X input of the said third conveyor, the Y input of the said first conveyor connected to terminal 1 of the said signal comparator, the Y input of the said third conveyor connected terminal 1 of the said signal comparator, the X input of the said second current conveyor connected to terminal 3 of the said signal comparator, the said third impedance means connected to the X input of the said first current conveyor and to terminal 2 of the said signal comparator, the Z output of the said second current conveyor connected to the X input of the said first current conveyor, the Z output of the said third current conveyor connected to terminal 2 of the said signal comparator, the Z output of the said first current conveyor connected to terminal 5 of the said signal comparator. 43 A linear amplifier as claimed in claim 42 wherein the said first current conveyor is a class II non-inverting type and the said second current conveyor is a class I inverting type, the said third current conveyor is a class I non-inverting type, the third impedance means is a resistor. 44 A linear amplifier as claimed in claims 18 and 23 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third current conveyor, a third impedance means, the Y input of the said second current conveyor connected to X input of the said third conveyor, the Y input of the said third conveyor connected to terminal 1 of the said signal comparator, the Y input of the said first current conveyor connected terminal 2 of the said signal comparator, the X input of the said second current conveyor connected to terminal 3 of the said signal comparator, the said third impedance means connected to the X input of the said first current conveyor and to terminal 1 of the said signal comparator, the Z output of the said second current conveyor connected to terminal 2 of the said signal comparator, the Z output of the said third current conveyor connected to the X input of the said first current conveyor, the Z output of the said first current conveyor connected to terminal 5 of the said signal comparator.

45 A linear amplifier as claimed in claim 44 wherein the said first current conveyor is a class II inverting type and the said second current conveyor is a class I non-inverting type, the said third current conveyor is a class I non-inverting type, the third impedance means is a resistor.

46 A linear amplifier as claimed in claims 19 and 24 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third current conveyor, a third impedance means, the Y input of the said second current conveyor connected to X input of the said third conveyor, the Y input of the said third conveyor connected to terminal 2 of the said signal comparator, the Y input of the said first conveyor connected terminal 1 of the said signal comparator, the X input of the said second conveyor connected to terminal 3 of the said signal comparator, the said third impedance means connected to the X input of the said first current conveyor and to terminal 2 of the said signal comparator, the Z output of the said second current conveyor connected to terminal 2 of the said signal comparator, the Z output of the said third current conveyor connected to the X input of the said first current conveyor, the Z output of the said first current conveyor connected to terminal 5 of the said signal comparator.

47 A linear amplifier as claimed in claim 46 wherein the said first current conveyor is a class II inverting type and the said second current conveyor is a class I non-inverting type, the said third current conveyor is a class I non-inverting type, the third impedance means is a resistor.

48 A linear amplifier as claimed in claims 16 and 21 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third current conveyor, a third impedance means, a fourth impedance means, the Y input of the said second current conveyor connected to X input of the said third current conveyor, the Y input of the said first current conveyor connected terminal 2 of the said signal comparator, the X input of the said second current conveyor connected to terminal 5 of the said signal comparator, the said third impedance means connected to the X input of the said first current conveyor and to terminal 1 of the said signal comparator, the said fourth impedance means connected to terminal 1 of the said signal comparator and to the Y input of the said third current conveyor, the Z output of the said second current conveyor connected to terminal 2 of the said signal comparator, the Z output of the said third current conveyor connected to the X input of the said first current conveyor, the Z output of the said first current conveyor connected to terminal 5 of the said signal comparator.

49 A linear amplifier as claimed in claim 48 wherein the said first current conveyor is a class II inverting type and the said second current conveyor is a class I non-inverting type, the said third current conveyor is a class I non-inverting type, the third impedance means is a resistor, the fourth impedance means is a resistor.

50 A linear amplifier as claimed in claims 17 and 22 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third current conveyor, a third impedance means, a fourth impedance means, the Y input of the said second current conveyor connected to X input of the said third current conveyor, the Y input of the said first current conveyor connected terminal 2 of the said signal comparator, the X input of the said second current conveyor connected to terminal 5 of the said signal comparator, the said third impedance means connected to the X input of the said first current conveyor and to terminal 1 of the said signal comparator, the said fourth impedance means connected to terminal 2 of the said signal comparator and to the X input of the said third current conveyor, the Z output of the said second current conveyor connected to the x input of the said first current conveyor, the Z output of the said third current conveyor connected to terminal 2 of the said signal comparator, the Z output of the said first current conveyor connected to terminal 5 of the said signal comparator.

51 A linear amplifier as claimed in claim 50 wherein the said first current conveyor is a class II non-inverting type and the said second conveyor is a class I non-inverting type, the said third current conveyor is a class I non-inverting type, the third impedance means is a resistor, the fourth impedance means is a resistor.

52 A linear amplifier as claimed in claims 16 and 21 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third current conveyor, a third impedance means, a fourth impedance means, the Y input of the said second current conveyor connected to X input of the said third conveyor, the Y input of the said first current conveyor connected terminal 1 of the said signal comparator, the X input of the said second current conveyor connected to terminal 5 of the said signal comparator, the said fourth impedance means connected to the Y input of the said third current conveyor and to terminal 1 of the said signal comparator, the said third impedance means connected to terminal 2 of the said signal comparator and to the X input of the said first current conveyor , the Z output of the said second current conveyor connected to the x input of the said first current conveyor, the Z output of the said third current conveyor connected to terminal 2 of the said signal comparator, the Z output of the said first current conveyor connected to terminal 5 of the said signal comparator.

53 A linear amplifier as claimed in claim 52 wherein the said first current conveyor is a class II non-inverting type and the said second current conveyor is a class I non-inverting type, the said third current conveyor is a class I non-inverting type, the third impedance means is a resistor, the fourth impedance means is a resistor.

54 A linear amplifier as claimed in claims 17 and 22 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third current conveyor, a third impedance means, a fourth impedance means, the Y input of the said second current conveyor connected to X input of the said third conveyor, the Y input of the said first current conveyor connected terminal 1 of the said signal comparator, the X input of the said second current conveyor connected to terminal 5 of the said signal comparator, the said third impedance means connected to the X input of the said first current conveyor and to terminal 2 of the said signal comparator, the said fourth impedance means connected to terminal 2 of the said signal comparator and to the Y input of the said third current conveyor, the Z output of the said second current conveyor connected to terminal 2 of the said signal comparator, the Z output of the said third current conveyor connected to the X input of the said first current conveyor, the Z output of the said first current conveyor connected to terminal 5 of the said signal comparator.

55 A linear amplifier as claimed in claim 54 wherein the said first current conveyor is a class II inverting type and the said second conveyor is a class I non-inverting type, the said third current conveyor is a class I non- inverting type, the third impedance means is a resistor, the fourth impedance means is a resistor.

56 A linear amplifier as claimed in claims 19 and 24 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, the X input of the said first current conveyor connected to terminal 3 of the said signal comparator, the said third impedance means connected to the X input of the said second current conveyor and to terminal 2 of the said signal comparator, the Y input of the said first current conveyor connected to terminal 2 of the said signal comparator, the Y input of the said second current conveyor connected to terminal 1 of the said signal comparator, the Z output of the said first current conveyor connected to the terminal 5 of the said signal comparator, the Z output of the said second current conveyor connected to the X input of the said first current conveyor.

57 A linear amplifier as claimed in claim 56 wherein the said first current conveyor is a class II inverting type and the said second current conveyor is a class II inverting type, the third impedance means is a resistor.

58 A linear amplifier as claimed in claims 19 and 24 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, the X input of the said first current conveyor connected to terminal 3 of the said signal comparator, the said third impedance means connected to the X input of the said second current conveyor and to terminal 1 of the said signal comparator, the Y input of the said first current conveyor connected to terminal 2 of the said signal comparator, the Y input of the said second current conveyor connected to terminal 2 of the said signal comparator, the Z output of the said first current conveyor connected to the terminal 5 of the said signal comparator, the Z output of the said second current conveyor connected to the X input of the said first current conveyor.

59 A linear amplifier as claimed in claim 58 wherein the said first current conveyor is a class II inverting type and the said second current conveyor is a class II non-inverting type, the third impedance means is a resistor.

60 A linear amplifier as claimed in claims 19 and 24 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, a fourth impedance means, a fifth impedance means, the said third impedance means connected to the X input of the said second current conveyor and to terminal 2 of the said signal comparator, the fourth impedance means connected to the X input of the said first current conveyor and to terminal 3 of the said signal comparator, the said fifth impedance means connected to terminal 2 of the said signal comparator and to terminal 3 of the said signal comparator, the Y input of the said first current conveyor connected to terminal 2 of the said signal comparator, the Y input of the said second current conveyor connected to terminal 1 of the said signal comparator, the Z output of the said first current conveyor connected to the terminal 5 of the said signal comparator, the Z output of the said second current conveyor connected to the X input of the said first current conveyor.

61 A linear amplifier as claimed in claim 60 wherein the said first current conveyor is a class II inverting type and the said second current conveyor is a class II inverting type, the third impedance means is a resistor, the fourth impedance means is a resistor, the fifth impedance means is a resistor.

62 A linear amplifier as claimed in claims 19 and 24 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, a fourth impedance means, a fifth impedance means, the said third impedance means connected to the X input of the said second current conveyor and to terminal 1 of the said signal comparator, the said fourth impedance means connected to the X input of the said first current conveyor and to terminal 3 of the said signal comparator, the said fifth impedance means connected to terminal 2 of the said signal comparator and to terminal 3 of the said signal comparator, the Y input of the said first current conveyor connected to terminal 2 of the said signal comparator, the Y input of the said second current conveyor connected to terminal 2 of the said signal comparator, the Z output of the said first current conveyor connected to the terminal 5 of the said signal comparator, the Z output of the said second current conveyor connected to the X input of the said first current conveyor.

63 A linear amplifier as claimed in claim 62 wherein the said first current conveyor is a class II inverting type and the said second current conveyor is a class II non-inverting type, the third impedance means is a resistor, the fourth impedance means is a resistor, the fifth impedance means is a resistor.

64 A linear amplifier as claimed in claims 19 and 24 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, a fourth impedance means, a fifth impedance means, the said third impedance means connected to the X input of the said second current conveyor and to terminal 2 of the said signal comparator, said the fourth impedance means connected to terminal 2 of the said signal comparator and to terminal 3 of the said signal comparator, the said fifth impedance means connected to terminal 2 of the said signal comparator and to the X input of the said first current conveyor, the Y input of the said first current conveyor connected to terminal 3 of the said signal comparator, the Y input of the said second current conveyor connected to terminal 1 of the said signal comparator, the Z output of the said first current conveyor connected to the terminal 5 of the said signal comparator, the Z output of the said second current conveyor connected to the X input of the said first current conveyor.

65 A linear amplifier as claimed in claim 64 wherein the said first current conveyor is a class II non-inverting type and the said second current conveyor is a class II non-inverting type, the third impedance means is a resistor, the fourth impedance means is a resistor, the fifth impedance means is a resistor.

66 A linear amplifier as claimed in claims 19 and 24 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, a fourth impedance means, a fifth impedance means, the said third impedance means connected to the X input of the said second current conveyor and to terminal 1 of the said signal comparator, the said fourth impedance means connected to terminal 3 of the said signal comparator and to terminal 2 of the said signal comparator, the said fifth impedance means connected to terminal 2 of the said signal comparator and to the X input of the said first current conveyor, the Y input of the said first current conveyor connected to terminal 3 of the said signal comparator, the Y input of the said second current conveyor connected to terminal 2 of the said signal comparator, the Z output of the said first current conveyor connected to the terminal 5 of the said signal comparator, the Z output of the said second current conveyor connected to the X input of the said first current conveyor.

67 A linear amplifier as claimed in claim 66 wherein the said first current conveyor is a class II non-inverting type and the said second current conveyor is a class II inverting type, the third impedance means is a resistor, the fourth impedance means is a resistor, the fifth impedance means is a resistor.

68 A linear amplifier as claimed in claims 19 and 24 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, a fourth impedance means, a fifth impedance means, a sixth impedance means, the said sixth impedance connected to terminal 3 of the said signal comparator and to terminal 2 of the said signal comparator, the fourth impedance means connected to terminal 1 of the said signal comparator and to the Y input of the said second current conveyor, the said fifth impedance means connected to terminal 2 of the said signal comparator and to the Y input of the said second current conveyor, the said third impedance means connected to the X input of the said second current conveyor and to the X input of the said first current conveyor, the Y input of the said first current conveyor connected to terminal 3 of the said signal comparator, the Z output of the said second current conveyor connected to the terminal 5 of the said signal comparator, the Z output of the said first current conveyor connected to terminal 2 of the said signal comparator.

69 A linear amplifier as claimed in claim 68 wherein the said first current conveyor is a class II inverting type and the said second current conveyor is a class π inverting type, the third impedance means is a resistor, the fourth impedance means is a resistor, the fifth impedance means is a resistor, the sixth impedance means is a resistor.

70 A linear amplifier as claimed in claims 19 and 24 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, a fourth impedance means, a fifth impedance means, a sixth impedance means, the said sixth impedance connected to terminal 3 of the said signal comparator and to terminal 2 of the said signal comparator, the fourth impedance means connected to terminal 1 of the said signal comparator and to the Y input of the said second current conveyor, the said fifth impedance means connected to terminal 2 of the said signal comparator and to the Y input of the said second current conveyor, the said third impedance means connected to the X input of the said second current conveyor and to the X input of the said first current conveyor, the Y input of the said first current conveyor connected to terminal 3 of the said signal comparator, the Z output of the said first current conveyor connected to the terminal 5 of the said signal comparator, the Z output of the said second current conveyor connected to terminal 2 of the said signal comparator.

71 A linear amplifier as claimed in claim 70 wherein the said first current conveyor is a class II non-inverting type and the said second conveyor is a class II non-inverting type, the third impedance means is a resistor, the fourth impedance means is a resistor, the fifth impedance means is a resistor, the sixth impedance means is a resistor.

72 A linear amplifier as claimed in claims 14 wherein the said signal comparator consists of a first current conveyor, a third impedance means, the said third impedance means connected to pin 5 of the said signal comparator and to pin 2 of the said signal comparator, the Y input of the said current conveyor connected to terminal 1 of the said signal conveyor, the X input of the said current conveyor connected to terminal 3 of the said signal comparator, the Z output of the said current conveyor connected to terminal 5 of the said signal comparator.

73 A linear amplifier as claimed in claim 72 wherein the said first current conveyor is a class II inverting type.

74 A linear amplifier as claimed in claims 19 and 24 wherein the said signal comparator consists of a first current conveyor, a third impedance means, a fourth impedance means, the Y input of the said first current conveyor connected to terminal 1 of the said first current conveyor, the said third impedance means connected to the X input of the said current conveyor and to terminal 3 of the said signal comparator, the said fourth impedance means connected to terminal 3 of the said signal comparator and to terminal 2 of the said signal comparator, the Z output of the said first current conveyor connected to terminal 5 of the said signal comparator.

75 A linear amplifier as claimed in claim 74 wherein the said first conveyor is a class II inverting type, the third impedance means is a resistor, the fourth impedance means is a resistor.

76 A linear amplifier as claimed in claims 19 and 24 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, the said third impedance means connected to the X input of the said second conveyor and to the X input of the said first current conveyor, the Y input of the said first current conveyor connected to terminal 5 of the said signal comparator, the Y input of the said second current conveyor connected to terminal 1 of the said signal comparator, the Z output of the said second current conveyor connected to the terminal 5 of the said signal comparator, the Z output of the said first current conveyor connected to terminal 2 of the said signal comparator, terminal 3 of the said signal comparator connected to terminal 2 of the said signal comparator.

77 A linear amplifier as claimed in claim 76 wherein the said first current conveyor is a class II inverting type, the said second conveyor is a class II inverting type, the third impedance means is a resistor.

78 A linear amplifier as claimed in claims 19 and 24 wherein the said signal comparator consists of a first current conveyor, a second current conveyor, a third impedance means, the said third impedance means connected to the X input of the said second current conveyor and to the X input of the said first current conveyor, the Y input of the said first current conveyor connected to terminal 5 of the said signal comparator, the Y input of the said second current conveyor connected to terminal 1 of the said signal comparator, the Z output of the said second current conveyor connected to the terminal 2 of the said signal comparator, the Z output of the said first current conveyor connected to terminal 5 of the said signal comparator, terminal 3 of the said signal comparator connected to terminal 2 of the said signal comparator.

79 A linear amplifier as claimed in claim 78 wherein the said first current conveyor is a class II non-inverting type, the said second current conveyor is a class II non-inverting type, the third impedance means is a resistor.

80 A linear amplifier as claimed in claim 72 wherein the said signal gain path has a magnitude of gain equal to the gain magnitude of 1 + Z1/Z2 + Zl/ZS, where ZS is the third impedance means, the said non-inverting positive current feedback loop having zero loop phase shift. 81 A linear amplifier as claimed in claim 80 wherein the said first impedance means is a resistor, the said second impedance means is a resistor, the third impedance means is a resistor.

82 A linear amplifier as claimed in claim 25 wherein the said error current is a function of the voltage drop between terminals 3 and 5 of the said signal comparator.

83 A linear amplifier as claimed in claim 25 wherein the said error current is the current into terminal 3 of the said signal comparator means.

84 A linear amplifier substantially as described herein with reference to figures 4 to 49 of the accompanying drawings.