GB2400732A - Column transistor in a semiconductor device - Google Patents

Abstract

A column transistor of a sense amplifier includes an orthogonal matrix of a plurality of sets of four square active regions, bitlines and local datalines running perpendicular to each other, with each active region having two bitlines and one local dataline connected thereto, and the gate electrode with a bent portion, thereby increasing a width of the transistor, which in turn reduces a number of contacts of the column transistor and increases a channel width, to permit to arrange the column transistor in a small area that increases an area for the sense amplifier within a limited area, to increase a design tolerance as well as a fabrication tolerance in formation of contacts, which is favorable for high density device packing and enhancing a device operation performance.

Description

TITLE: COLUMN TRANSISTOR IN SEMICONDUCTOR DEVICE

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a semiconductor column transistor in a memory, and more particularly, to a column transistor in a semiconductor device, which transmits data on a bitline to a loca] data line or vice versa, of which layout is made efficiently for enhancing a device packing density.

Background of the Related Art

In a memory, a layout area of a sense amplifier is usually dependent on a size of a memory cell. Because of this reason, as the packing density of the memory increases the more, the size of the memory cell gets reduced the more, and the size of the sense amplifier which senses and amplifies a data in the memory cell is also reduced the more in proportion to the size reduction of the memory cell. This size reduction of the sense amplifier lowers a driving performance of t'ne sense amplifier as well. It is very important to increase an operative frequency of the memory in correspondence with the operative frequency of a recent microprocessor which is well over the operative frequency of the memory. The present invention provides a method for enhancing a driving performance of the sense amplifier as one of method for increasing the operative frequency of the memory. The present invention also provides a method for making an effective layout of the column transistors located between the bitlines and the local datelines, for maximizing a layout area of the sense amplifiers located between the bitlines.

FIG. 1 illustrates a circuit diagram of related art column transistors, showing an example of the column transistors each with a width of 2.28cm.

A plurality of bitlines Biti, BitBi, Bitj, and BitBj in pairs are arranged in one direction, and a plurality of local data(bus) lines LDBi, LDE3Bi, LDBj, and LDBBj are connected to the column transistors(CTI CT8). As shown, the data on the bitline Biti is transferred to the local dateline LDBj through nodes Nl and N2 by the column transistors CTI and CT5, the data on the bitline Bitj is transferred to local dateline LDBBj through nodes N3 and N4 by the column transistors CT2 and CT6, the data on the bitline BitBi is transferred to the local dateline LDBBi through nodes N5 and N6 by the column transistors CT3 and CT7, and the data Oil the bitline BitBj is transferred to local dateline LDBj through nodes N7 and N8 by the column transistors CT4 and CT8. That is, there are data transmission paths of Biti CTI LDBi, Bitj CT2 LDBBj, BitBi CT3 LDBBi, and BitBj CT4 LDBj.

A layout of such column transistors will be discussed with reference to FIGS. 2 and 3.

Rectangular shaped active regions 10 are arranged on a semiconductor substrate in a check pattern. Ofthem, four adjacent active regions 10 constitute one set. Each active region has a gate electrode 12 crossed for two times each with a 1.14 width to make 2.28 width in total, and four gate electrodes 12 constituting one set are connected into one to form column transistors CTl CT4, respectively. Bitlines 14, Biti, Bitj, BitBi, and BitBj, are sequentia!!y arranged in one direction at both sides of upper and lower portions between the adjacent active regions 10, and each ofthe bitlines 14 is in contact with the active region 10 via two contacts BC. Local datelines 16, LDBi, LDBBj, LDBBi, LDBj, are arranged in a direction perpendicular to the bitlines 14, and tvo of the local datelines 16 overlap the active regions 10. Each ofthe local datelines 16 is in contact with the active region 10 ofthe column transistors CTI CT4 via a local dateline contact LDBC. The gate electrodes 12 in the column transistors CT l CT4 are connected by metal lines 18 and netal contacts MC. The foregoing stncture is repeated.

Since the related art column transistor can not reduce the area of the column transistors connected to the sense amplifiers, with consequential difficulty in making an effective layout of the sense amplifiers within a given area, packing devices to a high density and an enhancement of operating performance are failed.

SUMMARY OF TIlE Il\VENTIOIV

Accordingly, the present invention is directed to a column transistor in a semiconductor device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.

An object of the present invention is to provide a method for making a layout of column transistors which is favorable for packing devices to a high density, and enhance operation characteristics.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the column transistor in a semiconductor device includes a sense amplifier connecting to a local dateline and a bitline, wherein either a source or a drain region of the column transistor is shared with either a source or drain region of an adjacent sense amplifier column transistor active region.

A gate electrode of the column transistor is bent in an active region of the column transistor, thereby increasing a width of the transistor, the gate electrode is bent in a character form, all the gate electrodes of column transistors connected to one sense amplifier are shared, the gate electrode is in contact with one metal wiring at one point, and the active region of the column transistor is in contact with two bitlines and one local dateline.

In another aspect of the present invention, there is provided a column transistor in a semiconductor device including an orthogonal matrix of a plurality of sets of four square active regions, a gate electrode having a bent portion overlapped with the set, and connected to a metal wiring in common with the column transistors connected to the same sense amplifier, bitlines four of which are running over one of the active regions and only two of which are in contact with the active region, and local datelines running in a direction perpendicular to the bitlines, two of which are running over the active region and only one of which is in contact with the active region.

The gate electrode is bent in a character form.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention: FIG. I is a circuit diagram illustrating related art sense amplifier column transistors; FIG. 2 is a layout illustrating the circuit in FIG. 1; FIG. 3A is a layout illustrating the active regions and the gate electrodes in FIG. 2; FIG. 3B is a bitline layout in FIG. 2; FIG. 3C is a local data busline layout in FIG. 2; FIG. 4 is a circuit diagram illustrating a sense amplifier column transistor in accordance with a preferred embodiment of the present invention; FIG. 5 is a layout illustrating the circuit in FIG. 4; FlCr. 6A is a layout illustrating the active regions and the gate electrodes in FIG. 5; FIG. 6B is a bitline layout in FIG. 5; and, FIG. 6C is a layout illustrating the local data busline in FIG. 5.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

The circuit diagram of the column transistor of the present invention is similar to the same of the related art, wherein, as shown in FIG. 4, a layout of local datelines is changed to an order of LDBi, LDBBj, LDBBi, LDBj, which layout is characteristic of the present invention.

FIG. 5 illustrates a layout of the circuit in FIG. 4, FIG. 6A illustrates a layout of the active regions and the gate electrodes in FIG. 55 FIG. 5B illustrates a bitline layout in rIG.

5, and FIG. 6C illustrates a layout of the local data busline in FIG. 5.

Four adjacent column transistors constitute one set to share active regions 20, and the active regions 20 of adjacent two sets of column transistors CTI CT4 and CT5 CT8 are formed to share source/drain regions with adjacent sense amplifier column transistors. Gate electrodes 22 having a n shape, such as ''U " or " ", are arranged appropriately on each active region 20, such that four of the gate electrodes as one set share it. Bitlines 24, Bitj, BitBj, BitBi, and Biti, are arranged in one direction above the active regions 20 overlapping therewith, and local data lines 26 are arranged in an order of LDBi, LDBBj, LDBBi, LDBj starting from one side to the other in a direction perpendicular to the bitlines 24. A metal wiring 28 is formed over a portion between adjacent active regions 20 in a direction parallel to the bitlines 24. The bitlines 24 are connected to one active region 20 through two bitline contacts BC, and the local dateline 26 is connected to one active region 20 through one local dateline contact LDC, and one set of column transistors are connected to the metal wiring 28 through a metal wiring contact MC. That is, four square active regions are repeatedly arranged in a check pattem, each active region has two bitlines each one on an upper side and a louver side connected thereto, and one local dateline is connected to a center of the active region. Thus, two column transistors share either one source or drain region.

According to the foregoing layout, a gate electrode with a 1.141lm width in the same with the related art provides a transistor width in a range of approx. 3.35pm. This implies an increased size of the column transistor by approx. 47%, together with an area reduction coming from a reduction of the number of contacts by one half of the related art.

As has been explained, in the sense amplifier column transistor of the present invention, by providing an orthogonal matrix of a plurality of sets of four square active regions, bitlines and local datelines running perpendicular to each other, with each active region having two bitlines and one local dateline connected thereto, and the gate electrode with a bent portion, since a width of the transistor can be increased, which reduces a number of contacts of the column transistor and increases a channel width, to permit to arrange the column transistor in a small area that increases an area for the sense amplifier within a limited area, a design tolerance as well as a fabrication tolerance in formation of contacts can be increased, which is favorable for high density device packing and enhancing a device operation performance.

It will be apparent to those skilled in the art that various modifications and variations can be made in the column transistor in a semiconductor device of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within tile scope of the appended claims and their equivalents.

Claims (5)

1. A semiconductor device comprising: an orthogonal matrix of gate electrodes, each gate electrode comprising four portions with bends to form closed loops, each of the closed loops being fonned on one of four separate active regions and defining four separate column transistors, the four column transistors comprising a set of transistors, wherein the gate electrodes are electrically inter-connected to one another; a plurality of parallel bit lines, four bit lines running over each set of transistors, only two of the four bit lines being in contact with any single active region; a plurality of parallel local data lines, the local data lines running in a direction substantially perpendicular to the bit lines, four local data lines running over each set of transistors, only two local data lines running over any single active region, and only one local data line being in contact with any single active region.

2. The semiconductor device as claimed in claim 1, wherein each of the closed loops has a shape of"U".

3. The semiconductor device as claimed in claim 1, wherein the interconnected gate electrodes are connected to a metal wiring through a single contact.

4. The semiconductor device as claimed in claim 1, wherein the bit lines are in contact with the active regions inside the closed loops.

5. A column transistor in a semiconductor device comprising: an orthogonal matrix of a plurality of sets of four square active regions; gate electrodes having a n or "U" formed portion overlapped with the active region, adjacent four of which constitute one set in a form connected with one another and are connected to one sense amplifier; bit lines running in one direction such that a first bit line, a first complementary bit line, a second bit line and a second complementary bit line adjacent to one another are sequentially overlapped with one of the active regions, two of the four bit lines being in contact with the one active region; and local data lines running in a direction perpendicular to the bit lines such that two of the local data. lines are running over one active region, only one of which is in contact with the active region, Levity one set ol four local data lines arranged in an order of adjacent first local data line, second complementary local data line, first complementary local data line, and second data line starting from a right side of one set of four active regions.