GB2400709B - System and method for programming ONO dual bit memory cells - Google Patents

System and method for programming ONO dual bit memory cells

Info

Publication number
GB2400709B
GB2400709B GB0417770A GB0417770A GB2400709B GB 2400709 B GB2400709 B GB 2400709B GB 0417770 A GB0417770 A GB 0417770A GB 0417770 A GB0417770 A GB 0417770A GB 2400709 B GB2400709 B GB 2400709B
Authority
GB
United Kingdom
Prior art keywords
programming
memory cells
bit memory
dual bit
ono dual
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0417770A
Other versions
GB0417770D0 (en
GB2400709A (en
Inventor
Darlene Hamilton
Timothy Thurgate
Janet S Y Wang
Michael K Han
Narbeh Derhacobian
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/050,483 external-priority patent/US6567303B1/en
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of GB0417770D0 publication Critical patent/GB0417770D0/en
Publication of GB2400709A publication Critical patent/GB2400709A/en
Application granted granted Critical
Publication of GB2400709B publication Critical patent/GB2400709B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
    • G11C16/3409—Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5657—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using ferroelectric storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5671—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
GB0417770A 2002-01-16 2002-12-17 System and method for programming ONO dual bit memory cells Expired - Fee Related GB2400709B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/050,483 US6567303B1 (en) 2001-01-31 2002-01-16 Charge injection
PCT/US2002/040775 WO2003063167A2 (en) 2002-01-16 2002-12-17 System and method for programming ono dual bit memory cells

Publications (3)

Publication Number Publication Date
GB0417770D0 GB0417770D0 (en) 2004-09-15
GB2400709A GB2400709A (en) 2004-10-20
GB2400709B true GB2400709B (en) 2005-12-28

Family

ID=27609070

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0417770A Expired - Fee Related GB2400709B (en) 2002-01-16 2002-12-17 System and method for programming ONO dual bit memory cells

Country Status (8)

Country Link
JP (1) JP2005516330A (en)
KR (1) KR20040071322A (en)
CN (1) CN100433193C (en)
AU (1) AU2002367512A1 (en)
DE (1) DE10297641T5 (en)
GB (1) GB2400709B (en)
TW (1) TWI260639B (en)
WO (1) WO2003063167A2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6967873B2 (en) 2003-10-02 2005-11-22 Advanced Micro Devices, Inc. Memory device and method using positive gate stress to recover overerased cell
US7307878B1 (en) 2005-08-29 2007-12-11 Spansion Llc Flash memory device having improved program rate
US8358543B1 (en) 2005-09-20 2013-01-22 Spansion Llc Flash memory programming with data dependent control of source lines
US7957204B1 (en) 2005-09-20 2011-06-07 Spansion Llc Flash memory programming power reduction
US7433228B2 (en) 2005-09-20 2008-10-07 Spansion Llc Multi-bit flash memory device having improved program rate
KR100666223B1 (en) * 2006-02-22 2007-01-09 삼성전자주식회사 Three-level nonvolatile semiconductor memory device for decreasing noise between memory cells and operating method therefor
US7969788B2 (en) * 2007-08-21 2011-06-28 Micron Technology, Inc. Charge loss compensation methods and apparatus
CN111863086B (en) * 2019-04-29 2022-07-05 北京兆易创新科技股份有限公司 Method and device for controlling programming performance

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5675537A (en) * 1996-08-22 1997-10-07 Advanced Micro Devices, Inc. Erase method for page mode multiple bits-per-cell flash EEPROM
US6011725A (en) * 1997-08-01 2000-01-04 Saifun Semiconductors, Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6044022A (en) * 1999-02-26 2000-03-28 Tower Semiconductor Ltd. Programmable configuration for EEPROMS including 2-bit non-volatile memory cell arrays
US6307784B1 (en) * 2001-02-28 2001-10-23 Advanced Micro Devices Negative gate erase
WO2001084552A2 (en) * 2000-05-04 2001-11-08 Saifun Semiconductors Ltd. Programming of nonvolatile memory cells
WO2002071410A2 (en) * 2001-02-28 2002-09-12 Advanced Micro Devices, Inc. Higher program threshold voltage and faster programming rates based on improved erase methods
WO2003001530A2 (en) * 2001-06-21 2003-01-03 Advanced Micro Devices, Inc. Erase method for dual bit virtual ground flash

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5870335A (en) * 1997-03-06 1999-02-09 Agate Semiconductor, Inc. Precision programming of nonvolatile memory cells

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5675537A (en) * 1996-08-22 1997-10-07 Advanced Micro Devices, Inc. Erase method for page mode multiple bits-per-cell flash EEPROM
US6011725A (en) * 1997-08-01 2000-01-04 Saifun Semiconductors, Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6044022A (en) * 1999-02-26 2000-03-28 Tower Semiconductor Ltd. Programmable configuration for EEPROMS including 2-bit non-volatile memory cell arrays
WO2001084552A2 (en) * 2000-05-04 2001-11-08 Saifun Semiconductors Ltd. Programming of nonvolatile memory cells
US6307784B1 (en) * 2001-02-28 2001-10-23 Advanced Micro Devices Negative gate erase
WO2002071410A2 (en) * 2001-02-28 2002-09-12 Advanced Micro Devices, Inc. Higher program threshold voltage and faster programming rates based on improved erase methods
WO2003001530A2 (en) * 2001-06-21 2003-01-03 Advanced Micro Devices, Inc. Erase method for dual bit virtual ground flash

Also Published As

Publication number Publication date
AU2002367512A1 (en) 2003-09-02
GB0417770D0 (en) 2004-09-15
DE10297641T5 (en) 2005-01-05
TWI260639B (en) 2006-08-21
JP2005516330A (en) 2005-06-02
GB2400709A (en) 2004-10-20
CN1628358A (en) 2005-06-15
KR20040071322A (en) 2004-08-11
CN100433193C (en) 2008-11-12
TW200302486A (en) 2003-08-01
WO2003063167A2 (en) 2003-07-31
WO2003063167A3 (en) 2003-12-04

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Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)

Free format text: REGISTERED BETWEEN 20150618 AND 20150624

PCNP Patent ceased through non-payment of renewal fee

Effective date: 20181217