TW200302486A - Charge injection - Google Patents

Abstract

A system and methodology is provided for programming first bit (C0, C2, C4, C6) and second bit (C1, C3, C5, C7) of a memory array (68) of dual bit memory cells (10, 82, 84, 86, 88) at a substantially high delta VT. The substantially higher VT assures that the memory array (68) will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. At a substantially higher delta VT, programming of the first bit (C0, C2, C4, C6) of the memory cell (10, 82, 84, 86, 88) causes the second bit (C1, C3, C5, C7) to program harder and faster due to the shorter channel(8) length. Therefore, the present invention employs selected gate and drain voltages and programming pulse widths during the first bit (C0, C2, C4, C6) and second bit (C1, C3, C5, C7) that assures a controlled first bit VT and slows down programming of the second bit (C1, C3, C5, C7). Furthermore, the selected programming parameters keep the programming times short without degrading charge loss.

Description

200302486 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates generally to a memory system, and more particularly to an electronic device using a virtual ground architecture and having a two-bit memory transistor unit. System and method for programming and erasing several bit sectors in flash memory device. [Previous Technology] Flash memory is an electronic memory medium that can be rewritten and retains its contents without power. Flash memory devices typically have a useful life of 100,000 to 300,000 write cycles. And erasable single byte dynamic memory access memory (D y n a m 丨 c R a n d 0 m A c c e s s Memory; DRAM for short) and static machine access memory (static

Random Access Memory (abbreviated as SRAM) memory chips are different. Usually, flash memory is erased and written in blocks or sections with multiple bits. The flash memory system can be erased from its original position.

Programmable Read Only Memory (EEPR0M for short) has evolved. Flash memory has lower cost and higher component density. This new type of EEPR0M has been developed into an important non-volatile memory that combines eprom's high component density and E E P R 0 M which can electrically erase these two advantages. ▶ The traditional flash memory system is constructed with a memory cell structure that stores a single bit of information in each memory cell. In this single-bit memory architecture, each memory cell usually includes a metal oxide semiconductor (Metal Oxide Semiconductor; M0s) transistor junction.

92257.ptd Page 7 200302486 V. Description of the invention (2) The structure has a source, a drain, and a channel in a substrate or a P-type well, and a stacked type covering the channel Gate structure. The stacked gate may further include a thin gate dielectric layer (sometimes referred to as a tunnel oxide) formed on the surface of the P-well. The stacked gate also includes a polycrystalline silicon floating gate overlying the tunnel oxide and a polycrystalline silicon interlayer dielectric layer overlying the floating gate. The dielectric layer i between the polycrystalline silicon is often a multilayer insulator, such as an oxide-nitride-oxide (Oxide-Nitride-Oxide; abbreviated 0N0) layer having two oxide layers with a nitride layer sandwiched therebetween. Finally, a polycrystalline gate is overlaid on the dielectric layer between the polycrystalline silicon. The control gate is connected to a word line associated with a row of such memory cells to form sections of such memory cells in a typical NOR configuration. In addition, the memory early elements of the '> and polar regions are connected together by a conductive bit line. The channel of the memory cell conducts current between the source and the drain according to the electric field generated in the -channel by the stacked gate structure. In this NOR configuration, each drain terminal of each transistor in a single row is connected to the same bit line. In addition, each flash memory cell has its stacked gate terminals connected to a different word line, and all flash memory cells in the array have its source terminals connected to a common source terminal. In the operation, the individual flash # memory unit is addressed by using the surrounding decoder and control circuit through the respective bit lines and word lines in order to perform programming (writing), reading, or erasing functions. . This single-bit stacked gate flash memory cell applies a voltage to the control gate, grounds the source, and connects the drain to

92257.ptd Page 8 200302486 V. Description of the invention (3) The predetermined potential of the source potential is programmed. The high electric field created across the tunnel oxide ends can cause a phenomenon known as n F 0 w 1 e r-N 0 r d h e i mπ tunneling effect. In this process, the electrons in the central memory early channel region pass through the gate oxide and enter the floating gate, and are trapped in the floating gate. This is because the floating gate is blocked by the polycrystalline silicon medium. And surrounded by tunnel oxides. Due to the trapped electrons, the critical voltage of the memory cell is increased. The change in the threshold voltage of the memory cell (and the resulting change in the channel conductivity) caused by the trapped electrons causes the memory cell to be programmed. In order to erase a typical single-bit stacked gate flash memory cell, a voltage is applied to the source and the control gate is held at a negative potential while the drain is allowed to float. Under these conditions, an electric field is generated across the tunnel oxide between the floating gate and source. The electrons originally trapped in the floating gate flow toward the portion of the floating gate covering the source region, and cluster in this part, and are taken out from the floating gate and removed at F ow. 1 er-Ν rdheim enters the source region through the tunnel oxide under the tunneling effect. When the electrons are removed from the floating gate, the memory cell is erased. In a conventional single-bit flash memory device, an erase confirmation is performed in order to determine whether each memory cell in a block or a group of such memory cells has been erased correctly. The current single-bit erasure confirmation method provides erasure of confirmation bits or memory cells, and applies supplementary erasure pulses to individual memory cells. This method cannot pass the initial confirmation. Then confirm the status of the erased memory unit again and continue the process.

92257.ptd Page 9 200302486 V. Description of the invention (4) until the memory unit or bit is successfully erased or the memory unit is marked as unusable. Recently, a two-bit flash memory unit has been used, which can store two bits of information in a single memory unit. The traditional programming and erase confirmation methods used in the single-bit stacked gate architecture are not applicable to such two-bit devices. Recently, a two-bit flash memory structure that does not use a polysilicon spring gate has been used, such as an ON0 flash memory device that uses a polysilicon layer above the ON0 layer to provide word line connections. Traditional technology has never mentioned the characteristics associated with such devices. Because of the need for new and improved programming and erasing methods and systems in this technical field, such new and improved programming and erasing methods and systems will ensure proper programming and erasing of the dual-bit memory virtual ground The bits of data in a structure and the structural characteristics of such a structure. [Summary]-The present invention provides a system and method for programming the first and second bits of a two-bit memory cell of a memory array under a relatively high voltage difference (delta VT). The relatively high VT guarantees that after a relatively long period of time after high temperature stress and / or customer operation, the memory array can still maintain the programmed data and erase the data. At a higher voltage difference, programming the first bit of the memory cell makes programming the second bit less difficult and faster due to the shorter channel length. Therefore, during the programming of the first and second bits, the present invention uses the selected gate and drain voltages and the programming pulse width. This method ensures a controlled first bit V T, and Slowed down to second place

92257.ptd Page 10 200302486 V. Description of the invention (5) Meta programming. In addition, these selected programming parameters can keep programming time short without degrading charge loss. The present invention can perform efficient and thorough programming, erasing, and confirming, thereby minimizing the problems of data retention and excessive erasure that are similar to those in a 0N0 double-bit memory cell architecture. The present invention provides significant advantages when applied in a manner that is associated with a two-bit memory cell formed using a 0NO architecture. However, we should understand that the present invention has its utility in relation to the architecture of the two-bit memory cell, and the present invention is not limited to the implementation or configuration of any particular two-bit memory cell. Although the charge associated with programming a single bit in a two-bit memory cell is isolated, the charge will make the programming of the associated memory cell less difficult to change, making the memory cell more difficult to erase . For example, the residual charge may accumulate in the central area of the memory cell, and the memory cell cannot be erased in the normal way of erasing the bits individually. Therefore, the system and method include programming, cancer recognition, and erasing of normal bits and complementary bits (c0 in p 1 i m n t a r y bit) of two opposite ends of the same ONO transistor of the memory cell. The erasing includes applying a set of erasing pulse waves to the normal bit and the complementary bit in a single two-bit memory cell. The group of erasing pulse waves is erased by one end applied to both ends of the transistor, followed by a single-end erased pulse applied to one end, and a single-end erased pulse applied to the other end. Waves (composed). In one aspect of the present invention, a system and method for confirming erasure of a dual-bit flash memory unit of a memory array are provided. The system and method include: pre-programming one of each normal row position and complementary row position

92257.ptd Page 11 200302486 V. Description of the invention (6) Bits; then confirm the erasure of the bits in each normal and complementary bit row position. The disc erasure requires that the position of each bit address be confirmed by the erasure before moving to the next address. In addition, erase confirmation can be performed on bits of the I / 0 or word line so that before moving to the next I / 0 or word line, both the normal and complementary bits of the I / 0 must be confirmed by erase. If the location of the address is not lower than the maximum VT used to define the blank state, a set of erase pulses k is applied. This set of erasing pulse waves includes erasing the pulse waves at both ends of a bit applied to the normal and complementary row positions for a specified duration (for example, 10 milliseconds), and then for a specified duration (for example, 1 millisecond) One of the bits in one of the row positions applied to the normal # position and the complementary row position in the first single-ended erase pulse, and applied to the normal row position and the complement for a specified duration (eg, 1 millisecond) The second single-ended erase of the bit in the other row position of the row position erases the pulse wave. These confirmation and erasing steps are repeated until each normal bit and complementary bit in a segment is lower than the maximum VT used to define a blank note unit. These steps are then repeated for each segment. These bits are then evaluated to determine if they have been over-erased or below the minimum VT used to define a blank memory cell. A soft program pulse is provided to these bits which have been determined to have been over-erased. The soft ball type should include a low level source voltage in order to turn off leakage current from other memory cells on the same line. Perform a second or final confirmation erase procedure on the bits in the normal row position and the complementary row position to ensure that the soft program pulse does not raise the bits above the maximum VT used to define a blank memory cell .

92257.ptd Page 12 200302486 V. Description of the Invention (7) In order to achieve the foregoing and related purposes, the present invention includes features fully described herein and clearly indicated in the scope of the patent application. The description and drawings that follow set forth certain illustrative aspects and embodiments of the invention in detail. However, these aspects and embodiments are merely some of the various ways in which the principles of the invention may be employed. The other objects, advantages, and innovative features of the present invention can be easily understood by referring to the following detailed description of the present invention and the accompanying drawings. [Embodiment] The following is a detailed description of the present invention with reference to the drawings. The present invention provides a method and system for programming (writing), confirming (reading), and correctly erasing a two-bit memory cell operating in a two-bit mode. The present invention can be used in conjunction with a chip erase or sector erase operation in a flash memory device. In addition, the present invention provides a method and system for correctly configuring and maintaining two-bit memory cells in an array operating in a two-bit mode. Although the present invention is shown and described in the following in association with the 0N0 two-bit memory cell architecture using two bits of each memory cell for data storage, we should understand that the present invention can also be applied Used in other types of architectures and other dual-bit architectures. Referring now to the drawings, Figure 1 illustrates one example of a dual bit memory cell (1 0) in one or more of the various aspects in which the present invention can be implemented. The memory unit (10) includes a silicon nitride layer (16), which is sandwiched between the upper silicon dioxide layer (14) and the lower silicon dioxide layer (18), and these The three layers constitute the ON layer (30). A polycrystalline silicon layer (12) is disposed on the ON layer (30) and provides a memory cell (10).

92257.ptd Page 13 200302486 f V. Description of the invention (8) Word line connection. The first bit line (32) is located under the 0N layer (30) under the first area (4), and the second bit line (34) is located under the second area (6) Under the 0N layer (30). The bit lines (32) and (34) are composed of a conductive portion (24) and a freely selectable oxide portion (22). A boron ion implant (20) is provided on each end of each bit line (32) and (34), and the bit lines are in contact with the lower silicon oxide layer ( 1 8) Or along the entire transistor. The doping concentration of these boron ion core implants is higher than the doping concentration of the P-type substrate and helps to control the VT of the memory cell (10). The memory unit (10) is provided on a P-type substrate ¥ (9), and the conductive portion (24) 5 of the bit lines (3 2) and (34) is formed by using an N + arsenic ion implant. A channel (8) is formed across the P-type substrate. The memory unit (10) is composed of a single transistor having a drain electrode of an exchangeable source formed by the N arsenic ion implanted portion (2 4), and the N arsenic ion input portion (2 4) The gate is formed on the P-type substrate region (9) together with a gate formed as a part of the polycrystalline silicon word line (1 2). Although the first and second bit lines (32) and (34) are illustrated relative to the conductive portion (24) and the freely selectable oxide portion (22), we should understand that it is also possible to use only the conductive portion Form such bit lines.该 夕 # Although Figure 1 shows several gaps in the silicon nitride layer (16), we should understand that the nitrided layer (1) can also be manufactured in a single strip or single layer without gaps (1 6). The silicon nitride layer (16) forms a charge trap layer. The memory cell is programmed by applying a voltage to the drain and gate and grounding the source.

92257.ptd Page 14 200302486 F. This layer C to the near-kilth near-motion CC can be} 极 可 端 位 #, description of the invention (9) The voltage generates an electric field along this channel, which accelerates the electrons and automatically The substrate (9) jumps into the nitride, and this phenomenon is called hot electron injection. Because the electrons get most of their energy on the drain, the electrons are trapped and remain stored at the nitride layer of the electrode. The memory unit (10) is usually uniform, and the pole and source are interchangeable. Because the silicon nitride is not conductive, a charge (26) can be injected into the nitride (16) at an end near the central region (5), and a second charge (2 8) can be injected into the nitride (16). At the second end of the central area (5). Therefore, if the bits are not shifted, each memory cell can have two bits instead of one. As described above, the first charge (2 6) can be stored at the first end of the central region (5) in the nitride layer 16), and the second charge 2 8) can be stored in the nitride layer ( The second end of the central area (5) in 16), so each memory unit (10) may have two bits. The dual-bit memory cell (1 0) is generally symmetrical, so the drain and source are swapped. Therefore, when programming the left azimuth element C 0, the first bit line (3 2 can be used as the drain terminal, and the second bit line (34) can be used as the source end. Similarly, when programming the right azimuth element C 1 At the same time, the second bit line (34) is used as the drain terminal, and the first bit line (32) can be used as the source. The first bit is used to pair the first bit C0 and the second bit. C1's binary memory unit (1 0) performs reading, programming, and single-ended erasing of a set of voltage parameters.

92257.ptd Page 15 200302486 Brick V. Explanation of the invention (ίο) Table 1 Gate bit line 0 bit line 1 of the working memory unit Note 1 Read C0 Vcc 0 volt 1.2 volt Extra line Read C1 Vcc 1.2 volt 0 volt Normal Line programming CO 9.25 to 9.5 volts 5 to 5.5 volts 0 volts hot electron programming C1 9.25 to 9.5 volts 0 volts 5 to 5.5 volts thermal electron single-ended erase CO -3 to -6 volts 5 to 6 volts floating hot electron injection single End erase C1 -3 to -6 volts Floating 5 to 6 volts Hot electron injection End erases Cl'CO -3 to -6 volts 5 to 6 volts 5 to 6 volts Hot electron injection φ Or various embodiments that implement a two-bit memory cell architecture. The present invention is particularly applicable to a memory device using two bits of a two-bit memory unit for data or information storage. In the present invention, the inventors have discovered that programming and erasing a bit (such as bit C0) in such a memory unit will cause the associated bit (such as also element C1) of the bit to be programmed and erased. (Or) erase. For example, reprogramming of bit C 1 of memory cell (10) may cause charge accumulation in bit C 0 and vice versa. In addition, repeatedly applying the erase voltage pulse to the bit C1 may cause excessive erasure of the bit C0. These phenomena in the associated bit C0 will in turn cause a decrease in the performance of these bit operations in normal operations (for example, ^ ♦ also read, write / program, and / or erase one or two Bit capabilities). In the present invention, by selectively programming, confirming, erasing, and reconfirming individual bits of such a memory unit, in order to further ensure that the memory unit is erased during a flash memory device such as a block or sector erase operation. There is a correct erasure, and the above-mentioned problems related to the two-bit memory cell technology are solved

92257.ptd Page 16 200302486 V. Description of the invention (11) These questions. Figure 2 shows the programming of the two bits in the memory cell (10). For the convenience of explanation, a bit is called a normal bit (NB), and an associated bit is called a complementary bit (CB). During a read operation, the interface closest to the memory cell being read is the ground terminal, and the other end of the transistor is the drain. This method is called reverse reading. During programming and erasing, the drain is switched to the closest interface. At this time, the voltage of the closest interface is the drain voltage instead of ground. This method is used for reading and verifying. The two-bit memory unit (10) can be regarded as three parts that work together. These three parts are a complementary bit area (40), a central area (42), and a normal bit area (44). The complementary bit area (40) and the central area (42) are close to the drain / source interface, and the local VT can be modified during programming and erasing operations. The central area (42) should be close to the natural VT generated in the process of the memory unit (10). The silicon nitride (16) from the ON stack (30) is used to store the first charge (38) in the normal bit region (44) and the second charge (39) in the extra bit region ( 4 0). Because the nitride is not a conductor, the charge added or removed during programming and erasing should not be redistributed, but should remain where it was originally injected. That is, each end of the transistor may have a different charge and a different VT that are almost unrelated to the other end. For example, if the natural or erase / empty VT of the CB and NB is about 1.2 volts, and if the NB is programmed to a V T of about 3.8 volts, the C B should still be close to a blank state. In addition, if two bits are

92257.ptd Page 17 2002302486 V. Description of the invention (12) Program VT to 3.8 volts, and then erase the NB, then the CB should be about 3.8 volts, and the NB should be about 1.2 volts . In addition, during the reading operation of the NB, a portion of the charge close to the CB bit line should be covered by a drain empty region, because the source (ground point) is necessarily the closest to the memory cell being confirmed Meet. This operation is called a reverse reading operation because the interface of the identified memory unit is grounded. Although this reverse reading method covers some portion of the charge near the interface of another bit, any charge in the center of the channel will modify the effective VT of the CB and the NB. When the VT of one of these areas becomes lower, the other area may also be affected because these areas are all part of the same transistor. Figure 3 shows how, after the CB has been programmed with similar programming parameters, the programming operation performed on the NB to program the charge (38) to the NB area (44) will cause an accumulated charge ( 4 6) Partially detached into the central area (4 2). The effective shorter channel is due to the charge stored on the first bit approaching the ground that was ground during programming of the second bit. Due to the shorter channel length caused by the first bit being charged, programming the second bit will be much faster than programming the first bit. Because the second bit is programmed in a way that is less easily changed, erasing the second bit is slower than erasing the first bit. The invention solves the less easily changed programming place of the second bit by selecting a programming parameter that can be used to program and erase two bits in a consistent manner and eliminate residual charges accumulated during the programming and erasing cycle. Problems that arise. ν As shown in Figure 4, the accumulated charge (4 6) may stay on the memory sheet

92257.ptd Page 18 200302486 V. Description of the invention (13) Yuan (1 0), and change the programming and erasing characteristics of the memory unit (1 0) in each cycle. The position of the additional second bit programming charge (46) will change the effective VT of the CB area (40) and the NB area (44), and make the erase time increase with the number of programming and erase cycles. increase. The combination of two-end and single-end erase steps provides a stable method for controlling the two-bit erase of the general and outermost bits in the memory cells of the array. The outermost bits in the memory cells of the array usually have different channel lengths or widths, and they will be erased very slowly when only the two-side erase method is used, but the erase pulses at both ends are the best for ordinary memory cells. Effect. Therefore, a single-ended erase is added to maintain the erase speed of the outermost bits of the memory cells of the array. Therefore, it is important to determine the monitoring of the VTs in the NB area (44), the central area (42), and the CB area (40), and to maintain the VTs in these areas at known levels in order to correctly Operate the memory unit. The procedure of monitoring and controlling the VT of the CB and NB is usually performed during erasing (hereinafter referred to as π double-bit erasing). Therefore, in the present invention, the programming parameters are selected so as to ensure that the bits are not over-programmed due to the residual charge, and erase is performed to ensure that the residual charge in the central area (42) is controlled. By controlling the VT distribution during programming and erasing, the erasing and programming time during the programming and erasing cycle will remain stable. Fig. 5 shows a memory cell (10) using the two-bit programming and erasing method of the present invention after a programming and erasing cycle. Many flash memories have command logic and embedded state machines to automate complex programming and erase operations. Static random access memory

92257.ptd Page 19 200302486 V. Description of the Invention (14) (SRAM) module components can contain programs implemented by a microcontroller to control the operation of command logic and memory systems. When a system is turned on, these programs are usually loaded into a SRAM. A bus can be used to transmit control commands from a processor to a command logic device, and to read data from the flash memory device or write data to the flash memory device with the command logic and a main process器 开关。 Exchange. The embedded state machines of the flash memory device generate command logic controls for detailed operations, such as various individual steps required to perform programming, reading, and erasing operations. The state machine is thus used to reduce the resource consumption of a processor (not shown) typically associated with a microchip containing flash memory. Referring now to FIG. 6, there is provided a system (60) for performing programming and confirmation on a memory array (68) using the dual-bit memory unit of the present invention. , Soft programming, and erasing. In this example, the memory array (6 8) is composed of a plurality of 6 4 K segments (6 9). One segment (6 9) of the flash memory array contains the memory array (6 8) A portion of the memory cell that contains all memory cells clustered together via all word lines that share the same sector address. The sector address is usually the address bits used to address one or more memory cells in the memory array. Η (for example, six) most significant address bits of a meta signal, where η is an integer. For example, each 64K sector (69) can be composed of 8 10s, of which I 0 has 4 normal bits and 4 4 complementary memory cells or 4 double-bit memory cells constitute a column. We should understand that the memory array (68) can be any number of different configurations, for example, it can be on 8 memory cells 8 normal bits and 8 complementary bits form a 1 2 8 K segment. This

92257.ptd Page 20 200302486 V. Description of Invention (15) Any number of segments can be used, and it is limited only by the size of the application and the size of the device using the flash memory array (68). The system (60) includes an address decoder (62) connected to the flash memory array (68), and is used to perform various operations (e.g., programming, fetching, deciphering) on the array (68). , Erase) during the decoding of 10 each. The address decoder receives address bus information from a system controller (not shown) or a similar device. A command logic component (64) includes an internal state machine (65). The command logic component (6 4) is connected to the address memory array (6 8). The command logic and state machine receive commands or instructions from a data bus connected to a system controller or similar device. These commands or instructions call algorithms embedded in the command logic (64) and state machine (65). These algorithms perform the various programming, reading, erasing, soft programming, and validation methods that will be described in this article. A voltage generator component (66) is also connected to the memory array (68), the command logic (64) and the state machine (65). The voltage generator assembly (66) is controlled by the command logic (64) and the state machine (65). The voltage generator assembly (66) is operable to generate the voltages required for programming, reading, erasing, soft programming, and confirming the memory cells of the memory array (68). Fig. 7 is a top view or a plan view illustrating a layout of a part of a memory unit of a 64K block (70). This example is shown with reference to a 64 K block composed of 16 bit I / 0. We should understand that each block can be composed of 8-bit, 32-bit, 64-bit, or more I / 0, and is not limited to 64K (for example, it can be 128K, 2 5 6 K, etc.). The 64K block (70) can

92257.pid Page 21 200302486 V. Description of the invention (16) is a sector, or part of a sector. For example, one or more blocks with contacts connected to a common metal bit line may constitute a block. The 0N0 stacked bars or layers (72) extend to the length of the memory array and include blocks (70). Block (70) contains a group of 16 I / Os or rows (76). Each group of words or I / 0 is composed of eight transistors or eight standing bits and eight complementary bits. Each I / 0 contains a polysilicon word line (74), which is used to address the memory cells in the columns. The plurality of bit lines are arranged below the 0 N 0 stacked strip layer (72) so as to start reading, writing, and erasing the individual bits of the memory cells. Each bit line is connected to a first contact (78) and each metal bit line (not shown) on one end of the sixteenth column of the # group, and is connected to the other end of the group A second contact (7 9). In the example shown in FIG. 7, five bit lines are shown. Therefore, one bit line is connected to one end of every other transistor in a row, and two selection transistors are used to select two transistors. Four bits to perform reading, writing, and erasing. Figure 8 is a schematic diagram of addressing the first four two-bit memory cells in a column using a number of selection transistors and three bit lines to read, write, and erase each bit. The first double-bit memory unit (82) includes a first bit C0 and a second bit C1, and the second double-bit memory unit (84) includes a first Λ-bit C 2 and a second bit C 3, The three double-bit memory unit (86) includes a first bit C4 and a second bit C5, and the fourth double-bit memory unit (88) includes a first bit C6 and a second bit C 7. These four double-bit memory cells can form an 8-bit word. There are selection gates (8 8) (S e 1 0) and selection gates (90) (Sel 1) for activating the two-bit memory unit (82).

92257.ptd Page 22 200302486 V. Description of the invention (17) Bits C 0, C, and bits C 2 and C 3 of the double-bit memory unit (84) read, write, and erase. There are selection gates (92) (Sel2) and selection gates (9 4) (Se 1 3) for activating bits C4, C5, and two-bit memory units of the two-bit memory unit (86). (88) Bits C6, C7 are read, written, and erased. The first switch (96) is connected to the first bit line BL0, the second switch (98) is connected to a second bit line BL1, and the third switch (100) is connected to the third bit line Line BL2. The first, second, and third open relationships couple the corresponding bit lines between a power source (VDD) and a ground point (GND). By providing the different voltage configurations shown in Table 2 below, any bit of these two-bit memory cells can be read. In the example shown in Figure 8, the bit C0 ° of the two-bit memory cell (8 2) is being read. Table 2

Memory unit WL ABC selO sel 1 sel 2 Sel 3 BLO BL 1 BL2 CO Vgate HLXLHLL GND VD X C1 Vgate LHXLHLL VD GND X C2 Vgate HLXHLLL GND VD X C3 Vgate LHXHLLL VD GND X C4 Vgate XHLLLLHX GND VD C5 V5 C5 V5 Vgate XHLLLHLX GND VD C7 Vgate XLHLLHLX VD GND During the two-bit programming, select a higher VT change value in order to compensate the charge loss of the subsequent cycle. At these higher VT changes, the first bit on the transistor is much slower than the second bit on the programming transistor.

92257.ptd Page 23 200302486 V. Description of the invention (18) Programming at speed. This situation does not occur when the programming voltage is much lower. Fig. 9 shows the relationship between the programming time of the second bit and the VT change value of the first bit (110). Because the programming of the second bit is harder to change and faster, the second bit determines the double bit erasing time and the method that can be used to erase the double bit. It is important to select the programming conditions that make the VT after the second bit programming approach the VT after the first bit programming. Otherwise, the erase of the two bits may be very slow, and the first bit after programming will be Excessively erased. In general, it is critical to control the drain voltage during programming of the first bit in order to limit the V T range of the first bit. In order to control the VT of one bit, the gate voltage of the two bits during programming is selected to be approximately 9.5 volts to approximately 9.5 volts, and the drain voltage is selected to be approximately 5.0 volts to approximately 5 volts. 5 volts and reduces the pulse width of the programmed pulse to 0.5 microseconds. These conditions help maintain a stricter first bit VT and slow down programming of the second bit. • A key characteristic of the 0 N 0 dual bit memory cell is that the charge loss during accelerated high temperature baking (75 to 200 degrees Celsius) is a strong function of the number of programming and erasing cycles. Fig. 10 is a graph showing the relationship between the charge loss represented by the voltage and the number of times of the program and erase (Program and Erase; PE) cycle (120). This figure presents a possible reliability issue because the charge loss increases as the number of programming and erasing cycles increases to 10,000. The single-bit programming state of the transistor (when one end of the transistor is programmed, but the other end is blank or unprogrammed, that is to say, this state occurs) has a larger number of cycles. The problem of charge loss. The charge consumed when both bits are programmed is less than

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92257.ptd Page 24 200302486 V. Description of the invention (19) The charge consumed in the 10 or 01 state. Therefore, the VT change value is programmed to be between 2 and 2.5 volts to compensate for the charge loss caused by cycling. Considering the exemplary systems shown and described above, please refer to the flowcharts in Figures 11 to 14 to make it easier to understand a method that can be implemented in accordance with the present invention. For the sake of brevity of the description, although the methods in Figures 11 to 14 are shown and explained in a sequential manner, we should understand that the present invention is not limited to the order shown, because some steps may Performed in a different order according to the present invention, and / or may be performed concurrently with other steps shown and described herein. Furthermore, not all steps shown are necessary to implement a method according to the invention. One of the key characteristics of the dual-bit memory cell in the flash memory array of the present invention is that the charge loss during the accelerated high-temperature baking (75 to 200 degrees Celsius) is the number of burning and erasing cycles One of the strong functions. This phenomenon presents a possible reliability problem because the charge loss increases as the number of programming and erasing cycles increases to 10, 000 times. The single bit 1 to 0 or 0 to 1 state of the transistor (when one end of the transistor is programmed, but the other end is blank or unprogrammed, that is to say this kind of tragedy) occurs in a larger cycle There is a problem of large charge loss in the number of times. At a baking temperature of 250 degrees Celsius, the behavior of the memory early element transistor is not Gauss s i a η type. Below 250 ° C, due to the redistribution of the charge in the nitride and the local enhancement of the trapped nitride charge near the large polycrystalline silicon gap, it is close to the larger word line (the polycrystalline stone in the central part) (East gate) gap memory cell transistor consumes more charge. What we found: When

92257.ptd page 25 200302486 V. Description of the invention (20) __ All devices go through the same number of cycles. After the cell crystal grains are under the same data type, the second memory list appears. When the number of cycles exceeds K 〖〇 The wear distribution is a phenomenon in which the programming and erasing conditions will be repeated, and the effect of 之后 # = ^ after the cyclic cycle is small. The relationship between Er Maozhi and the number of cycles in order to cope with the value after 100k cycles (for example, to make ντ change, 佶 * Μ power consumption 'increase programming VT to change the lifetime of the flash memory array 5 volts), In order to ensure a fast and effective VT. We decided that ·····, / /, the memory unit after the process can maintain the sound ate = 9 · 2 5 to 9 · 5 volts, and widely choose the programming parameters of 疋 (for example, when the programming pulse is applied 0.5 Microseconds), i11 5 · 0 to 5 · 5 volts, the higher V T (2.0 volts to 25 volts) per word to program the dual bit memory cells to a pole. Short programming time. We, Fu a 'and still maintain 250 degrees in double-bit operation), the charge consumption refers to /, set at a higher temperature (such as Celsius, this type of cycle time related to the cycle time Function. It is used to modify the unit programming to 2.0 volts? P9 [The method to remove any loss is to program the bits in each memory (V, p, a) rate (the VT of one of the divisions changes the value, and At a slower speed

Ydraini · 0 to 5.5 Volts, at Vgate :: = 9 · 25 to 9 · 5 Volts, and) to apply a 0.5 microsecond control to the programming pulse that is a word with a double bit mother. & associated complementary bit interference effects

FIG. 11 shows a method for operating 4 ′ in an A-bit mode, according to an aspect of the present invention, and changing a specific value of the V T voltage, a two-bit memory cell of an array, in which the determination of I do Bu Shaofa. The method starts at step (2 0 0), where the memory cells in the array are normally blank or not.

200302486 V. Description of Invention (21) VT is programmed. In step (205), the array in the batch is programmed and erased several times with various programmed VT change values, and then a high temperature accelerated baking (100 to 250 degrees Celsius) is performed. Then in step (2 1 0), the charge loss of the memory cells is determined. In step (2 1 5), the programmed V T change value is increased according to the charge loss amount. In step (2 2 0), the programming parameters are selected (for example, at Vgate II 9. 2 5 to 9.5 volts and Vdrain II 5.0 to 5.5 volts, the programming pulse of each word applies 0 5 microseconds) in order to ensure that the VT of the first bit can be controlled and the programming of the second bit can be slowed down under the increased VT change value. In step (2 2 5), using the selected programming parameters, several programming and erasing cycles are performed on another array of the batch, and then accelerated baking is performed. In step (230), this method determines whether the results of the programming and erase cycles performed in step (22.5) are acceptable. If the results of such programming and erasing cycles are unacceptable ('' No 'branch), the method returns to step (2 2 0). If the results of these programming and erase cycles are acceptable ("yes" branch), then in step (2 3 5) the command logic and state machine are set to use the VT to change the value and the selected drain And gate potential to program the two fixed bits of these two-bit memory cells. We should understand that not only under normal programming conditions can be used to use higher V T to change the value of the programming, but also in the two-bit erase The programming method described above can also be used in the pre-programming or programming stages of the division method. Figure 12 shows a method using the selected programming parameters (for example, at Vgate = 9. 2 5 to 9.5 volts, Vdrain = 5. 0 to 5.5 volts, VT changes between 2 volts and 2.5 volts, and a programming pulse of 0.5 microseconds is applied).

92257.ptd Page 27 200302486 V. Description of the invention (22) The two-bit erasing method shown in Figs. 12 to 14 includes a memory unit erasing program to control the complementary bits of each memory transistor. The upper limit and lower limit of the VT threshold value of the terminal and the normal bit terminal under blank or erased conditions (for example, minimum VT = 1.0 volt, maximum VT = 1.8 volt). In addition, the two-bit erase method includes a soft programming program to avoid excessive erasing of the memory cells which may cause longer programming time, and to control the programming time. This soft programming i may affect the charge loss after recycling. Finally, the two-bit erase procedure may include a second erase procedure to ensure that any memory cells are not programmed by the soft programming procedure. The dual method shown in Figures 12 to 14 improves the flash memory array of the present invention that operates during extended cycle use (eg, 1,000 programming and erase (PE) cycles). Programming and erasing features. Fig. 12 shows an erasing method using hot hole injection at the high-voltage drain junction near the normal bit and the complementary bit. Heavy-duty programming of a single bit will cause a residual charge to accumulate, which cannot be reached by single-ended erase or traditional erase methods within an acceptable voltage level and / or acceptable erase time range Charge. This double-bit erasing method ensures the control of the blank VT of the normal bit and the complementary bit in each cycle by confirming and modifying the erasing method. Therefore, the present two-bit erase method applies a series of erase conditions or sequences to the complementary bits and their associated normal bits in a single memory cell during each month. The first erase sequence of each pulse is an erase pulse with two ends or two drains, which causes the source and drain of all memory cell transistors to become high voltage (for example, 4 to 7 volts) . The complementary bits and their associated normal bits are allowed to discharge. Then put a single-ended Λ

92257.ptd page 28 200302486 V. Description of the invention (23) The erasing pulse is applied to the complementary bit (for example, the drain of the complementary bit terminal becomes high voltage, and the other transistor interface is floating), A single-ended erase pulse is then applied to the normal bit (for example, the drain at the normal bit terminal becomes high voltage and the other transistor junction is floating). Regardless of the bit to be confirmed, the order of these single-ended pulses can be exchanged. When the pulse wave erasing time at these two ends is about 75% to 95% of the total pulse wave erasure time, a significantly improved result is achieved in the 0N0 double-bit architecture. Figure 12 illustrates a specific method for programming and erasing a flash memory array having a dual bit memory cell according to an aspect of the present invention. The method starts at step (300), at which point the erase routine is called. For example, a command can be transmitted from the controller to a state machine provided on the flash memory device, and the erase program can be called. In step (305), the bits in the normal row position and the extra row position are programmed to the VT change value. The selected programming voltage parameters are: at V gate = 9. 25 to 9.5 volts, Vdrain = 5.0 to 5.5 volts, and VT changes between 2 and 2.5 volts, applying 0. 5 microsecond pulse. The method then proceeds to step (310), at which time the address counter pointing to the memory location of the array is set to the first address. The method then proceeds to step (31 5). In step (315), the method performs a confirmation erase on one address location in a sector. The address location may be a memory address of a single bit location, or a memory address of a sector I / 0 or word location. If the confirmation erase of the address position fails, the method proceeds to step (3 2 0). In step (3 2 0), the method determines whether the maximum pulse wave count has been reached. If the maximum pulse wave count has been reached ("is a π branch), the method proceeds to step (3 2 5), at which point the device is indicated as

92257.ptd Page 29 200302486 V. Description of the Invention (24) did fail. If the maximum pulse wave count ("No" branch) has not been reached, the method proceeds to step (330) to apply an erase pulse wave. In step (3 3 0), the method applies a two-end erasing pulse wave to each complementary row position and normal row position of the section in a period of 8 to 12 milliseconds (for example, a 10 millisecond Pulse). After a period of discharge time is exhausted, two first single-ended pulses are applied to the bits in the complementary row position for a duration of 0.5 to 2 milliseconds (for example, 1 millisecond), and then 0.5 to 2 milliseconds A second single-ended pulse is applied to a bit in the normal row position for a duration (eg, 1 millisecond). The method then returns to step ^ 3 15) to confirm the erasure of the current address location. If the confirmation erasure of the current address position has passed, the method continues to step (3 3 5) to determine whether the current bit or I / 0 address is the largest address position. If the current memory location or I / O address is not the largest address position ("Noπ branch"), the address position of the address counter is incremented to the next address position in step (340). This method then Return to step (3 1 5) in order to perform the confirmation of the erasure of the one-bit address position. If it is determined in step (3 3 5) that the maximum address has been reached (π is the π branch), the method enters The soft programming procedure shown in Figure 13 is used to ensure that the memory cells are not over-erased. # After the erase method shown in Figure 12 is used, a soft programming method is used to control the minimum of The erased) normal bit and complementary bit V T. The over-erased memory cell is the sum of the minimum value of V T below the blank state. It is not a traditional row drain potential cell. Storage of holes in the nitride layer is not considered possible, but

92257.ptd Page 30 200302486 V. Description of the invention (25) The electric field used to erase the memory unit is extremely high, and it may reduce the local VT of the memory unit to below the natural state. When this happens, the programming time of one or both of the normal bit and the complementary bit of the over-erased memory cell will increase. Therefore, the soft programming method shown in Fig. 13 is performed in order to eliminate the over-erased memory cells and maintain a stable programming time during cycle use. Figure 13 illustrates a specific method for performing soft programming of the flash memory array to ensure that the memory cell portion of the flash memory is not over-erased. In step (400), the soft programming program is started. For example, a command can be transmitted from the controller to a state machine provided on the flash memory device, and the soft programming program can be called. In an alternative embodiment, the soft programming program may be a part of the overall erasing program, and the soft programming program is started after the method shown in FIG. 12 is completed. The method then proceeds to step (405) where the address counter is set to the first address. The method then proceeds to step (41 0). In step (410), the method confirms the soft programming of the first address location. The acknowledgement should include a lower source voltage to suppress any subthreshold leakage current. If the soft programming of the confirmation of the address location fails, the method proceeds to step (4 1 5) in order to determine whether the maximum pulse wave count (for example, 5 pulse waves) has been reached. If the maximum pulse count ("yes" branch) has been reached, it is indicated in step (4 2 5) that it did fail. If the maximum pulse wave count has not been reached ("Noπ branch"), the method proceeds to step (4 2 0), so as to apply a soft programming pulse to the address location, and returns to step (4 1 0) to

92257.ptd Page 31 200302486 V. Description of the invention (26) It is confirmed whether the address location has passed the soft programming confirmation condition. If the address position of the sector has passed in step (41 0), the method proceeds to step (430), at which time it is determined whether the maximum address of the sector has been reached. If the maximum sector address has not been reached ("Noπ branch"), then the address position of the address counter is moved to the next land certificate position in step (4 3 5), and the method returns to step (4 1 0) In order to repeat the steps of performing soft programming confirmation on the next address location in the memory array. If it is determined in step (4 3 0) that the maximum address location has been reached (1 is a π branch), then this method Enter the second erase procedure shown in Fig. 14. φ Fig. 14 shows a method for performing a second erase procedure on a flash memory array according to the present invention to ensure that the soft programming program does not over-program the A specific method of the memory unit. The method starts at step 50 of the second erase procedure. For example, a command may be transmitted from the controller to a state machine provided on the flash memory device, and the second method may be called. Erase procedure. In an alternative embodiment, the second erasure procedure may be part of the overall erasure procedure, and the second erasure procedure is started after the method shown in FIGS. 12 and 13 is completed. This method then proceeds to step (5 0 5), at this time, the address counter is set to the first address position. The method then proceeds to step (510). In step (51 0), the method performs a confirmation wipe on the address position of one of the memory arrays. The address position can be the memory address of a single bit position, or the memory address of the sector's I / 0 or word position. If the confirmation and erasure of the address position fails, the method proceeds to step ( 5 2 0). In step (5 2 0), the method determines whether the maximum pulse wave count has been reached. If the maximum pulse wave count has been reached (π

92257.ptd page 32 200302486 Five 'invention description (27) is the π branch), then the method proceeds to step (5 3 0), at which time one of the devices is indicated to have failed. If the maximum pulse wave count has not been reached ("Noπ branch"), the method proceeds to step (5 2 5) in order to apply the erasing pulse wave. In step (5 2 5), the method ranges from 8 to 12 milliseconds. A wipe pulse is applied to the complementary row position and normal row position of the segment for a duration (for example, a pulse of 10 milliseconds). After a discharge time, between 0.5 · 2 to 2 milliseconds (for example, 1 Milliseconds) apply a single-ended pulse to a bit in a complementary row position for a duration, and then apply a single-ended pulse to the normal row for a duration of 0.5 to 2 milliseconds (eg, 1 millisecond) The bit in the position. The method then returns to step (5 1 0) in order to confirm the erasure of the current address position. If the confirmation erasure of the current address position has passed, the method proceeds to step (5 3 5), In order to determine whether the current bit or I / 0 address is the maximum address position. If the current memory unit or I / 0 address is not the maximum address position (π no π branch), then the address counter is set in step (5 4 0) The address location is incremented to the next address bit The method then returns to step (51 0) in order to perform confirmation of the erasure of the next address location. If it is determined in step (5 3 5) that the maximum address has been reached ("is a π branch), then this method The method ends and the device returns to normal operation. In order to achieve the foregoing and other objectives of the present invention, the present invention includes the features fully described and specifically pointed out in the scope of the patent application to be described later, but those with ordinary knowledge of this technology can understand that many further combinations of the present invention and Changes are also possible. Therefore, this invention shall include all such changes, modifications, and alterations within the spirit and scope of the scope of the final patent application.

92257.ptcl Page 33 200302486 V. Description of the invention (28). In addition, although specific features of the invention may be disclosed with reference to only one of the several embodiments, such features may be combined with one or more other features of other embodiments that may be needed and advantageous for any particular application.

92257.ptd Page 34 200302486 Brief description of the drawings [Simplified description of the drawings] Fig. 1 is a side sectional view of one example of a dual-bit memory unit capable of implementing various aspects of the present invention; Fig. 2 is used for explanation A cross-sectional side view of a two-bit memory cell storing a programmed charge in a normal region and a complementary region of the two-bit memory cell; Figure 3 is used to illustrate the second Side-view cross-sectional view of a double-bit memory cell that accumulates non-uniform electricity in the central region of the early memory cell by over-programming the bit; Figure 4 is used to illustrate the use of single-end erase or two-end erase Side view sectional view of a two-bit memory cell remaining in the central region of the memory cell near the edge of the array after the memory cell is erased; FIG. 5 is a diagram for explaining the two-bit memory cell according to the present invention after erasing Later, the side view of the two-bit memory cell with the residual charge remaining in the central region of the memory cell near the edge of the array removed; FIG. 6 is a block diagram of various systems suitable for implementing the present invention; FIG. 7 Top view of a portion of a 64 K segment of a dual bit flash memory array with 16 bits of 16 bits of memory according to the present invention; FIG. 8 is a diagram of a dual bit memory cell according to the present invention Part of a column is not intended; FIG. 9 is a relationship diagram between a first bit VT change value and a second bit programming time according to the present invention; FIG. 10 is a VT change according to the present invention Value Charge Depletion and Programming

92257.ptd Page 35 200302486 Schematic illustration and diagram of the relationship between the erasing period; Figure 11 is used to determine a relatively high VT change value and selected programming parameters to program the dual bit according to the present invention Flow chart of the method of the first and second bits of the meta-memory unit; Figure 12 is a flowchart of a method for performing erasure confirmation on a double-bit 1-memory unit of an array according to the present invention; FIG. 13 is a flowchart of a method for performing soft programming on the memory cells of the two-bit memory cell array after executing the erase confirmation method shown in FIG. 12 according to an aspect of the present invention; and Fig. 14 is a flowchart of a method for performing a confirm erase operation on the memory cells of the two-bit memory cell array after executing the soft programming method shown in Fig. 13 according to an aspect of the present invention. 4th — 5, 42 central area 6-second area 8 channels 9 P-type substrate area 10 double-bit memory early 12 polycrystalline silicon layer 14 up-silicon oxide layer 16 silicon nitride layer 18 lower silicon dioxide layer 20 Boron ion core implant 22 Oxide part • Conductive part 26, 38 No. — charge 28, 39 second charge 30 ONO layer 32 first bit line 34 second bit line 40 extra bit 44 normal bit area 46 electrical service 60 system

92257.ptd Page 36 200302486

Schematic description 68 memory array 69 64K segment 62 address decoder 64 command logic component 65 state machine 66 voltage generator component 70 6 4 K block 72 0N0 stacking bar 74 polycrystalline word line 76 row 78 first Contact 79 Second contact 82 First double bit memory unit 84 Second double bit memory unit 86 Third double bit memory unit 88 88, Fourth double bit memory list 90, 92, 94 Yuan selection gate 96 100 First switch Third switch 98 Second switch 92257.ptd Page 37

Claims (1)

200302486 β 6. Application for patent scope 1. A method for programming the bits in the ON0 double-bit memory cell (1 0, 8 2, 8 4, 8, 6, 8 8) working in double-bit mode, The method includes the following steps: A programming pulse is applied to at least one bit of the two-bit memory cell (10, 8 2, 8, 4, .8 6, 88) by applying a voltage to the 1 The drain of at least one bit, and at the same time a voltage is applied to the gate of the at least one bit; confirm that the VT change value of the at least one bit is in the range of about 2.0 volts to about 2.5 volts And φ repeats the step of applying a programming pulse until the V T change value of the at least one bit is in a range of about 2.0 volts to about 2.5 volts. 2. The method of claim 1 in the patent application range, wherein the step of applying a programming pulse includes the following steps: repeatedly applying an electric power ranging from about 5 volts to about 5.5 volts to the drain, and simultaneously applying the range A voltage of about 9.5 volts to about 9.5 volts is applied to the gate. 3. The method as described in the first item of the patent application, wherein the ONO double-bit memory unit (1 0, 8 2, 84, 8 6, 8 8) works in a double-bit mode, where the ONO double-bit memory The memory unit (10, 8 2, 84, 8 6, 8 8) has a normal bit and a complementary bit, wherein the normal bit and the complementary bit are programmed. 4. A method for determining programming parameters for programming the bits of an ON0 double-bit memory cell array (68) operating in a double-bit mode, the method comprising the following steps: ^ Performing on at least one array in a batch A predetermined number of programming 92257.ptd Page 38 200302486 VI. Scope of patent application and erasing cycle, and then perform accelerated baking; after these programming and erasing cycles and accelerated baking, determine the charge of at least one bit of the at least one array Depletion; determining an increase in the value of ντ to reconcile the charge depletion of at least one bit of at least one of the several additional arrays in the batch; and determining a number of programming parameters so that the increased The memory cells are programmed under changing values of VT, and the programming parameters include a programming pulse width, a potential of the programming pulse on a gate of the bit, a potential, > of the bit, and the Program the potential of one of the pulses. 5. The method according to item 4 of the patent application, wherein the programmed pulse width is at a gate potential of about 9.5 volts to about 9.5 volts and at about 5.0 volts to about 5.5 volts The drain potential is approximately 0.5 microseconds. 6. The method according to item 5 of the patent application scope, further comprising the following steps: setting the command logic (6 4) and the state machine (6 5), so as to use the selected potential and gate potential to program to the increased VT changes value. 7. A system for programming a 0N0 double-bit memory cell array (68) that operates in a double-bit mode, the system comprising: a two-bit flash memory cell array (68); coupled to the ON0 An address decoder component (62) of the two-bit flash memory cell array (68), the address decoder component (62) is adapted to provide bit memory for the ON0 dual-bit flash memory cells Take; a voltage generator (66), the voltage generator (66) is adapted to provide 92257.ptd Page 39 200302486 6. The scope of the patent application is for the appropriate voltage to program and erase the bits of these 0 N 0 dual-bit flash memory cells; and the command logic containing the state machine (65) Component (64), the command logic component (6 4) and the state machine (6 5) are coupled to the array and the address decoder component (6 2), and are operable to control the voltage 'generator ( 6 6), the command logic component (6 4) and the state machine (65 5 parameters) are suitable for programming at least one bit, the programming method is: selecting the at least one bit; applying a programming pulse, the programming pulse The wave applies a first voltage to a drain of the at least one bit, and applies a second voltage φ to a gate of the at least one bit; confirms that the VT change value of the at least one bit is about 2.0. Volts to a range of about 2.5 volts; and repeating the step of applying a programming pulse until the VT change value of the at least one bit / is in a range of about 2.0 volts to about 2.5 volts . 8. If the system of item 7 of the patent application 'where the voltage applied to the electrode is in the range of about 5.0 volts to about 5.5 volts, and the voltage applied to the gate is about 9 25 Volts to approximately 9.5 Volts. 9. The system according to item 8 of the patent application, wherein the programming pulse has a duration of about 0.5 microseconds. 10. The system according to item 7 of the scope of patent application, wherein the 0N0 double-bit memory_cell array (68) operates in a double-bit mode, wherein each of the ON0 double-bit memory cells has a normal bit. And the complementary bit, wherein the normal bit and the complementary bit are programmed. 92257.ptd Page 40