GB2399945A

GB2399945A - Methods of forming semiconductor structures

Info

Publication number: GB2399945A
Application number: GB0413750A
Authority: GB
Inventors: Leonard Forbes; Kie Yeung Ahn; Luan C Tran
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2000-01-06
Filing date: 2001-01-08
Publication date: 2004-09-29
Anticipated expiration: 2021-01-08
Also published as: GB0413750D0; GB2399945B

Abstract

A method for forming semiconductor structures including gate stacks for field effect transistor (FET) and flash memory devices, whereby a patterned line is formed on a semiconductor structure over a silicon dioxide layer, the line comprising a first layer formed from doped silicon 108 and a second layer formed from metal 112. The line stack sidewall edges comprise a first layer defined portion and a second layer defined portion. A second silicon layer 150, 152 (fig. 4: 120) is formed along the sidewall edges and over the stack, which may be anisotropically etched to remove the layer from over the line, leaving portions along the sidewall edges (see fig. 15). The silicon is reacted with the metal at the edges to form a silicide layer 154, which protects against subsequent oxidation of the metal layer.

Description

DESCRIPTION

M15:THODS OF FORMING SEMICONDUCTOR STRUCTURES

Technical Field

The invention pertains to methods of forming semiconductor structures, s including methods of forming transistor gates for field effect transistor and flash memory devices.

Background Art

A continuing goal in semiconductor device fabrication is to create increasing 0 densities of circuitry on semiconductor real estate. Such goal is realized through ever-decreasing dimensions of semiconductor circuit elements. For instance, in the early 1970's a typical gate length of a field effect transistor gate in a dynamic random access memory (DRAM) device was on the order of from to 6 micrometers, and polysiIicon was utilized as a sole conductive material of the gate.

Is Advances in DRAM generation of the late 1980's reduced the gate length to approximately one micrometer. However, it was found that word line resistance was too high if conductively doped polysilicon was utilized as the sole conductive component of a gate line, and accordingly silicide (such as tungsten silicide, molybdenum silicide or titanium silicide) was deposited over the polysilicon. The to term "polycide" was coined to describe a stack of gate materials which comprised conductively doped polysilicon having a silicide thereover.

Technological advances of the 1990's reduced the gate length to less than 0.2 micrometers. It was found that the resistance of polycide materials was too high for such gates, and accordingly procedures were developed to provide a metal to replace the silicide of the polycide structure. Exemplary metals utilized are tungsten, molybdenum and titanium. Such gates would be considered modern structures in current technology.

Fig. 1 shows a semiconductor wafer fragment 10 comprising a field effect transistor 12 having such a gate structure. More specifically, wafer fragment 10 So comprises a substrate 14 having a gate structure 16 formed thereover. Gate structure 16 comprises a gate oxide layer 20 (which typically comprises silicon dioxides, a conductively-doped-semiconductivematerial layer 22 (which can comprise silicon and germanium, and which typically comprises conductively doped polysilicon), a conductive diffusion barrier layer 24 (which typically comprises a metal nitride, such as, for example, WNx, TiN), a metal layer 26 (which can comprise, for example, tungsten, molybdenum or titanium), and an insulative cap 28 (which can comprise, for example, silicon nitride or silicon dioxide).

Serniconductive substrate 14 can comprise, for example, conductively doped s monocrystalline silicon. To aid in interpretation of the claims that follow, the terms "semiconductive substrate,' and "semiconductor substrate" are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk serniconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers lo (either alone or in assemblies comprising other materials). The term "substrate" refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.

Gate structure 16 has opposing sidewalls 30, and insulative spacers 32 are formed along such opposing sidewalls. Insulative spacers 32 can comprise, for example, silicon nitride.

Source/drain regions 18 formed proximate gate structure 16, and a channel region 19 is defined beneath gate structure 16. Spacers 32 can be utilized during formation of source/drain regions 18 to space an implant of a conductivity-enhancing dopant from sidewall edges 30, and to thereby control a location of heavily doped source/drain regions 18 relative to sidewalls 30. Lightly doped diffusion regions are formed beneath sidewalls 32, and between heavily doped source/drain regions 18 and channel region 19, to define graded junction regions 33. The lightly doped diffusion regions are frequently formed prior to provision of sidewalls 32.

A problem can occur in utilizing the field effect transistor structure 12 of as Fig. 1 in DRAM devices. DRAM devices normally operate with a wordline voltage in excess of power supply voltage (a so-called boosted wordline). Accordingly, transistor gates utilized in gated DRAM structures are exposed to larger electric fields than in other devices, and are more subject to breakdown and failure. Also, DRAM retention time depends on the storage node junction leakage, which in turn sc can be affected by the electric field at intersecting corners of the gate and the drain junction. The electric field between the gate and the drain junction often induces more jurlc,ion leakage and Is frequently referred to as Gate Induced Drain Leakage (GIDL). It is therefore desirable to have a thickened gate oxide region at the corner of the gate and the drain to reduce the electric field, and hence the leakage.

One of the techniques utilized to enhance integrity of transistor gates is to oxidize a portion of a serniconductive material substrate proximate the gate to form small "bird's beak;' structures beneath sidewall edges 30. Such technique is illustrated in Fig. 2 wherein wafer fragment 10 is illustrated at a processing step subsequent to the formation of gate structure 16, but prior to formation of spacers 32 and source/drain regions 18. ran upper surface of semiconductive material wafer 14 has been oxidized to form a silicon dioxide layer 34 which connects with gate oxide 2Q. Silicon dioxide layer 34 comprises small bird's beak regions 36 which extend beneath sidewalls 30. Silicon dioxide layer 34 also extends along a portion of sidewall 30 corresponding to the sidewall edges of semiconductive-material layer 22, as such edges are oxidized during the oxidation of the upper surface of semiconductive material 14.

A problem which occurs with the processing of Fig. 2 is that sidewall edges of metal layer 26 can be oxidized during the oxidation of serniconductive material 14. Oxidation of metal layer 26 forms metal oxide regions 38. The volume expansion associated with the formation of metal oxide regions 38 can cause lifting of the metal lines, which can result in failure of field effect transistor structures incorporating gate structure 16.

Among the techniques which have been utilized to avoid oxidation of the so metal edge are wet hydrogen oxidation, and the utilization of silicon nitride or silicon dioxide to protect the edges. Additionally, silicon o7ynitride has been utilized to cover edges of the metal material in the gate stack prior to oxidation of an upper surface of semiconductive material 14.

The above-described problems are not limited to field effect transistor is technologies. The problems can also occur in stacks utilized for other memory devices, such as, for example, the gate stacks utilized in flash memory devices. Fig. 3 illustrates a semiconductor wafer fragment 50 comprising a semiconductive material substrate 52, and a flash memory device gate stack 54 formed over substrate 52.

Substrate 52 can comprise, for example, monocrystalline silicon lightly doped with so a p-type background dopant. Gate stack 54 comprises a gate oxide layer 56 (which can comprise silicon dioxide), a floating gate SS (which comprises se,miconductive material, which can comprise Si and Ge, and which typically comprises conductively doped polysilicon), an intergate dielectric layer 60 (which can comprise silicon dioxide), a conductively-doped-semiconductive-material layer 62 (which can comprise conductively doped polysilicon), a barrier layer 64 (which can comprise a metal nitride), a metal layer 66 (which can comprise tungsten, titanium or molybdenum), and an insulative cap 68 (which can comprise silicon nitride). Fig. 3 also shows an oxide layer 69 over substrate 52, and Lightly Doped Diffusion (LDD) regions 71 s implanted beneath oxide layer 69 and proximate gate stack 54. LDD regions 71 can be formed by, for example, implanting e-type conductivity enhancing dopant (such as phosphorus or arsenic) into substrate 52.

Note that layers 60, 62, 64, 66 and 68 comprise a stack identical to the stack utilized in gate structure 16. Accordingly, oxidation of semiconductive material lo substrate 52 can lead to problems similar to those discussed above regarding oxidation of semiconductive material 14. Specifically, oxidation of semiconductive material 52 can be accompanied by oxidation of sidewall edges of metal layer 66 which can cause failure of a circuit device incorporating stack 54.

The above-described Figs. 1-3 illustrate cross-sectional views through the described stacks of conductive and insulative materials. Such crosssectional views are utilized to illustrate various layers within the stacks. An alternative description of the stacks of Figs. 1-3 is to refer to the stacks as portions of patterned wordlines. In such alternative description, it is to be understood that the stacks can be portions of lines extending across tile respective semiconductor material substrates to (i.e., the stacks can be patterned in the shape of lines). Sourceldrain regions will be provided at various intervals along the lines, and the lines will thus have transistor gate regions functioning as Sating structures between respective pairs of source/drain regions.

It would be desirable to develop alternative methods of forming gate stacks and wordlines.

Disclosure of the Invention

One aspect of the invention includes a method of forming a conductive line.

A line stack is formed of at least two different conductive material layers. At least one of the layers comprises a metal, and the line stack has at least one sidewall edge that includes the metal-comprising layer. The metal-comprising layer is reacted at the sidewall edge traits silicon to form tee metal-comprising layer to comprise a silicide at the sidewall edge and unreacted metal inwardly thereof. After the reacting, at least a portion of the line stack is oxidized. of

Another aspect of the invention encompasses a method of forming a semiconductor structure. A patterned line is formed to comprise a first layer and a second layer. The first layer comprises silicon and the second layer comprises a metal. The line has at least one sidewall edge comprising a first-layer-defined portion and a second-layer-defined portion. A third layer is formed along the at least one sidewall edge. The third layer comprises silicon and is along both the first-layereddefined portion of the sidewall edge and the second-layered-defined portion of the sidewall edge. The silicon of the third layer is reacted with the metal of the second layer to form a silicide along the secondlayer-defined portion of the sidewall edge. The silicon of the third layer is removed to leave the silicon of the first layer, the metal of the second layer, and the silicide.

In another aspect, the invention encompasses another method of forming a semiconductor structure. A patterned line is formed to comprise a first layer and a second layer. The first layer comprises silicon and the second layer comprises a Is metal. The line has at least one sidewall edge comprising a first-layered-defined portion and a second-layered- defined portion. A third layer is formed along the at least one sidewall edge. The third layer comprises silicon and is along both the first-layer- defined portion of the sidewall edge and the second-layer-defined portion of the sidewall edge. The silicon of the third layer is reacted with metal of the second layer to form a silicide along the second-layer- defined portion of the sidewall edge. The silicon of the third layer is provided to be different than the silicon of the first layer, and is selectively removed relative to the silicon of the first layer to leave the silicide along the second-layer-defined portion of the sidewall edge. 2s

Brief Description of the Drawings

Preferred embodiments of the invention are described below with reference to the following accompanying drawings.

Fig. 1 is a fragmentary, diagrammatic, cross-sectional view of a semiconductor wafer fragment illustrating a prior art field effect transistor device.

Fig. 2 is a fragmentary, diagrammatic, cross-sectional view of a semiconductor wafer fragment illustrating a prior art gate structure.

Fig. 3 is a diagrammatic, fragmentary, cross-sectional view of a semiconductor wafer fra<,nent illustrating a prior art gate structure for a flash memory device.

Fig. 4 is a diagrammatic, fra=nentay, cross-sectional view of a semiconductor wafer fragment illustrating a gate structure at a preliminary step of a method of the present invention.

Fig. 5 is a view of the Fig. 4 wafer fragment illustrating the structure of Fig. 4 at a processing step subsequent of that of Fig. 4.

Fig. 6. is a view of the Fig. 4 wafer fragment illustrating the structure of Fig. I 4 at a processing step subsequent to that shown in Fig. 5.

Fig. 7 is a view of the Fig. 4 wafer fragment illustrating the structure of Fig. 4 at a processing step subsequent to that of Fig. 6.

lo Fig. 8 is a view of the Fig. 4 wafer fragment illustrating the structure of Fig. I 4 processed according to another method of the present invention, and shown at a processing step subsequent to that of Fig. 4.

Fig. 9 is a view of the Fig. 4 wafer fragment shown at a processing step subsequent to that of Fig. 8.

Fig. 10 is a view of the Fig. 4 wafer fraDnent shown at a processing step subsequent to that of Fig. 9.

Pig. 11 is a view of the Fig. 4 wafer fragment shown at a processing step subsequent to that of Pig. 4, and in accordance with yet another embodiment method of the present invention.

do Fig. 12 is a view of the Fig. 4 wafer fragment shown at a processing step subsequent of that of Fig. 11.

Fig. 13 is a view of the Fig. 4 wafer fragment shown at a processing step subsequent to that of Fig. 17.

Fig. 14 is a fragmentary, diagrammatic, cross-sectional view of a semiconductor wafer fragment shown at a preliminary processing step of yet another method of the present invention.

Fig. 15 is a view of the Fig. 14 wafer fra=nent shown at a processing step subsequent to that of Fig. 14.

Fig. 16 is a view of the Fig. 14 wafer fragment shown at a processing step so subsequent to that of Fig. 15.

Fig. 17 is a view of the Fig. 14 wafer fragment shown at a processing step subsequent to that of Fig. 16.

Disclosure of Invention

In particular aspects, the invention encompasses methods of protecting a metal layer during oxidation of a proxnate substrate by forming silicide structures over regions of the metal layer. The silicide protects regions of the metal layer s from being exposed to oxidizing conditions.

A first embodiment method of the present invention is described with I reference to Figs. 4-6. Referring initially to Fig. 4, such illustrates a semiconductor wafer fragment 10Q comprising a semiconductive material substrate 102 having a gate stack 104 formed thereover. Semiconductive material substrate 102 can comprise, for example, monocrystalline silicon lightly doped with a p-type background dopant. I Gate stack 104 comprises a gate dielectric layer 106 (which can comprise, for example, silicon dioxide), a semiconductive-material layer 108 (which can comprise silicon and germanium, and which typically comprises conductively doped polysilicon), a barrier layer 110 (which can comprise, for example, a metal nitride, such as titanium nitride or tungsten nitride), a metal layer 112 (which preferably comprises an elemental form of a metal, and which can comprise, for example, tungsten, titanium, cobalt or molybdenum) , and an insulative cap 114 (which can comprise, for example, silicon nitride and/or silicon dioxide).

For purposes of interpreting this disclosure and the claims that follow, a layer So which is referred to as a "silicon layer" is to be understood to comprise silicon and may consist essentially of silicon, but not necessarily to consist essentially of silicon unless it is expressly stated that such layer consists essentially of silicon.

Accordingly, a "silicon layer" can comprise, for example, silicon and germanium.

Additionally, a "metal layer" is to be understood to comprise metal and may consist essentially of metal, but not to necessarily consist essentially of metal unless it is specifically stated to consist essentially of metal.

Gate stack 104 comprises sidewalls 116, and such sidewalls comprise portions of each of layers 106, 108, 11O, 112 and 114. In particular aspects of the invention, layer 108 can be referred to as a first layer and layer 112 as a second layer. The portion of sidewall 116 corresponding to layer 112 can thus be referred to as a second-layer- defined portion, and the portion of sidewall 116 corresponding to layer 108 can be referred to as a first-layer-ecfined portion.

Substrate 102 comprises an upper surface 11S, some of which is covered by gate stack 104, and some of which extends beyond gate stacI: 104. An etch stop layer 117 is formed over upper surface 118 of substrate 109. Such etch stop layer can comprise, for example, silicon oxide or silicon nitride. A silicon layer 120 is formed over upper surface 118 of substrate 102 (and specifically on etch stop layer 117), along sidewalls 116 of gate stack 104, and over an upper surface of gate s stack 104. Layer I20 can comprise, for example, silicon in amorphous or polycrystalline form, and is typically formed to a thickness of from about 100 angstroms to about 200 angstroms. Silicon layer 120 can be formed by chemical vapor deposition to provide layer 120 to lie conformally over the sidewalls and top of gate stack 104. Generally, the difference between whether layer 120 comprises amorphous silicon or polycrystalline silicon is determined by a temperature of deposition, with amorphous silicon being deposited at temperatures of from about 500 C to about 550 C, and polycrystalline silicon being deposited at temperatures of from about 5SO C to about 625C.

In particular aspects of the invention, silicon layer 120 comprises a different composition than silicon-containing layer 108. Such difference in composition can correspond to, for example, a difference in dopant concentration within silicon layer relative to silicon layer 108. For instance, layer 108 preferably has a conductivity-enhancing impurity concentration of at least IxlO:8 atoms/cm3 to render layer 108 electrically conductive. Accordingly, layer 120 can be provided with a JO conductivity-enhancing dopant concentration of less than 1X10lB atoms/cm3 to provide a difference between layer 120 and 180. Such difference can be exploited in later steps of the method to enable layer 12D to be selectively removed relative to layer 103. In particular embodiments, layer 120 can be provided to be substantially undoped with conductivity-enhancing impurity, with the term "substantially undoped" 2s understood to mean a dopant concentration of less than or equal to about 1x10is atoms/crn3. A "substantially undoped" silicon layer is different than an "undoped" silicon layer in that an "unhoped" silicon layer would have a dopant concentration of about 0, whereas a "substantially undoped" silicon layer can have a dopant concentration from zero to as high as about 10is atoms/cm3.

In particular aspects of the invention, layer 120 can be referred to as a third layer which extends aloe:, both the portion of the sidewall 116 defined by silicon layer IDS, and the portion defined by rectal layer 119.

Fig. 5 shows fragment 100 after exposure to conditions which react silicon of layer 120 with metal of layer 112 to form silicide regions 122. Exemplary reaction conditions are to anneal fragment 100 at 900 C for about 20 minutes in an inert atmosphere. Alterrative reaction conditions comprise rapid thermal processing (RTP) for ten seconds to 950CC. The second reaction conditions can be preferred in order to avoid dopant redistribution between silicon layers 120 and 108.

Referring to Fig. 6, layer 120 (Fig. 5) has been removed to leave silicide regions 122 along sidewalls 116. Removal of layer 120 can be accomplished by, for example, a timed etch, such as, for example, a timed reactive ion etch, wet etch, or high density plasma etch. Preferably, the etch will not appreciably etch into the sidewalls of silicon layer 108, (with the term "appreciable etching" meaning an etch of more than angstroms into the sidewall), and also preferably the etch stops on etch stop layer 117 rather extending into upper surface 118 of substrate 102.

Particular etching methodology can be utilized in embodiments in which silicon layer (Fig. 5) comprises a different composition than silicon layer 108. In such Is embodiments, the etching preferably takes advantage of such differences in composition to selectively remove silicon of layer 120 relative to silicon of layer 108.

For instance, if layer 120 comprises silicon which is less doped than the silicon of layer 108, such less doped silicon can be selectively removed utilizing a tetramethylammonium hydroxide (TMAH) etch solution.

So Fig. 7 shows fragment 100 after exposure to oxidizing conditions. It is noted that etch stop layer 117 can be stripped from over substrate 102 prior to the exposure of the substrate to oxidizing conditions, or can remain, and if it comprises silicon dioxide, be expanded upon exposure of the underlying substrate to oxidizing conditions. The oxidizing conditions incorporate silicon from upper surface 118 o substrate 102 into a layer 130 of silicon dioxide, and also incorporate silicon from sidewalls of layer 108 into silicon dioxide. Further, the oxidation has formed small bird's beaks 132 under sidewall edges 116 of gate stack 104. However, in contrast to the prior art (Fig. 2 illustrates the result of an exemplary prior art process) the oxidation has not oxidized sidewalls of metal layer 112. Rather, silicide regions 122 so have protected the sidewalls of metal layer 112 during the oxidation.

Figs. 8-10 illustrate an embodiment of the invention wherein the silicon of layer 120 (Fig. 5) is converted to a font, which can lie selectively removed relative to the silicon of layer 108. Referring initially to Fig. 8, such illustrates wafer fragment 100 at a processing step subsequent to that shown in Fig. is. Specifically, silicon layer 120 of Fig. has been subjected to oxidizing conditions to convert the layer to a silicon dioxide layer 140. Subsequent processing such as, for example, wet etching of oxide layer 140 in a diluted HF solution can selectively remove the oxide of layer 140 relative to non-oxidized silicon of layer 108 to form the structure s of Fig. 6 (although some etching into sidewall edge 116 may occur).

Fig. 9 shows wafer fragment 100 after a second insulative layer I43 has been formed over silicon dioxide layer 140 (the second insulative layer can comprise, for example, silicon oxide or silicon nitride), and both silicon dioxide layer 140 and second insulative layer 143 have been exposed to an anisotropic etch to form to insulative spacers 142. Exemplary conditions for anisotropically etching silicon dioxide are etching of the silicon dioxide in a magnetic loop discharge plasma, or utilization of a fluorine-containing plasma in a reactive ion etch. It is noted that layer 117 is shown remaining over substrate 102 after the anisotropic etch of materials 142 and 143. In embodiments in which layer 117 comprises silicon nitride and materials 142 and 143 both comprise silicon dioxide, layer 117 can function as an etch stop layer to protect substrate 102 during the anisotropic etch of layers 142 and 143. Alternatively, if layer 117 comprises silicon dioxide, and materials 142 and 143 also comprise silicon dioxide, layer 117 can form a buffer over substrate 102 to protect substrate 102 during a timed anisotropic etch of materials 142 and 143.

to Fig. 10 shows a dopant 144 implanted into fragment 100 to form source/drain regions 146 proximate gate stack 104. Source1drain regions 146 are aligned utilizing spacers 142. In subsequent processing (not shown) spacers 142 can be remove, and substrate 102 can be oxidized to form small bird's beak structures analogous to the structures 132 of Fig. 7. Further, graded junction regions can be implanted proximate source/drain regions 146 subsequent to removal of spacers 142.

Alternatively, graded junctions (such as LDD or "link-up" regions) can be implanted in a processing step prior to that shown in Fig. 4. Such processing a step can, for example, occur after formation of gate stack 104 and before deposition of silicon layer 120.

Yet another method of the present invention is described with reference to Figs. 11-13. Referring to Fig. 11, wafer fragment 100 is shown at a processing step subsequent to that of Fig. 4, and specifically is shown after a material 153 is provided over silicon layer 120 (Fig. 4), and both material 13 and silicon layer 120 have been subjected to anisotropic etching. Material 153 can comprise, for example, silicon dioxide or silicon nitride. The anisotropic etching removes the silicon layer from over stack 104 and leaves portions 150 and 152 of the silicon layer along sidewall edges 116.

Referring to Fig. 12, fragment 100 is shown after exposure to suitable conditions to react silicon of portions 150 and 1j? with metal of layer 112 to form silicide regions 154. Such suitable conditions can comprise, for example, the conditions described above with reference to Fig. S. Referring to Fig. 13, anisotropically etched material 13 is utilized with portions 150 and 159 as spacers during an implant of a dopant 156. The implanted lo dopant forms source/drain regions 158. Also shown are graded junction regions 190 (such as, for example, LDD regions or halo regions), which can be formed by, for example, an angled implant. After formation of source/drain regions 158 and graded junction regions 190, stack 104 comprises a gate for a field effect transistor which gatedly connects source/drain regions 158 with one another. Stack 104 defines a channel region 160 thereunder which is between the source/drain regions 158. In further processing (not shown) portions 150 and 152 can be removed. Such further processing can be similar to that described above with reference to Fig. 6, and can occur before or after formation of diffusion regions 158.

In yet other aspects of the invention, the utilization of material 153 can be to avoided, to leave only portions 150 and 152 along stack 104. Further, portions 150 and 152 can be removed prior to any implant of source/drain regions, to form a structure identical to that shown in Fig. 6. Such structure can be subjected to the oxidative processing described with reference to Fig. 7. Alternatively, such oxidative processing can occur after formation of source/drain regions 158, and either with Is portions 10 and 152 in place, or after portions 150 and 152 have been removed.

Another method encompassed by the present invention is described with reference to Figs. 14-17. In referring to Figs. 14-17, similar numbering will be used as was utilized in describing Figs. 4-13, with differences indicated by the suffix "a".

Fig. 14 shows a semiconductor wafer fragment 100a which is similar to the fragment 100 of Fig. 4. Fragment 100a of Fig. 14 differs from fragment 100 of Fig. 4 in that frap,Tnent 100a comprises a silicon dioxide layer 106a having portions which extend outwardly beyond stack 104, as well as having a portion beneath stack 104.

In contrast, fragment 100 of Fig. 4 has a silicon dioxide layer 106 which is patterned to have sidewalls coextensive with sidewalls of silicon layer 108, and accordingly, part of sidewalls 116 of gate stack 104.

Fragment 100a comprises a silicou layer 120 identical to that of Fig. 4 fragment 100, and such silicon layer can be processed identically to the processing s described above with reference to Figs. :-13. particular processing sequence is described with reference to Figs. 15-17. Referring to Fig. 15, wafer fragment lOOa is shown after silicon layer 120 (Fig. 14) has been subjected to an anisotropic etch to convert the layer toextensions 170 which extend along sidewall edges 116 of gate staclc 104. The shown etch has stopped at oxide layer 106a. Such can be lo accomplished by timing an etch of layer 120 to stop at silicon dioxide layer 106a, or by utilizing etchant conditions which are selective for the silicon material of layer relative to the silicon dioxide of layer 106a. In an alternative embodiment of the invention (not shown), etch conditions can be utilized which do not stop at layer 106a, but which rather extend through layer 106a to substrate 102. Such conditions pattern layer 106a into an insulative layer which is only beneath stack 104 and extensions 170 (i.e., which does not extend outwardly beyond extensions 170).

Referring to Fig. 16, fragment 100a is subjected to conditions which react silicon from extensions 170 with metal from layer 112 to form silicide extensions 172. Suitable conditions for reacting the silicon and metal are the conditions so described above with reference to Fig. 5.

Referring to Fig. 17, extensions 170 (Fig. 16) are removed to leave silicide regions 172 protecting sidewalls of metal 112. Portions of silicon dioxide layer 106a which were covered by extensions 170 in the processing step of Fig. 16 remain after extensions 170 are removed. After removal of extensions 170, fra=,nent 100a can 2s be subjected to oxidation conditions such as those described above with reference to Fig. 7. In alternative embodiments of the present invention, extensions 170 can be utilized as spacers during an implant of dopant to form source/drair regions in processing sirmlar to that described above with reference to Fig. 13.

Although the invention has been described with reference to methods of so forming field effect transistor structures, it is to be understood that the invention can also be applied to methods of forming other memory devices, such as, for example, flash memory devices. An exemplary method of utilizing the techniques described with reference to Figs. 4-17 to form flash memory devices is to form the gate stacks described in Figs. 4- 17 over floating gate structures (with an exemplary floating gate structure shown in Fig. 3). The gate stacks will, of course, generally be separated from a floating gate by an intergate dielectric, such as, for example, the dielectric 60 described with reference to Fig. 3.

Claims

CLAIMS: 1. A method of forming a semiconductor structure, comprising:

providing a semiconductive substrate having a layer of silicon dioxide thereover; forming a patterned line over the layer of silicon dioxide, the patterned line comprising a doped silicon layer and a metal layer over the doped silicon layer; the line having a pair of opposing sidewall edges comprising regions of the doped silicon layer and metal layer; forming a second silicon layer along the opposing sidewall edges and over the line, the second silicon layer being along the doped silicon layer and metal layer regions of the sidewall edges; anisotropically etching the second silicon layer to remove the second silicon layer from over the line and leave portions of the second silicon layer along the sidewall edges; and reacting silicon of the second silicon layer with metal of the metal layer region to form a silicide along the metal layer region of the sidewall edges.
2. A method as claimed in claim 1 further comprising, after the reacting, removing the second silicon layer to leave the doped silicon layer, the metal layer and the silicide.
3. A method as claimed in claim 2 wherein the removing the second silicon layer comprises a timed etch of the second silicon layer.
4. A method as claimed in claim 2 further comprising patterning the layer of silicon dioxide prior to forming the second silicon layer, the patterning of the layer of silicon dioxide forming a patterned gate oxide beneath the doped silicon layer.
5. A method as claimed in claim 2 wherein the patterned line comprises only a portion of the layer of silicon dioxide and leaves an other portion extending outwardly beyond the patterned line, wherein the second silicon layer is formed over at least some of said other portion of the layer of silicon dioxide, and wherein said other portion of the layer of silicon dioxide remains after the removing of the second silicon layer.
6. A method as claimed in claim wherein the removing the second silicon layer comprises a timed etch of the second silicon layer.
7. A method as claimed in claim S wherein the removing the second silicon layer comprises a timed etch of the second silicon layer utilizing an etchant selective for the material of the second silicon layer relative to the silicon dioxide of the layer of silicon dioxide.
8. A method as claimed in claim l wherein the metal layer comprises tungsten.
9. A method as claimed in claim 1 further comprising forming source/drain regions proximate at least a portion of the line and utilizing said portion of the line as a

gate of a field effect transistor.
10. A method as claimed in claim 9 wherein the portions of the source/drain regions are formed by implanting a dopant into the semiconductive substrate, and wherein the portions of the second silicon layer along the sidewall edges are utilized as spacers during the implanting.
11. A method as claimed in claim l further comprising forming at least a portion of the line over a floating gate.
12. A method of forming a semiconductor structure substantially as hereinbefore described, with reference to Figures 4, 11 to 13 and 14 to 17 of the accompanying drawings.