GB2399898A

GB2399898A - Memory access circuitry and method

Info

Publication number: GB2399898A
Application number: GB0307014A
Authority: GB
Inventors: David Desmond Gilbert
Original assignee: Zarlink Semiconductor Ltd
Current assignee: Microsemi Semiconductor Ltd
Priority date: 2003-03-27
Filing date: 2003-03-27
Publication date: 2004-09-29
Also published as: GB0307014D0

Abstract

Memory access circuitry (30) is provided for use with a memory device (22) addressable within a predetermined normal addressing range. The circuitry (30) comprises a mapping portion (26) for mapping an access address (ADDR) issued from a processing unit (24) to a mapped address (ADDM) falling within the predetermined normal addressing range. Data stored in the memory device (22) in an internal format is retrieved from the memory device (22) based on the mapped address (ADDM). The circuitry (30) further comprises a function processing portion (28) for determining within which one of a number of function addressing ranges the access address (ADDR) falls and for processing the retrieved data (IDAT) in dependence upon the determined function addressing range to produce data (EDAT) in an external format for forwarding to the processing unit (24). The memory access circuitry is for use in voice echo canceller apparatus.

Description

1\11EMORY ACCESS CIRCUITRY AND METHOD The present invention relates to

memory access circuitry and a memory access method, and in particular to memory access circuitry and a memory access method for use in an echo canceller.

Figure 1 of the accompanying drawings shows a typical echo canceller architecture.

The echo canceller comprises an adaptive filter 2 and an adder 4, and is placed between a telephone handset on the left-hand side and a telephone network on the right-hand side. The adaptive filter 2 receives a signal RIN from the telephone's microphone and the output signal SOUT from the adder 4 is connected to the telephone's loudspeaker.

The signal RIN is passed to the telephone network as signal ROUT and a signal SIN received from the telephone network is passed to the positive input of the adder 4. The negative input of the adder 4 is received from the adaptive filter 2.

The arrow 6 between ROUT and SIN represents a source of echo in the telephone network. This could result from an impedance mismatch or other electrical source, or handset coupling at the far end of the telephone connection. As a result of this echo, a portion of the signal on ROUT appears on SIN mixed with the desired signal. This portion is the echo. Since the telephone connection is a long signal path, the echo does not occur immediately but will be delayed. The echo canceller works using the adaptive filter 2 to detect the echo delays and by subtracting an appropriate amount of the signal ROUT from the signal SIN so that the echo in SOUT is removed.

Figure 2 of the accompanying drawings shows a typical echo canceller architecture in more detail. The echo canceller architecture shown in Figure 2 comprises, in addition to the parts shown in Figure 1, PCM (pulse code modulation) to linear converters 10 and 16 connected respectively to receive the signals RIN and SIN, and linear to PCM converters 12 and 14 which output respective signals ROUT and SOUT. The echo canceller architecture of Figure 2 further comprises a memory portion 8 connected to receive the output of the PCM to linear converter 10 and to output data to the adaptive filter 2.

In this example, the signals RIN and SIN contain speech sampled at 8 kHz. The format of the signals RIN, SIN, ROUT and SOUT is 8-bit compressed PCM, compressed using an A-law or U-law compander. Since the echo is delayed for up to 64ms, it is necessary to store 64ms of RIN samples to be subtracted from the signal SIN. These samples are stored in the memory portion 8 and accordingly the memory portion requires N locations, where N is 64ms/1251ls = 512.

Improvements can be made to the above echo canceller architecture that may result in a smaller chip area and a more flexible scheme.

According to a first aspect of the present invention there is provided memory access circuitry, for use with a memory device addressable within a predetermined normal addressing range, comprising: mapping means for mapping an access address to a mapped address falling within said predetermined normal addressing range and for causing data stored in said memory device in an internal format to be retrieved based on said mapped address; and function processing means for determining within which one of a number of function addressing ranges the access address falls and for processing the retrieved data in dependence upon the determined function addressing range to produce data in an external format.

The memory device may be random access memory. The access address, which is the address of an access to the memory device, may comprise a lower portion containing the least significant bits of the access address and an upper portion containing the most significant bits of the access address, and the mapping means may conveniently perform its mapping by using the lower portion as the mapped address. The function processing means may conveniently determine the function addressing range of the access address by examining the upper portion of the access address.

The function processing means may comprise a plurality of converters each for processing the retrieved data in dependence upon a different one of the function addressing ranges. The converters may perform their processing in parallel, or alternatively only the converter corresponding to the determined function addressing range may process the retrieved data. The memory access circuitry may further comprise a multiplexer for receiving the respective outputs of the converters, the output of the mutiplexer being selected in dependence upon the determined function addressing range.

When the function processing means determine that the access address falls within a function addressing range requiring no modification of the retrieved data the external format is preferably the same as the internal format, otherwise the external format is different from the internal format.

According to a second aspect of the present invention there is provided memory access circuitry for use with a memory device addressable within a predetermined normal addressing range, comprising: function processing means for determining within which one of a number of function addressing ranges an access address falls and for processing data in an external format in dependence upon the determined function addressing range to produce data in an internal format; and mapping means for mapping said access address to a mapped address falling within said predetermined normal addressing range and for causing said processed data to be stored in said memory device based on said mapped address.

According to a third aspect of the present invention there is provided a memory access method for use with a memory device addressable within a predetermined normal addressing range, comprising the steps of: determining within which one of a number of function addressing ranges an access address falls; mapping said access address to a mapped address falling within said predetermined normal addressing range; retrieving data stored in said memory device in an internal format based on said mapped address; and processing said retrieved data in dependence upon the function addressing range determined in said determining step to produce data in an external format.

According to a fourth aspect of the present invention there is provided a memory access method, for use with a memory device addressable within a predetermined normal addressing range, comprising the steps of: determining within which one of a number of function addressing ranges an access address falls; mapping said access address to a mapped address falling within said predetermined normal addressing range; processing data in an external format in dependence upon the function addressing range determined in said determining step to produce data in an internal format; and storing said processed data in said memory device based on said mapped address.

According to a fifth aspect of the present invention there is provided echo canceller apparatus comprising: echo cancelling means for employing a sequence of outgoing data samples to cancel echo in a sequence of incoming data samples; memory means for storing said sequence of outgoing data samples in a first format; and memory access means arranged between said memory means and said echo cancelling means for converting data samples retrieved from said memory means from said first format to a second format for use by said echo cancelling means.

The echo canceller apparatus may comprise conversion means for converting the sequence of incoming data samples from a third format into the second format for use by the echo cancelling means. The first and third formats may be compressed formats and said second format may be an uncompressed format. The first format may be the same as the third format. The incoming and outgoing data samples may be pulse code modulated samples. At least one of the first and third formats may be the compressed u-law format or the compressed A-law format.

The echo canceller apparatus may be voice echo canceller apparatus with the incoming and outgoing data samples being voice samples.

The memory access means may comprise memory access circuitry according to the first aspect of the present invention, with the memory means of the fifth aspect being the memory device of the first aspect, the first format of the fifth aspect being the same as the internal format of the first aspect and the second format of the fifth aspect being the same as said external format of the first aspect. s

According to a sixth aspect of the invention there is provided an echo cancelling method comprising the steps of: storing in a memory unit a sequence of outgoing data samples in a first format; employing an echo cancelling unit to cancel echo in a sequence of incoming data samples using said sequence of outgoing data samples; and converting data samples retrieved from said memory unit from said first format to a second format for use by said echo cancelling unit.

According to a seventh aspect of the invention there is provided voice echo canceller apparatus comprising memory access circuitry according to the first aspect of the present invention.

According to an eighth aspect of the invention there is provided a voice echo canceller method comprising memory access method steps according to the third aspect of the present invention.

According to a ninth aspect of the invention there is provided an operating program which, when loaded into an echo canceller device, causes the device to become apparatus according to the fifth or seventh aspects of the present invention.

According to a tenth aspect of the invention there is provided an operating program which, when run in an echo canceller device, causes the device to carry out a method according to the sixth aspect of the present invention.

Reference will now be made, by way of example, to the accompanying drawings, in which: Figure 1, discussed hereinbefore, is a block diagram showing a typical echo canceller architecture; Figure 2, also discussed hereinbefore, is a block diagram showing a typical echo canceller architecture in more detail; Figure 3 is a block diagram showing an echo canceller architecture embodying the present invention; Figure 4 is a block diagram showing memory access circuitry according to a first embodiment of the present invention; ! Figure 5 is an illustrative flow diagram showing the operation of the memory access circuitry shown in Figure 4; Figure 6 is a block diagram showing the memory access circuitry of the first embodiment in more detail; Figure 7 is a table showing the correspondence between the ADDF signal of Figure 6 and the function to be performed by the function processing unit; Figure 8 is a table showing the correspondence between the function addressing ranges and the format of the data EDAT; and Figure 9 is a block diagram showing memory access circuitry according to another embodiment of the present invention.

Because the adaptive filter 2 described above with reference to Figure 2 operates on uncompressed data, the samples within the RIN and SIN signals must be converted from PCM to linear as they enter the echo canceller the echo canceller outputs must be converted back to PCM format as they leave the echo canceller. The samples are therefore stored in the memory portion 8 in uncompressed format, leading to an increase in the size of the memory.

Figure 3 is a block diagram showing a voice echo canceller embodying the present invention. The voice echo canceller of Figure 3 differs from that in Figure 2 by having a PCM to linear converter 16 arranged between the memory portion 8 and the adaptive filter 2, instead of the converters 10 and 12 of Figure 2. This allows the R1N data to be stored in compressed format and therefore saves memory area. The stored RIN data is converted to linear format by the PCM to linear converter 16 as it is read from the memory portion 8 and before being received by the adaptive filter 2.

The function performed by the adaptive filter 2 can either be implemented as a program running on a digital signal processor or central processing unit, or alternatively the adaptive filter 2 can be implemented in hardware. A standard PCM to linear converter can be used as the PCM to linear converter 16 in Figure 3 to convert all of the RIN data stored in the memory portion 8 before it reaches the adaptive filter 2.

However, it is preferable that the adaptive filter 2, whether it is implemented using a digital signal processor, central processing unit or hardware block, has access to the compressed values actually stored in the memory portion 8 for debug and test purposes.

For improved functionality, it is also desirable that the conversion which takes place between the memory portion 8 and the adaptive filter 2 can be configured or changed depending on the format of the RIN data stored in the memory portion 8. For example, the RIN data may be stored in the memory portion 8 as PCM data compressed using either G711 u-law or A-law. The adaptive filter 2 may also usefully have the data read out in an alternative compressed format, for example either zero-filled upper byte or sign-extended upper byte format.

One possibility for implementing such a configurable scheme would be to have the RIN data stored in the memory portion 8 in the various required formats so that the adaptive filter 2 has direct access to the data in any one of those formats. However, this requires an increase in the size of the required memory.

Figure 4 is a block diagram showing memory access circuitry according to an embodiment of the present invention. The memory access circuitry comprises a mapping unit 26 and a function processing unit 28 arranged between a central processing unit 24 and a memory unit 22. The memory access circuitry is suitable for use with a voice echo canceller embodying the present invention as shown in Figure 3, where the memory unit 22 of Figure 4 corresponds to the memory portion 8 shown in Figure 3 and the central processing unit 24 of Figure 4 corresponds to the adaptive filter 2 shown in Figure 3.

In the embodiment shown in Figure 4, an access address ADDR is passed from the central processing unit 24 to the mapping unit 26 and a mapped address ADDM is passed from the mapping unit 26 to the memory unit 22. A function identifying signal ADDF is passed from the mapping unit 26 to the function processing unit 28. Data IDAT in an internal format is passed from the memory unit 22 to the function processing unit 28 and data EDAT in an external format is passed from the function processing unit 28 back to the central processing unit 24.

Operation of the memory access circuitry shown in Figure 4 will now be described in more detail with reference to the illustrative flow diagram shown in Figure 5.

The memory unit 22 is addressable within a predetermined normal addressing range 36 shown in Figure 5, so that any of the data stored in the memory unit 22 in an internal format can be accessed using an address within that predetermined normal addressing range 36. However, with memory access circuitry embodying the present invention, an access request can be made by the central processing unit 24 using an address ADDR falling outside of the predetermined normal addressing range 36 of the memory unit.

The addressing range 38 within which the access address EDDR falls comprises a number of function addressing ranges A, B. C and D. The function addressing range within which the access address ADDR falls determines the format of the data EDAT eventually returned to the central processing unit 24. In the example shown in Figure 5, the access address ADDR falls within the function addressing range C, and this information is passed to the function processing unit 28 using the function identifying signal ADDF.

The mapping unit 26 maps the access address ADDR falling within function addressing range C to a mapped address ADDM falling within the predetermined normal addressing range 36 of the memory unit 22. Data IDAT in the internal format is retrieved from the memory unit 22 based on this mapped address ADDM and passed to the function processing unit 28. The processing unit 28 processes the data IDAT according to the selected function C to produce data EDAT in the external format and passes this data to the central processing unit 24.

Figure 6 shows one possible implementation of the mapping circuitry embodying the present invention described above with reference to Figures 4 and 5. In particular, the implementation shown in Figure 6 shows in more detail the structure of the mapping unit 26 and the function processing unit 28.

In this specific embodiment, the memory unit 22 holds 512 compressed data values, requiring 9 address bits addr[8:0] of the address bus to access all of the compressed data values. If the central processing unit 24 has a 16-bit address bus, bits addr[15:9] would usually be decoded as a memory/chip select signal to access a particular memory or chip on the board. If this particular memory unit 22 were to be selected when all of the address bits addr[15:9] were zero then the memory unit 22 would be mapped from 000H to 1FFH. This would be the normal addressing range of the memory unit 22.

However, in this embodiment address bits addr[10:9] are used to select the data format and address bits addr[15:11] are used to select accesses to the memory unit 22. The correspondence between the values of the address bits addr[10:9] is shown in Figure 7.

For example, when addr[10:9] equals "10", this indicates that the data IDAT retrieved from the memory unit 22 in the internal (compressed) format is to be decompressed using A-law. On the other hand, when addr[10:9] equals "00", this indicates that no processing is to be performed and that the data IDAT is to be passed unchanged to the central processing unit 94 as external data EDAT, so that IDAT is the same as EDAT.

As shown in Figure 6, in this particular embodiment, the mapping unit 26 performs the function of mapping the access address ADDR to a mapped address ADDM falling within the predetermined normal addressing range 36 of the memory unit 22 by splitting off the address bits addr[8:0] to form the mapped address ADDM. The other address bits addr[10:9], which determine the function to be performed by the function processing unit 28, is merely passed to the function processing unit 28 as ADDF.

The function processing unit 28 uses these address bits addr[10:9] to control a multiplexer 34. The function processing unit 28 further comprises three converters 32 to 323. These converters 32 to 323 receive the data IDAT from the memory unit 22 and their respective outputs are passed to the multiplexer 34. The multiplexer 34 further receives the data IDAT direct from the memory unit 22. The converters 32 to 323 process the data IDAT according to one of the functions selected by address bits addr[10:9].

The access address ADDR therefore comprises a lower portion ADDM containing the least significant bits of the access address ADDR and an upper portion ADDF containing the most significant bits of the access address ADDR, and the mapping unit 26 uses the lower portion as the mapped address ADDM. The function addressing range is determined by examining the upper portion ADDF of the access address ADDR. In this specific embodiment, the upper portion ADDF is used to select one of the inputs to the multiplexer 34 in the function processing unit 28 as the data EDAT to be passed to the processing unit 24.

Figure 8 shows the correspondence between the function addressing range within which the access address ADDR falls and the format of the data EDAT returned to the central processing unit 24. The effect of employing memory access circuitry embodying the present invention is that the memory unit 22 appears to have 2048 locations which are mapped according to the arrangement shown in the table of Figure 8. The advantage is therefore that the central processing unit 24 has access to all of the formats of the data whilst still requiring only a 512-location memory unit 22. The memory access circuitry does not impose an undue delay in accessing data in a variety of formats because a hardware compander can decompress data in less than one clock cycle. The technique can be extended if the processing by the memory access circuitry takes too long by adding wait states decoded from the address bus.

It will be appreciated that the correspondence between the function addressing ranges of ADDR and the format of the processed data EDAT need not be as is shown in the table of Figure 8. For example, a function addressing range A from 000 to 1FFH could be used to indicate that decompression using u-law is required and the function addressing range C from 400 to SFFH could be used to indicate that no processing is required at all.

It is also not essential that the first function addressing range A coincides with the predetermined normal addressing range of the memory unit 22. For example, as shown in Figure 5, the function addressing range A could be smaller than the predetermined normal addressing range 36 and can be mapped in any desired way into the predetermined normal addressing range 36; for example, the mapping need not be a direct mapping. Likewise, the mapping performed to map an access address ADDR falling within the function addressing region D need not be a direct mapping into the predetermined normal addressing range 36, but could, for example, be an inverse mapping or any other type of mapping.

It is also possible that two function addressing ranges overlap, such that for example an access address falling within the range of overlap indicates that dual processing according to both associated functions should be performed. In this case, the range of overlap can be regarded as a range separate to the adjacent non-overlapping ranges with its own associated function (the dual processing function).

The memory access circuitry embodying the present invention described above with reference to Figure 6 is intended for post-processing data as it leaves the memory unit 22 and before it is received by the processing unit 24. Figure 9 shows memory access circuitry according to another embodiment of the present invention in which pre- processing is performed on data before it is stored in the memory unit 22 to convert data EDAT in an external format into data IDAT for storing in the memory unit 22. The memory access circuitry shown in Figure 9 operates in much the same way as that shown in Figure 6, with the components in the data path being reversed. Much of the description above therefore applies generally to the circuitry of Figure 9.

The above description with reference to Figure 3 refers to a program running on a digital signal processor or central processing unit. Such an operating program embodying the present invention could be stored on a computer-readable medium, but could also be embodied, for example, in a signal such as a downloadable data signal provided from an Internet website. The appended claims are to be interpreted as covering an operating program by itself, or as a record on a carrier, or as a signal, or in any other form.

Claims

CLAIMS: 1. Memory access circuitry, for use with a memory device

addressable within a predetermined normal addressing range, comprising: mapping means for mapping an access address to a mapped address falling within said predetermined normal addressing range and for causing data stored in said memory device in an internal format to be retrieved based on said mapped address; and function processing means for determining within which one of a number of function addressing ranges said access address falls and for processing said retrieved data in dependence upon the determined function addressing range to produce data in an external format.
2. Memory access circuitry as claimed in claim 1, wherein said access address comprises a lower portion containing the least significant bits of said access address and an upper portion containing the most significant bits of the access address, and wherein said mapping means perform said mapping by using said lower portion as said mapped address.
3. Memory access circuitry as claimed in claim 1 or 2, wherein said access address comprises a lower portion containing the least significant bits of said access address and an upper portion containing the most significant bits of the access address, and wherein said function processing means determine the function addressing range of said access address by examining said upper portion of said access address.
4. Memory access circuitry as claimed in any preceding claim, wherein said function processing means comprise a plurality of converters each for processing said retrieved data in dependence upon a different one of the function addressing ranges.
5. Memory access circuitry as claimed in claim 4, wherein said converters perform their processing in parallel.
6. Memory access circuitry as claimed in claim 4, wherein only the converter corresponding to the determined function addressing range processes said retrieved data.
7. Memory access circuitry as claimed in claim 4, 5 or 6, further comprising a multiplexer for receiving the respective outputs of said converters, the output of the mutiplexer being selected in dependence upon the determined function addressing range.
8. Memory access circuitry as claimed in any preceding claim wherein when said function processing means determine that said access address falls within a function addressing range requiring no modification of said retrieved data said external format is the same as said internal format, otherwise said external format is different from said internal format.
9. Memory access circuitry, for use with a memory device addressable within a predetermined normal addressing range, comprising: function processing means for determining within which one of a number of function addressing ranges an access address falls and for processing data in an external format in dependence upon the determined function addressing range to produce data in an internal format; and mapping means for mapping said access address to a mapped address falling within said predetermined normal addressing range and for causing said processed data to be stored in said memory device based on said mapped address.
10. A memory access method, for use with a memory device addressable within a predetermined norma] addressing range, comprising the steps of: determining within which one of a number of function addressing ranges an access address falls; mapping said access address to a mapped address falling within said predetermined normal addressing range; retrieving data stored in said memory device in an internal format based on said mapped address; and processing said retrieved data in dependence upon the function addressing range determined in said determining step to produce data in an external format.
11. A memory access method, for use with a memory device addressable within a predetermined normal addressing range, comprising the steps of: determining within which one of a number of function addressing ranges an access address falls; mapping said access address to a mapped address falling within said predetermined normal addressing range; processing data in an external format in dependence upon the function addressing range determined in said determining step to produce data in an internal format; and storing said processed data in said memory device based on said mapped address.
12. Echo canceller apparatus comprising: echo cancelling means for employing a sequence of outgoing data samples to cancel echo in a sequence of incoming data samples; memory means for storing said sequence of outgoing data samples in a first format; and memory access means arranged between said memory means and said echo cancelling means for converting data samples retrieved from said memory means from said first format to a second format for use by said echo cancelling means.
13. Echo canceller apparatus as claimed in claim 12, further comprising conversion means for converting said sequence of incoming data samples from a third format into said second format for use by said echo cancelling means.
14. Echo canceller apparatus as claimed in claim 13, wherein said first and third formats are compressed formats and said second format is an uncompressed format.
15. Echo canceller apparatus as claimed in claim 14, wherein said first format is the same as said third format.
16. Echo canceller apparatus as claimed in claim 15, wherein said incoming and outgoing data samples are pulse code modulated samples.
17. Echo canceller apparatus as claimed in claim 14, 15 or 16, wherein at least one of said first and third formats is the compressed u-law format.
18. Echo canceller apparatus as claimed in claim 14, 15 or 16, wherein at least one of said first and third formats is the compressed A-law format.
19. Echo canceller apparatus as claimed in any one of claims 12 to 18, being voice echo canceller apparatus with said incoming and outgoing data samples being voice samples.
20. Echo canceller apparatus as claimed in any one of claims 12 to 19, wherein said memory access means comprise memory access circuitry as claimed in any one of claims 1 to 8, said memory means comprising said memory device, said first format being the same as said internal format and said second format being the same as said external format.
21. An echo cancelling method comprising the steps of: storing in a memory unit a sequence of outgoing data samples in a first format; employing an echo cancelling unit to cancel echo in a sequence of incoming data samples using said sequence of outgoing data samples; and converting data samples retrieved from said memory unit from said first format to a second format for use by said echo cancelling unit.
22. Memory access circuitry substantially as hereinbefore described with reference to Figures 3 to 9 of the accompanying drawings.
23. A memory access method substantially as hereinbefore described with reference to Figures 3 to 9 of the accompanying drawings.
24. Echo canceller apparatus substantially as hereinbefore described with reference to Figures 3 to 9 of the accompanying drawings.
25. Voice echo canceller apparatus comprising memory access circuitry as claimed in any one of claims 1 to 8 and 22.
26. A voice echo canceller method comprising memory access method steps as claimed in claim 10 or 23.
27. An operating program which, when loaded into an echo canceller device, causes the device to become apparatus as claimed in any one of claims 12 to 20, 24 and 25.
28. An operating program which, when run in an echo canceller device, causes the device to carry out a method as claimed in claim 21, 23 or 26.
29. An operating program as claimed in claim 27 or 28, carried on a carrier medium.
30. An operating program as claimed in claim 29, wherein the carrier medium is a transmission medium.
31. An operating program as claimed in claim 29, wherein the carrier medium is a storage medium.