GB2398426A - Process for recognising the end point of etching of a semiconductor, an etching process and apparatus - Google Patents

Abstract

A process for etching a semiconductor is proposed, whereby the rate of erosion of the semiconductor 30, 31 is adjusted by adjusting the polarity and/or density of free charge caters in the semiconductor. A process for recognising an etching end point, a material junction or an interface while etching a semiconductor 30, 31, is also described. Zone 32 in the semiconductor has inhomogeneous charge carrier density and/or inhomogeneous charge carrier polarity, in particular a p-n junction. A voltage is applied to the zone during etching and the current induced in the zone is measured. The point where etching reaches zone 32 is determined from a change in the current. This process is suitable for recognising the end pint of etching silicon using C1F3 or Br F3 gases, or anisotropic plasma etching. Apparatus suitable for the processes is described.

Description

A process for etching a semiconductor, the use thereof to recognise the

end point of etching and a device for performing same The invention relates to a process for recognizing an end point, a material junction or an interface when etching a semiconductor, the use thereof to detect the end point of etching during the gas phase etching of silicon substrates, a process for etching a semiconductor with a gaseous medium and a device for etching a semiconductor, in particular for performing the said process, in accordance with the type in the independent Claims.

When using etching gases such as chlorine trifluoride (ClF3) or bromine trifluoride (BrF3), silicon is spontaneously etched after adsorption of these compounds on a silicon surface due to the release of fluorine radicals which react with silicon atoms on the accessible silicon surface to form spontaneously volatile silicon fluoride compounds which then leave the surface. In this respect, erosion of silicon takes place everywhere that silicon and the etching gas used come into contact with each other.

In this case it is known that the rate of etching increases with decreasing temperature of the silicon surface and increasing partial pressure of the process gas.

Furthermore, it is known that when using these etching processes, rates of erosion of more than 10 Am per minute are possible at appropriately high pressures within the range from a few mbar up to a few lOs of mbar, an appropriate rate of supply of the reactive gas from a few lOOs of scam (cm3 gas flow per minute at a pressure of 1 bar) up to a few slm (dm3 gas flow per minute at a pressure of 1 bar) and a low substrate temperature of, for example, -20 C to +20 C. Etching continues for as long as a suitable process gas and silicon are available.

The gas phase etching process for silicon explained above using a halogen trifluoride has the advantage, as compared with most non-silicon materials, of extraordinarily high selectivity so that it is very easy to mask this etching.

In particular quite thin photolacquer masks, hard substance layers of SiO2, silicon nitride or silicon oxynitride, are sufficient for use as masking layers in order to define the areas of silicon to be etched and the areas of silicon not to be etched. In practice, these types of masking layers cannot be eroded to a measurable extent so that even very deep or prolonged etching of silicon is possible without the need for thick masking layers.

Finally, it is known that silicon which is locally masked, or even unmasked, can be etched by directed supply of the etching gas onto a silicon surface, for example using a nozzle or other discharge device, for example by moving the nozzle about over the silicon surface. In this respect, it is even possible to "write" on silicon or to "cut" silicon in this way.

An advantageous feature of the spontaneous gas phase etching of silicon described above is that no plasma, or similar excitation of the reactive gas, is required at all.

In this respect, this process is continually gaining in importance in sacrificial layer techniques in the silicon micromechanics field, in particular for preparing caverns and membranes, for example for pressure sensors, hot-film sensors, microphones, etc. and also in general for structures where it is not so very critical to achieve lateral dimensional accuracy and a certain degree of undercutting of edges can be tolerated.

The advantages of gas phase etching of silicon as compared with nonsilicon materials, in addition to the high selectivity mentioned above, are the simplicity of the etching devices used and the very high rates of erosion at low gas costs.

A very disadvantageous feature when preparing micromechanical structures, for example caverns or membranes, with a process of this type, however, is the lack of a simple and effective etching stop. In this respect, it has hitherto been simple to etch a cavern to be produced in a silicon wafer deep enough for a hole to be produced in the wafer, or else the production of a membrane or cavern with a preset defined thickness or depth takes place in a purely time-controlled manner, which is difficult to control and is also inaccurate.

The process according to the invention and the device according to the invention use the observation that the etched erosion of semiconductors, in particular silicon structures, depends substantially on the charge carrier density and the charge carrier polarity in the etched semiconductor. Surprisingly, it was found in particular that, during the gas phase etching of silicon substrates, e-doped silicon is etched much more deeply than p-doped silicon. Therefore the effect of charge carrier polarity or charge carrier density due to the targeted adjustment of an inhomogeneous charge carrier density and/or an inhomogeneous charge carrier polarity in a zone in which the processes according to the invention are used can produce, in a simple manner, a type of "electrochemical etching stop", like that known from KOH wet-etching technology, within the etched semiconductor or silicon wafer so that this is no longer etched, or only etched at a considerably reduced rate, selectively in a localised area.

In this respect, the process according to the invention is also especially suitable for recognizing an end point, a material junction or an interface within a semiconductor which is characterized by an inhomogeneous charge carrier density and/or an inhomogeneous charge carrier polarity.

A suitable criterion for reaching these zones is advantageously the measurement of an electric current which is induced by applying an electric voltage to the zone with inhomogeneous charge carrier density and/or inhomogeneous charge carrier polarity.

It was found that this induced electric current changes considerably during etching, in particular rises, when the zone with the inhomogeneous charge carrier density and/or inhomogeneous charge carrier polarity is reached in the etching process. In this respect, this current is a very good criterion for monitoring the progress of etching and for determining the depth of etching reached in the semiconductor.

In this connection, it was also found that, when etching a semiconductor with a gaseous etching medium, for example bromine trifluoride or chlorine trifluoride, in the event that silicon is the semiconductor, the rate of erosion of the semiconductor during etching can be adjusted in a very defined manner and in particular can also be altered locally, by localized adjustment of the polarity and/or the density of the free charge carrier in the semiconductor.

Thus, the opportunity to alter the rate of etching and in particular also to interrupt the etching process regionally within the semiconductor is also gained.

The device according to the invention has the advantage, as compared with the prior art, of a very simple construction and low investment costs because it can be made just by simple modification of a conventional etching device for semiconductors, this having to be supplemented only by a few simple components.

Advantageous further developments of the invention are given by the measures mentioned in the sub-claims.

Thus, surprisingly, it was found that the surface-catalytic dissociation of the C1F3 molecule or the BrF3 molecule on a silicon surface or the release of fluorine radicals depends substantially on the available electron density in the silicon and that in this way the rate of erosion in silicon can be controlled very simply via the electron density in the semiconductor material. Thus, the process according to the invention enables, very advantageously, the production of an etching stop which is expressed to a greater or lesser extent, as required, for the gas phase etching of silicon using C1F3 or BrF3 in order to produce in this way, for example, pressure sensor membranes with a defined thickness.

Furthermore, it is advantageously also possible, in addition to providing an etching stop, i.e. an interruption in etching on reaching a zone, layer or island, the position of which is defined, produced or known and which has pre-adjusted properties due to its electrical properties, i.e. charge carrier density and charge carrier polarity, to detect an end- point directly during etching via the change in an electric current on reaching this zone.

Furthermore, the detection of an end-point, or more generally a material junction or an interface, when etching a semiconductor by the application of an electric voltage and measurement of an electric current induced in this way, is a universal method which can be used not only during the gas phase etching of silicon using chlorine trifluoride or bromine trifluoride but is also extremely suitable for recognising the end-point during plasma etching, for example of the type in DE 42 41 045 C1, for example when producing membranes.

Thus the device according to the invention and the process according to the invention enable a very economic and, for many applications, a sufficiently precise production of micromechanical structures where it is not absolutely necessary to use expensive plasma sources and where in particular cost-effective process gases can be used.

The invention is explained in more detail by using the drawing and the description given below. Figure 1 shows a schematic diagram, in section, of a plasma etching device for performing the process according to the invention.

Figure 1 shows an etching device 5 suitable for performing the processes described in the following, with a vacuum chamber 10 and a gas inlet 20, wherein the process gashes) are supplied to the vacuum chamber 10 via gas inlet 20 from pressurized containers 22 via downstream flow-controllers 21. In the example described, the process gas is ClF3, which has a sufficiently high vapour pressure to be supplied via conventional flowcontrollers 21, or BrF3, when special flow-controllers 21 are required due to its low vapour pressure at room temperature, of about 7 mbar. Besides, in figure 1, it may also be provided that pressurised containers 22 and/or the pipes or flow-controllers 21 used are heated in order to avoid the formation of a condensate and/or to increase the vapour pressure of the process gas BrF3.

In the vacuum chamber 10 used as a process chamber, a substrate electrode 40 is also provided, on which a silicon wafer 25, as a semiconductor, is firmly clamped. The silicon wafer 25 in the example described is in particular homogeneously p-doped and has a e-doped epitaxial layer 31 on the face turned towards the substrate electrode 40. In this respect, a zone 32 in the form of a pn-interface between the p-doped region 30 and the e-doped region 31 is present within silicon wafer 25 which consists of a p-doped region 30 and the e-doped epitaxial layer 31.

Furthermore, it is provided in figure 1 that clamping the silicon wafer 25 to the substrate electrode 40 takes place via a conventional electrostatic chuck 41, in particular a holding device for the silicon wafer 25 such as is described in detail in DE 101 56 407.4, by means of which the other face of the silicon wafer 25 lying on substrate electrode 40 is protected from the process gases in the vacuum chamber 10. In addition, it is provided in figure 1 that contact springs, contact tips, contact needles or more generally electric contact agents starting out from substrate electrode 40 project through electrostatic chuck 41, or alternatively also a corresponding mechanical clamping device for silicon wafer 25, and are connected in an electrically conducting manner to corresponding contacts on the face of silicon wafer 25 turned towards substrate electrode 40 and thus make electrical contact with these.

These contact springs or contact tips are used to apply a blocking voltage at the pn-junction 32 or zone 32 in the silicon wafer 25, with this operating in the same way as in a diode.

The applied blocking voltage is preferably a direct voltage the polarity of which is chosen in such a way that the smallest possible electric current flows to the pn- junction. Its amplitude is between 5 volts and 30 volts, wherein the highest possible voltage has a more pronounced effect on the rate of etching, i.e. it is preferred that the highest possible electric voltage is applied, this being determined empirically in the individual case and being highly dependent on the wafer material used, i.e. for example on the quality and extent of the pn-junction.

In accordance with figure 1, it is also provided that the face of silicon wafer 25 lying on substrate electrode 40 is subjected to helium via electrostatic chuck 41 in order to achieve good thermal connection of the silicon wafer 25 to substrate electrode 40 and at the same time to achieve additional isolation of the lower face of the silicon wafer 25 from process gases in vacuum chamber 10. In addition to that, corrosion of the electric contact agents connected to silicon wafer 25 is prevented.

The substrate electrode 40 also has, in accordance with figure 1, electric lead wires 42 for electrical contact of silicon wafer 25, electrostatic chuck 41 and optionally provided electric heating elements, which may be integrated in substrate electrode 40, in order thereby to adjust the temperature of silicon wafer 25. Electric lead wires 42 are also used to transmit an electric current induced in the region of zone 32, i.e. the pn-junction produced, by the electric voltage applied which, due to the polarity of the applied electric voltage, is a blocking-state current or leakage current of a diode, to the outside and there to measure it. For this purpose, conventional electric components are provided outside vacuum chamber 10 with which, one the one hand, zone 32 can be subjected to the desired electric voltage and with which, on the other hand, an electric current induced in zone 32 by the electric voltage can be measured. Furthermore, measurement data relating to the temperature of substrate electrode 40 or the helium rear face pressure of electrostatic chuck 41 can be transferred to the outside via electric lead wires 42.

Substrate electrode 40 also has a gas supply 43 with which preferably helium, as a convection medium for cooling silicon wafer 25 during etching, is supplied at a pre- adjustable pressure. The pressure of the helium supplied should be greater than that of the intended process pressure in vacuum chamber 10, i.e. it is, for example, mbar to 20 mbar higher than the process pressure. The helium pressure is preferably supplied, in the case of a variable process pressure in the vacuum chamber 10, in such a manner that there is always a constant difference. Figure 1 also shows an optionally provided cooling agent supply 44 with which, if required, substrate electrode 40 can be supplied with a cooling agent which circulates in substrate electrode 40 in order to adjust its temperature and in particular to dissipate the heat of reaction being produced on silicon wafer 30 during etching due to an exothermal etching reaction. The temperature of silicon wafer 30 is preferably -20 C to 30 C in order to achieve optimum etching conditions and optimum masking selectivity.

Fluorinerts or an ethylene glycol/water mixture is for example suitable for use as a cooling agent which is supplied via cooling agent supply 44.

Etching device 5 is finally provided with a rotary pump 80 which is preferably specified as a dry-running pump. This is used to evacuate etching device 5 after it has been aerated and as a process pump in order to pump out the process gases supplied while performing the etching process. Furthermore, a control valve 70 is provided to control the pressure and a conventional Baratron or a combined Baratron/Ionivac is provided as pressure gauge 90 to measure the pressure. Pressure gauge 90 and control valve 70 are used primarily to set the desired process pressure which is, for example, 5 mbar to 100 mbar, preferably 30 mbar, in as stable a manner as possible during processing of silicon wafer 25. Finally, etching device 5 has a turbopump 60 connected to a cut-off valve 50 which is used to achieve as good a final vacuum as possible, in particular a vacuum better than 10-4 Pa, before and after processing of a silicon wafer 25. This is important because, on the one hand, residual moisture in etching device 5 or on silicon wafer 25 would have a sensitive detrimental effect on the gas phase etching process performed and, on the other hand, it is absolutely essential to avoid the presence of residues of the process gas prior to removing silicon wafer 25 from etching device 5.

During etching, turbopump 60 is separated from vacuum chamber 10 by cutoff valve 50 since it cannot be used for the actual etching process due to the process pressures used then, these being in the mbar range. Furthermore it is advantageous if etching device 5 in accordance with figure 1 also has a, not shown, material transfer device in order to be able to insert and remove silicon wafer 25 without gas exchange with the surroundings.

To process the silicon wafer 25, this is inserted in etching device 5 and first clamped onto substrate electrode with the aid of electrostatic chuck 41. Silicon wafer 25 is oriented in such a way that appropriately provided contact springs or contact faces on the lower face of silicon wafer 25 and contact springs on the upper face of substrate electrode 40 meet each other. After completion of the, for example, electrostatic or alternatively also mechanical clamping procedure, the face of silicon wafer 25 turned towards substrate electrode 40 is then subjected to helium and, as explained above, a blocking voltage is applied to zone 32 or the pn-junction present there in the interior of silicon wafer 30. Then vacuum chamber 10 is pumped out using turbopump 60 until the desired base vacuum is reached. Then cut-off valve 50 is closed. Now, using flowcontroller 21, the desired amount of process gas is supplied, for example 100 scam to 1 slm of ClF3. At this point, the pressure inside vacuum chamber 10 is measured, in particular constantly, using pressure gauge 90 and stabilized at the desired value by means of the combination of rotary pump 80 and control valve 70. Silicon wafer 25 is now etched spontaneously until a rise in the blocking current in the region of the pn-junction 32 is measured using a, not shown, current meter which is connected to electric lead wire 42 and thereby to zone 32. This rise in the blocking current above a pre-set threshold value, signals that the e- doped epitaxial layer 31 has been reached, i.e. etching through of the p- doped region 30 of silicon wafer 25. After exceeding the threshold value for the blocking current, the process gas supply is first stopped and then vacuum chamber 10 is evacuated. Lastly, on opening cut-off valve 50, turbopump 60 then takes over pumping out to the lowest possible final pressure so that when this is achieved silicon wafer 25 can be removed from etching device 5 using a, not shown in figure l, material transfer device.

The process according to the invention is explained further using the example of the p-doped silicon wafer 25 in accordance with figure 1, on one face of which epitaxial layer 31 has been grown, the thickness of this layer being intended to correspond, for example, to the thickness of a membrane required subsequently for a pressure sensor.

To etch a cavern on the rear face of silicon wafer 25, i.e. the face of silicon wafer 25 turned away from the e-doped epitaxial layer 31, this face is first masked with, for example, a photolacquer so that only those surface regions of the silicon wafer 25 are exposed, and thus accessible to the etching gas used, where the desired cavern is intended to be produced. For the etching process itself, silicon wafer 25 is then preferably plated "face down", i.e. with the e-doped epitaxial layer 31 downwards, onto substrate electrode 40, via which both the e-doped epitaxial layer 31 and also the p-doped substrate material of the silicon wafer 25, i.e the p-doped region 30 can make electrical contact. For this purpose, spring pins as explained above or other types of electrical contacts, are provided on the face of the substrate electrode, while silicon wafer 25 has access to contact fields assigned to these. Furthermore, during etching the p-doped region 30 is subjected to a negative electric voltage and e-doped epitaxial layer 31 is subjected, in contrast, to a positive voltage. The two- dimensional pn-diode formed by p-doped region 31 and n doped epitaxial layer 31 is thus polarised in the blocking direction so that only a very low blocking current flows and moreover high voltages, up to below the breakthrough limit for the diode, can also be applied. In this case, furthermore, it is not the overall electric potential applied to silicon wafer 25 which is critical, rather merely the potential differences within silicon wafer 25, i.e. in particular across zone 32.

As a result of the polarised pn-diode, or pn-junction polarized in this manner, in zone 32, as explained above, negative charge carriers (electrons) are injected into the p-doped regions 30 of silicon wafer 25, whereas the e-doped epitaxial layer 31 is depleted in electrons, these being withdrawn by the source of voltage connected via electric lead wires 42.

Here, the observation that negative charge carriers are required for the gas phase etching process performed is essential because it supports the surface catalytic dissociation of C1F3 and BrF3, whereas a lack of electrons slows down the etching process to a corresponding extent.

Thus, if the etching front reaches the e-doped epitaxial layer 31 after fully etching the p-doped region 31 or the silicon material in the cavern region, etching is slowed down there by the prevailing charge carrier depletion zone or comes to a standstill, depending on the extent of charge carrier depletion. At the same time, pn-junction 32, which is initially located in the interior of silicon wafer 25 and thus protected from the surroundings, is uncovered, i.e. amplified leakage currents appear due to exposure of the pn-junction 32, this being measured by an appropriate current meter and using electric lead wires 42 and can be used as an indicator of the end of the etching process, i.e. in the example used as an illustration, the fact that e-doped epitaxial layer 31 has been reached.

Thus, using the process explained above, a membrane with a defined thickness which corresponds to the thickness of n- doped epitaxial layer 31, can be produced, wherein the blocking current exceeding a pre-defined threshold value is used as the termination criterion.

At the end of the process therefore, on the one hand etching is slowed down or even stopped completely on reaching the electrically biased pnjunction 32 and, on the other hand, a decision can be made, which then ends further processing, as a result of the rise in leakage current which flows across pn-junction 32, to stop the gas supply of reactive gas to silicon wafer 25 via flow-controller 21, to evacuate etching device 5 and to remove silicon wafer 25. Thus, on the one hand, an automatic decrease in the rate of etching, to a greater or lesser extent, is achieved on reaching the etching target and, on the other hand, an indicator for terminating the process, i.e. recognition of the end point of etching, is provided.

Detection of the rise in leakage current, as explained above, when the etching front reaches a previously applied pn-junction 32 within silicon wafer 25, or more generally a zone 32 with inhomogeneous charge carrier density and/or inhomogeneous charge carrier polarity, is universally applicable and is not restricted only to the gas phase etching of silicon with C1F3 or BrF3. Rather, it is also suitable for recognising the end point during plasma etching, when, for example, a cavern, for instance for reasons of accuracy, is intended to be etched to a certain depth and precisely predetermined residual membrane thickness using anisotropic plasma etching in accordance with DE 42 41 045 C1. In this case, naturally, although reaching the pn-junction 32 does not lead to an automatic end to etching at the e-doped epitaxial layer 31, the sudden rise in the leakage current due to the "damaged" or etched pn-junction, i. e. zone 32, in the circuit explained above, can also be used as a criterion for terminating the etching process.

Besides, it is an advantage, in the previously explained plasma etching process, when this has previously been optimised with regard to setting up the best possible degree of uniformity over the entire surface of the silicon wafer 25, as is described, for example, in patent application PCT/DE 01/01031, in order to reach the etching target as simultaneously as possible over all of the surface of silicon wafer 25.

Overall, using the previously explained process, it is now possible to control reaching the etching target no longer only by the process time, but to use the blocking current over pn-junction 32 in silicon wafer 25 as a clearly detectable termination criterion.

Claims (11)

1. Claims 1. A process for etching a semiconductor, in particular a silicon

   wafer, with a gaseous etching medium, wherein during etching the rate of at least regional erosion of the semiconductor is adjusted or changed by an especially localised adjustment of the polarity and/or the density of free charge carriers in the semiconductor.
2. 2. A process according to claim 1, wherein the rate of the at least regional erosion of the semiconductor is adjusted or changed by means of a zone with inhomogeneous charge carrier density and/or inhomogeneous charge carrier polarity, in particular a pn-junction, subjected to an electric voltage and present in or induced in the semiconductor (30, 31).
3. 3. A process according to claim 1, wherein the silicon wafer is etched with gaseous C1F3 and/or gaseous BrF3.
4. 4. A process according to any one of the preceding claims, wherein during etching, an electric current induced by the electric voltage in the zone is measured and reaching the zone in the semiconductor is determined from a change in this electric current.
5. 5. A process according to any one of the preceding claims, wherein a direct voltage is used as the electric voltage, this being polarised in such a way that the zone designed as a pn-junction is blocked and that a blocking current or leakage current of the pn-junction is measured as the electric current.
6. 6. A process according to claim 4 or 5, wherein the change in the electric current is used to recognize an end point, a material junction or an interface in the semiconductor.
7. 7. A device for performing a process according to any one of the preceding claims, with a substrate electrode located in an etching chamber and agents for etching a semiconductor which can be held by the substrate electrode wherein the substrate electrode has contact agents and is connected to electrical components by means of which, during etching, a zone with inhomogeneous charge carrier density and/or charge carrier polarity present in the semiconductor can be subjected to an electric voltage and an electric current induced in the zone by the electric voltage can be measured.
8. 8. A device according to claim 7, wherein a change, in particular a rise, in the electric current can be detected on reaching the zone designed as a pn-junction, as a result of the etching process, using the electrical components.
9. 9. A device according to claim 8, wherein the substrate electrode has contact springs or contact tips with which, on the one hand, an e-doped region and, on the other hand, a p-doped region of the semiconductor held by the substrate electrode can make contact.
10. 10. A process for etching a semiconductor substantially as herein described with reference to the accompanying drawing.
11. 11. A device for etching a semiconductor substantially as herein described with reference to the accompanying drawings.